919 lines · c
1// SPDX-License-Identifier: GPL-2.02 3/*4 * Copyright 2016-2018 HabanaLabs, Ltd.5 * All Rights Reserved.6 */7 8#include "gaudiP.h"9#include "../include/gaudi/gaudi_coresight.h"10#include "../include/gaudi/asic_reg/gaudi_regs.h"11#include "../include/gaudi/gaudi_masks.h"12#include "../include/gaudi/gaudi_reg_map.h"13 14#include <uapi/drm/habanalabs_accel.h>15 16#define SPMU_SECTION_SIZE MME0_ACC_SPMU_MAX_OFFSET17#define SPMU_EVENT_TYPES_OFFSET 0x40018#define SPMU_MAX_COUNTERS 619 20static u64 debug_stm_regs[GAUDI_STM_LAST + 1] = {21 [GAUDI_STM_MME0_ACC] = mmMME0_ACC_STM_BASE,22 [GAUDI_STM_MME0_SBAB] = mmMME0_SBAB_STM_BASE,23 [GAUDI_STM_MME0_CTRL] = mmMME0_CTRL_STM_BASE,24 [GAUDI_STM_MME1_ACC] = mmMME1_ACC_STM_BASE,25 [GAUDI_STM_MME1_SBAB] = mmMME1_SBAB_STM_BASE,26 [GAUDI_STM_MME1_CTRL] = mmMME1_CTRL_STM_BASE,27 [GAUDI_STM_MME2_ACC] = mmMME2_ACC_STM_BASE,28 [GAUDI_STM_MME2_SBAB] = mmMME2_SBAB_STM_BASE,29 [GAUDI_STM_MME2_CTRL] = mmMME2_CTRL_STM_BASE,30 [GAUDI_STM_MME3_ACC] = mmMME3_ACC_STM_BASE,31 [GAUDI_STM_MME3_SBAB] = mmMME3_SBAB_STM_BASE,32 [GAUDI_STM_MME3_CTRL] = mmMME3_CTRL_STM_BASE,33 [GAUDI_STM_DMA_IF_W_S] = mmDMA_IF_W_S_STM_BASE,34 [GAUDI_STM_DMA_IF_E_S] = mmDMA_IF_E_S_STM_BASE,35 [GAUDI_STM_DMA_IF_W_N] = mmDMA_IF_W_N_STM_BASE,36 [GAUDI_STM_DMA_IF_E_N] = mmDMA_IF_E_N_STM_BASE,37 [GAUDI_STM_CPU] = mmCPU_STM_BASE,38 [GAUDI_STM_DMA_CH_0_CS] = mmDMA_CH_0_CS_STM_BASE,39 [GAUDI_STM_DMA_CH_1_CS] = mmDMA_CH_1_CS_STM_BASE,40 [GAUDI_STM_DMA_CH_2_CS] = mmDMA_CH_2_CS_STM_BASE,41 [GAUDI_STM_DMA_CH_3_CS] = mmDMA_CH_3_CS_STM_BASE,42 [GAUDI_STM_DMA_CH_4_CS] = mmDMA_CH_4_CS_STM_BASE,43 [GAUDI_STM_DMA_CH_5_CS] = mmDMA_CH_5_CS_STM_BASE,44 [GAUDI_STM_DMA_CH_6_CS] = mmDMA_CH_6_CS_STM_BASE,45 [GAUDI_STM_DMA_CH_7_CS] = mmDMA_CH_7_CS_STM_BASE,46 [GAUDI_STM_PCIE] = mmPCIE_STM_BASE,47 [GAUDI_STM_MMU_CS] = mmMMU_CS_STM_BASE,48 [GAUDI_STM_PSOC] = mmPSOC_STM_BASE,49 [GAUDI_STM_NIC0_0] = mmSTM_0_NIC0_DBG_BASE,50 [GAUDI_STM_NIC0_1] = mmSTM_1_NIC0_DBG_BASE,51 [GAUDI_STM_NIC1_0] = mmSTM_0_NIC1_DBG_BASE,52 [GAUDI_STM_NIC1_1] = mmSTM_1_NIC1_DBG_BASE,53 [GAUDI_STM_NIC2_0] = mmSTM_0_NIC2_DBG_BASE,54 [GAUDI_STM_NIC2_1] = mmSTM_1_NIC2_DBG_BASE,55 [GAUDI_STM_NIC3_0] = mmSTM_0_NIC3_DBG_BASE,56 [GAUDI_STM_NIC3_1] = mmSTM_1_NIC3_DBG_BASE,57 [GAUDI_STM_NIC4_0] = mmSTM_0_NIC4_DBG_BASE,58 [GAUDI_STM_NIC4_1] = mmSTM_1_NIC4_DBG_BASE,59 [GAUDI_STM_TPC0_EML] = mmTPC0_EML_STM_BASE,60 [GAUDI_STM_TPC1_EML] = mmTPC1_EML_STM_BASE,61 [GAUDI_STM_TPC2_EML] = mmTPC2_EML_STM_BASE,62 [GAUDI_STM_TPC3_EML] = mmTPC3_EML_STM_BASE,63 [GAUDI_STM_TPC4_EML] = mmTPC4_EML_STM_BASE,64 [GAUDI_STM_TPC5_EML] = mmTPC5_EML_STM_BASE,65 [GAUDI_STM_TPC6_EML] = mmTPC6_EML_STM_BASE,66 [GAUDI_STM_TPC7_EML] = mmTPC7_EML_STM_BASE67};68 69static u64 debug_etf_regs[GAUDI_ETF_LAST + 1] = {70 [GAUDI_ETF_MME0_ACC] = mmMME0_ACC_ETF_BASE,71 [GAUDI_ETF_MME0_SBAB] = mmMME0_SBAB_ETF_BASE,72 [GAUDI_ETF_MME0_CTRL] = mmMME0_CTRL_ETF_BASE,73 [GAUDI_ETF_MME1_ACC] = mmMME1_ACC_ETF_BASE,74 [GAUDI_ETF_MME1_SBAB] = mmMME1_SBAB_ETF_BASE,75 [GAUDI_ETF_MME1_CTRL] = mmMME1_CTRL_ETF_BASE,76 [GAUDI_ETF_MME2_ACC] = mmMME2_MME2_ACC_ETF_BASE,77 [GAUDI_ETF_MME2_SBAB] = mmMME2_SBAB_ETF_BASE,78 [GAUDI_ETF_MME2_CTRL] = mmMME2_CTRL_ETF_BASE,79 [GAUDI_ETF_MME3_ACC] = mmMME3_ACC_ETF_BASE,80 [GAUDI_ETF_MME3_SBAB] = mmMME3_SBAB_ETF_BASE,81 [GAUDI_ETF_MME3_CTRL] = mmMME3_CTRL_ETF_BASE,82 [GAUDI_ETF_DMA_IF_W_S] = mmDMA_IF_W_S_ETF_BASE,83 [GAUDI_ETF_DMA_IF_E_S] = mmDMA_IF_E_S_ETF_BASE,84 [GAUDI_ETF_DMA_IF_W_N] = mmDMA_IF_W_N_ETF_BASE,85 [GAUDI_ETF_DMA_IF_E_N] = mmDMA_IF_E_N_ETF_BASE,86 [GAUDI_ETF_CPU_0] = mmCPU_ETF_0_BASE,87 [GAUDI_ETF_CPU_1] = mmCPU_ETF_1_BASE,88 [GAUDI_ETF_CPU_TRACE] = mmCPU_ETF_TRACE_BASE,89 [GAUDI_ETF_DMA_CH_0_CS] = mmDMA_CH_0_CS_ETF_BASE,90 [GAUDI_ETF_DMA_CH_1_CS] = mmDMA_CH_1_CS_ETF_BASE,91 [GAUDI_ETF_DMA_CH_2_CS] = mmDMA_CH_2_CS_ETF_BASE,92 [GAUDI_ETF_DMA_CH_3_CS] = mmDMA_CH_3_CS_ETF_BASE,93 [GAUDI_ETF_DMA_CH_4_CS] = mmDMA_CH_4_CS_ETF_BASE,94 [GAUDI_ETF_DMA_CH_5_CS] = mmDMA_CH_5_CS_ETF_BASE,95 [GAUDI_ETF_DMA_CH_6_CS] = mmDMA_CH_6_CS_ETF_BASE,96 [GAUDI_ETF_DMA_CH_7_CS] = mmDMA_CH_7_CS_ETF_BASE,97 [GAUDI_ETF_PCIE] = mmPCIE_ETF_BASE,98 [GAUDI_ETF_MMU_CS] = mmMMU_CS_ETF_BASE,99 [GAUDI_ETF_PSOC] = mmPSOC_ETF_BASE,100 [GAUDI_ETF_NIC0_0] = mmETF_0_NIC0_DBG_BASE,101 [GAUDI_ETF_NIC0_1] = mmETF_1_NIC0_DBG_BASE,102 [GAUDI_ETF_NIC1_0] = mmETF_0_NIC1_DBG_BASE,103 [GAUDI_ETF_NIC1_1] = mmETF_1_NIC1_DBG_BASE,104 [GAUDI_ETF_NIC2_0] = mmETF_0_NIC2_DBG_BASE,105 [GAUDI_ETF_NIC2_1] = mmETF_1_NIC2_DBG_BASE,106 [GAUDI_ETF_NIC3_0] = mmETF_0_NIC3_DBG_BASE,107 [GAUDI_ETF_NIC3_1] = mmETF_1_NIC3_DBG_BASE,108 [GAUDI_ETF_NIC4_0] = mmETF_0_NIC4_DBG_BASE,109 [GAUDI_ETF_NIC4_1] = mmETF_1_NIC4_DBG_BASE,110 [GAUDI_ETF_TPC0_EML] = mmTPC0_EML_ETF_BASE,111 [GAUDI_ETF_TPC1_EML] = mmTPC1_EML_ETF_BASE,112 [GAUDI_ETF_TPC2_EML] = mmTPC2_EML_ETF_BASE,113 [GAUDI_ETF_TPC3_EML] = mmTPC3_EML_ETF_BASE,114 [GAUDI_ETF_TPC4_EML] = mmTPC4_EML_ETF_BASE,115 [GAUDI_ETF_TPC5_EML] = mmTPC5_EML_ETF_BASE,116 [GAUDI_ETF_TPC6_EML] = mmTPC6_EML_ETF_BASE,117 [GAUDI_ETF_TPC7_EML] = mmTPC7_EML_ETF_BASE118};119 120static u64 debug_funnel_regs[GAUDI_FUNNEL_LAST + 1] = {121 [GAUDI_FUNNEL_MME0_ACC] = mmMME0_ACC_FUNNEL_BASE,122 [GAUDI_FUNNEL_MME1_ACC] = mmMME1_ACC_FUNNEL_BASE,123 [GAUDI_FUNNEL_MME2_ACC] = mmMME2_ACC_FUNNEL_BASE,124 [GAUDI_FUNNEL_MME3_ACC] = mmMME3_ACC_FUNNEL_BASE,125 [GAUDI_FUNNEL_SRAM_Y0_X0] = mmSRAM_Y0_X0_FUNNEL_BASE,126 [GAUDI_FUNNEL_SRAM_Y0_X1] = mmSRAM_Y0_X1_FUNNEL_BASE,127 [GAUDI_FUNNEL_SRAM_Y0_X2] = mmSRAM_Y0_X2_FUNNEL_BASE,128 [GAUDI_FUNNEL_SRAM_Y0_X3] = mmSRAM_Y0_X3_FUNNEL_BASE,129 [GAUDI_FUNNEL_SRAM_Y0_X4] = mmSRAM_Y0_X4_FUNNEL_BASE,130 [GAUDI_FUNNEL_SRAM_Y0_X5] = mmSRAM_Y0_X5_FUNNEL_BASE,131 [GAUDI_FUNNEL_SRAM_Y0_X6] = mmSRAM_Y0_X6_FUNNEL_BASE,132 [GAUDI_FUNNEL_SRAM_Y0_X7] = mmSRAM_Y0_X7_FUNNEL_BASE,133 [GAUDI_FUNNEL_SRAM_Y1_X0] = mmSRAM_Y1_X0_FUNNEL_BASE,134 [GAUDI_FUNNEL_SRAM_Y1_X1] = mmSRAM_Y1_X1_FUNNEL_BASE,135 [GAUDI_FUNNEL_SRAM_Y1_X2] = mmSRAM_Y1_X2_FUNNEL_BASE,136 [GAUDI_FUNNEL_SRAM_Y1_X3] = mmSRAM_Y1_X3_FUNNEL_BASE,137 [GAUDI_FUNNEL_SRAM_Y1_X4] = mmSRAM_Y1_X4_FUNNEL_BASE,138 [GAUDI_FUNNEL_SRAM_Y1_X5] = mmSRAM_Y1_X5_FUNNEL_BASE,139 [GAUDI_FUNNEL_SRAM_Y1_X6] = mmSRAM_Y1_X6_FUNNEL_BASE,140 [GAUDI_FUNNEL_SRAM_Y1_X7] = mmSRAM_Y1_X7_FUNNEL_BASE,141 [GAUDI_FUNNEL_SRAM_Y2_X0] = mmSRAM_Y2_X0_FUNNEL_BASE,142 [GAUDI_FUNNEL_SRAM_Y2_X1] = mmSRAM_Y2_X1_FUNNEL_BASE,143 [GAUDI_FUNNEL_SRAM_Y2_X2] = mmSRAM_Y2_X2_FUNNEL_BASE,144 [GAUDI_FUNNEL_SRAM_Y2_X3] = mmSRAM_Y2_X3_FUNNEL_BASE,145 [GAUDI_FUNNEL_SRAM_Y2_X4] = mmSRAM_Y2_X4_FUNNEL_BASE,146 [GAUDI_FUNNEL_SRAM_Y2_X5] = mmSRAM_Y2_X5_FUNNEL_BASE,147 [GAUDI_FUNNEL_SRAM_Y2_X6] = mmSRAM_Y2_X6_FUNNEL_BASE,148 [GAUDI_FUNNEL_SRAM_Y2_X7] = mmSRAM_Y2_X7_FUNNEL_BASE,149 [GAUDI_FUNNEL_SRAM_Y3_X0] = mmSRAM_Y3_X0_FUNNEL_BASE,150 [GAUDI_FUNNEL_SRAM_Y3_X1] = mmSRAM_Y3_X1_FUNNEL_BASE,151 [GAUDI_FUNNEL_SRAM_Y3_X2] = mmSRAM_Y3_X2_FUNNEL_BASE,152 [GAUDI_FUNNEL_SRAM_Y3_X4] = mmSRAM_Y3_X4_FUNNEL_BASE,153 [GAUDI_FUNNEL_SRAM_Y3_X3] = mmSRAM_Y3_X3_FUNNEL_BASE,154 [GAUDI_FUNNEL_SRAM_Y3_X5] = mmSRAM_Y3_X5_FUNNEL_BASE,155 [GAUDI_FUNNEL_SRAM_Y3_X6] = mmSRAM_Y3_X6_FUNNEL_BASE,156 [GAUDI_FUNNEL_SRAM_Y3_X7] = mmSRAM_Y3_X7_FUNNEL_BASE,157 [GAUDI_FUNNEL_SIF_0] = mmSIF_FUNNEL_0_BASE,158 [GAUDI_FUNNEL_SIF_1] = mmSIF_FUNNEL_1_BASE,159 [GAUDI_FUNNEL_SIF_2] = mmSIF_FUNNEL_2_BASE,160 [GAUDI_FUNNEL_SIF_3] = mmSIF_FUNNEL_3_BASE,161 [GAUDI_FUNNEL_SIF_4] = mmSIF_FUNNEL_4_BASE,162 [GAUDI_FUNNEL_SIF_5] = mmSIF_FUNNEL_5_BASE,163 [GAUDI_FUNNEL_SIF_6] = mmSIF_FUNNEL_6_BASE,164 [GAUDI_FUNNEL_SIF_7] = mmSIF_FUNNEL_7_BASE,165 [GAUDI_FUNNEL_NIF_0] = mmNIF_FUNNEL_0_BASE,166 [GAUDI_FUNNEL_NIF_1] = mmNIF_FUNNEL_1_BASE,167 [GAUDI_FUNNEL_NIF_2] = mmNIF_FUNNEL_2_BASE,168 [GAUDI_FUNNEL_NIF_3] = mmNIF_FUNNEL_3_BASE,169 [GAUDI_FUNNEL_NIF_4] = mmNIF_FUNNEL_4_BASE,170 [GAUDI_FUNNEL_NIF_5] = mmNIF_FUNNEL_5_BASE,171 [GAUDI_FUNNEL_NIF_6] = mmNIF_FUNNEL_6_BASE,172 [GAUDI_FUNNEL_NIF_7] = mmNIF_FUNNEL_7_BASE,173 [GAUDI_FUNNEL_DMA_IF_W_S] = mmDMA_IF_W_S_FUNNEL_BASE,174 [GAUDI_FUNNEL_DMA_IF_E_S] = mmDMA_IF_E_S_FUNNEL_BASE,175 [GAUDI_FUNNEL_DMA_IF_W_N] = mmDMA_IF_W_N_FUNNEL_BASE,176 [GAUDI_FUNNEL_DMA_IF_E_N] = mmDMA_IF_E_N_FUNNEL_BASE,177 [GAUDI_FUNNEL_CPU] = mmCPU_FUNNEL_BASE,178 [GAUDI_FUNNEL_NIC_TPC_W_S] = mmNIC_TPC_FUNNEL_W_S_BASE,179 [GAUDI_FUNNEL_NIC_TPC_E_S] = mmNIC_TPC_FUNNEL_E_S_BASE,180 [GAUDI_FUNNEL_NIC_TPC_W_N] = mmNIC_TPC_FUNNEL_W_N_BASE,181 [GAUDI_FUNNEL_NIC_TPC_E_N] = mmNIC_TPC_FUNNEL_E_N_BASE,182 [GAUDI_FUNNEL_PCIE] = mmPCIE_FUNNEL_BASE,183 [GAUDI_FUNNEL_PSOC] = mmPSOC_FUNNEL_BASE,184 [GAUDI_FUNNEL_NIC0] = mmFUNNEL_NIC0_DBG_BASE,185 [GAUDI_FUNNEL_NIC1] = mmFUNNEL_NIC1_DBG_BASE,186 [GAUDI_FUNNEL_NIC2] = mmFUNNEL_NIC2_DBG_BASE,187 [GAUDI_FUNNEL_NIC3] = mmFUNNEL_NIC3_DBG_BASE,188 [GAUDI_FUNNEL_NIC4] = mmFUNNEL_NIC4_DBG_BASE,189 [GAUDI_FUNNEL_TPC0_EML] = mmTPC0_EML_FUNNEL_BASE,190 [GAUDI_FUNNEL_TPC1_EML] = mmTPC1_EML_FUNNEL_BASE,191 [GAUDI_FUNNEL_TPC2_EML] = mmTPC2_EML_FUNNEL_BASE,192 [GAUDI_FUNNEL_TPC3_EML] = mmTPC3_EML_FUNNEL_BASE,193 [GAUDI_FUNNEL_TPC4_EML] = mmTPC4_EML_FUNNEL_BASE,194 [GAUDI_FUNNEL_TPC5_EML] = mmTPC5_EML_FUNNEL_BASE,195 [GAUDI_FUNNEL_TPC6_EML] = mmTPC6_EML_FUNNEL_BASE,196 [GAUDI_FUNNEL_TPC7_EML] = mmTPC7_EML_FUNNEL_BASE197};198 199static u64 debug_bmon_regs[GAUDI_BMON_LAST + 1] = {200 [GAUDI_BMON_MME0_ACC_0] = mmMME0_ACC_BMON0_BASE,201 [GAUDI_BMON_MME0_SBAB_0] = mmMME0_SBAB_BMON0_BASE,202 [GAUDI_BMON_MME0_SBAB_1] = mmMME0_SBAB_BMON1_BASE,203 [GAUDI_BMON_MME0_CTRL_0] = mmMME0_CTRL_BMON0_BASE,204 [GAUDI_BMON_MME0_CTRL_1] = mmMME0_CTRL_BMON1_BASE,205 [GAUDI_BMON_MME1_ACC_0] = mmMME1_ACC_BMON0_BASE,206 [GAUDI_BMON_MME1_SBAB_0] = mmMME1_SBAB_BMON0_BASE,207 [GAUDI_BMON_MME1_SBAB_1] = mmMME1_SBAB_BMON1_BASE,208 [GAUDI_BMON_MME1_CTRL_0] = mmMME1_CTRL_BMON0_BASE,209 [GAUDI_BMON_MME1_CTRL_1] = mmMME1_CTRL_BMON1_BASE,210 [GAUDI_BMON_MME2_ACC_0] = mmMME2_ACC_BMON0_BASE,211 [GAUDI_BMON_MME2_SBAB_0] = mmMME2_SBAB_BMON0_BASE,212 [GAUDI_BMON_MME2_SBAB_1] = mmMME2_SBAB_BMON1_BASE,213 [GAUDI_BMON_MME2_CTRL_0] = mmMME2_CTRL_BMON0_BASE,214 [GAUDI_BMON_MME2_CTRL_1] = mmMME2_CTRL_BMON1_BASE,215 [GAUDI_BMON_MME3_ACC_0] = mmMME3_ACC_BMON0_BASE,216 [GAUDI_BMON_MME3_SBAB_0] = mmMME3_SBAB_BMON0_BASE,217 [GAUDI_BMON_MME3_SBAB_1] = mmMME3_SBAB_BMON1_BASE,218 [GAUDI_BMON_MME3_CTRL_0] = mmMME3_CTRL_BMON0_BASE,219 [GAUDI_BMON_MME3_CTRL_1] = mmMME3_CTRL_BMON1_BASE,220 [GAUDI_BMON_DMA_IF_W_S_SOB_WR] = mmDMA_IF_W_S_SOB_WR_BMON_BASE,221 [GAUDI_BMON_DMA_IF_W_S_0_WR] = mmDMA_IF_W_S_HBM0_WR_BMON_BASE,222 [GAUDI_BMON_DMA_IF_W_S_0_RD] = mmDMA_IF_W_S_HBM0_RD_BMON_BASE,223 [GAUDI_BMON_DMA_IF_W_S_1_WR] = mmDMA_IF_W_S_HBM1_WR_BMON_BASE,224 [GAUDI_BMON_DMA_IF_W_S_1_RD] = mmDMA_IF_W_S_HBM1_RD_BMON_BASE,225 [GAUDI_BMON_DMA_IF_E_S_SOB_WR] = mmDMA_IF_E_S_SOB_WR_BMON_BASE,226 [GAUDI_BMON_DMA_IF_E_S_0_WR] = mmDMA_IF_E_S_HBM0_WR_BMON_BASE,227 [GAUDI_BMON_DMA_IF_E_S_0_RD] = mmDMA_IF_E_S_HBM0_RD_BMON_BASE,228 [GAUDI_BMON_DMA_IF_E_S_1_WR] = mmDMA_IF_E_S_HBM1_WR_BMON_BASE,229 [GAUDI_BMON_DMA_IF_E_S_1_RD] = mmDMA_IF_E_S_HBM1_RD_BMON_BASE,230 [GAUDI_BMON_DMA_IF_W_N_SOB_WR] = mmDMA_IF_W_N_SOB_WR_BMON_BASE,231 [GAUDI_BMON_DMA_IF_W_N_HBM0_WR] = mmDMA_IF_W_N_HBM0_WR_BMON_BASE,232 [GAUDI_BMON_DMA_IF_W_N_HBM0_RD] = mmDMA_IF_W_N_HBM0_RD_BMON_BASE,233 [GAUDI_BMON_DMA_IF_W_N_HBM1_WR] = mmDMA_IF_W_N_HBM1_WR_BMON_BASE,234 [GAUDI_BMON_DMA_IF_W_N_HBM1_RD] = mmDMA_IF_W_N_HBM1_RD_BMON_BASE,235 [GAUDI_BMON_DMA_IF_E_N_SOB_WR] = mmDMA_IF_E_N_SOB_WR_BMON_BASE,236 [GAUDI_BMON_DMA_IF_E_N_HBM0_WR] = mmDMA_IF_E_N_HBM0_WR_BMON_BASE,237 [GAUDI_BMON_DMA_IF_E_N_HBM0_RD] = mmDMA_IF_E_N_HBM0_RD_BMON_BASE,238 [GAUDI_BMON_DMA_IF_E_N_HBM1_WR] = mmDMA_IF_E_N_HBM1_WR_BMON_BASE,239 [GAUDI_BMON_DMA_IF_E_N_HBM1_RD] = mmDMA_IF_E_N_HBM1_RD_BMON_BASE,240 [GAUDI_BMON_CPU_WR] = mmCPU_WR_BMON_BASE,241 [GAUDI_BMON_CPU_RD] = mmCPU_RD_BMON_BASE,242 [GAUDI_BMON_DMA_CH_0_0] = mmDMA_CH_0_BMON_0_BASE,243 [GAUDI_BMON_DMA_CH_0_1] = mmDMA_CH_0_BMON_1_BASE,244 [GAUDI_BMON_DMA_CH_1_0] = mmDMA_CH_1_BMON_0_BASE,245 [GAUDI_BMON_DMA_CH_1_1] = mmDMA_CH_1_BMON_1_BASE,246 [GAUDI_BMON_DMA_CH_2_0] = mmDMA_CH_2_BMON_0_BASE,247 [GAUDI_BMON_DMA_CH_2_1] = mmDMA_CH_2_BMON_1_BASE,248 [GAUDI_BMON_DMA_CH_3_0] = mmDMA_CH_3_BMON_0_BASE,249 [GAUDI_BMON_DMA_CH_3_1] = mmDMA_CH_3_BMON_1_BASE,250 [GAUDI_BMON_DMA_CH_4_0] = mmDMA_CH_4_BMON_0_BASE,251 [GAUDI_BMON_DMA_CH_4_1] = mmDMA_CH_4_BMON_1_BASE,252 [GAUDI_BMON_DMA_CH_5_0] = mmDMA_CH_5_BMON_0_BASE,253 [GAUDI_BMON_DMA_CH_5_1] = mmDMA_CH_5_BMON_1_BASE,254 [GAUDI_BMON_DMA_CH_6_0] = mmDMA_CH_6_BMON_0_BASE,255 [GAUDI_BMON_DMA_CH_6_1] = mmDMA_CH_6_BMON_1_BASE,256 [GAUDI_BMON_DMA_CH_7_0] = mmDMA_CH_7_BMON_0_BASE,257 [GAUDI_BMON_DMA_CH_7_1] = mmDMA_CH_7_BMON_1_BASE,258 [GAUDI_BMON_PCIE_MSTR_WR] = mmPCIE_BMON_MSTR_WR_BASE,259 [GAUDI_BMON_PCIE_MSTR_RD] = mmPCIE_BMON_MSTR_RD_BASE,260 [GAUDI_BMON_PCIE_SLV_WR] = mmPCIE_BMON_SLV_WR_BASE,261 [GAUDI_BMON_PCIE_SLV_RD] = mmPCIE_BMON_SLV_RD_BASE,262 [GAUDI_BMON_MMU_0] = mmMMU_BMON_0_BASE,263 [GAUDI_BMON_MMU_1] = mmMMU_BMON_1_BASE,264 [GAUDI_BMON_NIC0_0] = mmBMON0_NIC0_DBG_BASE,265 [GAUDI_BMON_NIC0_1] = mmBMON1_NIC0_DBG_BASE,266 [GAUDI_BMON_NIC0_2] = mmBMON2_NIC0_DBG_BASE,267 [GAUDI_BMON_NIC0_3] = mmBMON3_NIC0_DBG_BASE,268 [GAUDI_BMON_NIC0_4] = mmBMON4_NIC0_DBG_BASE,269 [GAUDI_BMON_NIC1_0] = mmBMON0_NIC1_DBG_BASE,270 [GAUDI_BMON_NIC1_1] = mmBMON1_NIC1_DBG_BASE,271 [GAUDI_BMON_NIC1_2] = mmBMON2_NIC1_DBG_BASE,272 [GAUDI_BMON_NIC1_3] = mmBMON3_NIC1_DBG_BASE,273 [GAUDI_BMON_NIC1_4] = mmBMON4_NIC1_DBG_BASE,274 [GAUDI_BMON_NIC2_0] = mmBMON0_NIC2_DBG_BASE,275 [GAUDI_BMON_NIC2_1] = mmBMON1_NIC2_DBG_BASE,276 [GAUDI_BMON_NIC2_2] = mmBMON2_NIC2_DBG_BASE,277 [GAUDI_BMON_NIC2_3] = mmBMON3_NIC2_DBG_BASE,278 [GAUDI_BMON_NIC2_4] = mmBMON4_NIC2_DBG_BASE,279 [GAUDI_BMON_NIC3_0] = mmBMON0_NIC3_DBG_BASE,280 [GAUDI_BMON_NIC3_1] = mmBMON1_NIC3_DBG_BASE,281 [GAUDI_BMON_NIC3_2] = mmBMON2_NIC3_DBG_BASE,282 [GAUDI_BMON_NIC3_3] = mmBMON3_NIC3_DBG_BASE,283 [GAUDI_BMON_NIC3_4] = mmBMON4_NIC3_DBG_BASE,284 [GAUDI_BMON_NIC4_0] = mmBMON0_NIC4_DBG_BASE,285 [GAUDI_BMON_NIC4_1] = mmBMON1_NIC4_DBG_BASE,286 [GAUDI_BMON_NIC4_2] = mmBMON2_NIC4_DBG_BASE,287 [GAUDI_BMON_NIC4_3] = mmBMON3_NIC4_DBG_BASE,288 [GAUDI_BMON_NIC4_4] = mmBMON4_NIC4_DBG_BASE,289 [GAUDI_BMON_TPC0_EML_0] = mmTPC0_EML_BUSMON_0_BASE,290 [GAUDI_BMON_TPC0_EML_1] = mmTPC0_EML_BUSMON_1_BASE,291 [GAUDI_BMON_TPC0_EML_2] = mmTPC0_EML_BUSMON_2_BASE,292 [GAUDI_BMON_TPC0_EML_3] = mmTPC0_EML_BUSMON_3_BASE,293 [GAUDI_BMON_TPC1_EML_0] = mmTPC1_EML_BUSMON_0_BASE,294 [GAUDI_BMON_TPC1_EML_1] = mmTPC1_EML_BUSMON_1_BASE,295 [GAUDI_BMON_TPC1_EML_2] = mmTPC1_EML_BUSMON_2_BASE,296 [GAUDI_BMON_TPC1_EML_3] = mmTPC1_EML_BUSMON_3_BASE,297 [GAUDI_BMON_TPC2_EML_0] = mmTPC2_EML_BUSMON_0_BASE,298 [GAUDI_BMON_TPC2_EML_1] = mmTPC2_EML_BUSMON_1_BASE,299 [GAUDI_BMON_TPC2_EML_2] = mmTPC2_EML_BUSMON_2_BASE,300 [GAUDI_BMON_TPC2_EML_3] = mmTPC2_EML_BUSMON_3_BASE,301 [GAUDI_BMON_TPC3_EML_0] = mmTPC3_EML_BUSMON_0_BASE,302 [GAUDI_BMON_TPC3_EML_1] = mmTPC3_EML_BUSMON_1_BASE,303 [GAUDI_BMON_TPC3_EML_2] = mmTPC3_EML_BUSMON_2_BASE,304 [GAUDI_BMON_TPC3_EML_3] = mmTPC3_EML_BUSMON_3_BASE,305 [GAUDI_BMON_TPC4_EML_0] = mmTPC4_EML_BUSMON_0_BASE,306 [GAUDI_BMON_TPC4_EML_1] = mmTPC4_EML_BUSMON_1_BASE,307 [GAUDI_BMON_TPC4_EML_2] = mmTPC4_EML_BUSMON_2_BASE,308 [GAUDI_BMON_TPC4_EML_3] = mmTPC4_EML_BUSMON_3_BASE,309 [GAUDI_BMON_TPC5_EML_0] = mmTPC5_EML_BUSMON_0_BASE,310 [GAUDI_BMON_TPC5_EML_1] = mmTPC5_EML_BUSMON_1_BASE,311 [GAUDI_BMON_TPC5_EML_2] = mmTPC5_EML_BUSMON_2_BASE,312 [GAUDI_BMON_TPC5_EML_3] = mmTPC5_EML_BUSMON_3_BASE,313 [GAUDI_BMON_TPC6_EML_0] = mmTPC6_EML_BUSMON_0_BASE,314 [GAUDI_BMON_TPC6_EML_1] = mmTPC6_EML_BUSMON_1_BASE,315 [GAUDI_BMON_TPC6_EML_2] = mmTPC6_EML_BUSMON_2_BASE,316 [GAUDI_BMON_TPC6_EML_3] = mmTPC6_EML_BUSMON_3_BASE,317 [GAUDI_BMON_TPC7_EML_0] = mmTPC7_EML_BUSMON_0_BASE,318 [GAUDI_BMON_TPC7_EML_1] = mmTPC7_EML_BUSMON_1_BASE,319 [GAUDI_BMON_TPC7_EML_2] = mmTPC7_EML_BUSMON_2_BASE,320 [GAUDI_BMON_TPC7_EML_3] = mmTPC7_EML_BUSMON_3_BASE321};322 323static u64 debug_spmu_regs[GAUDI_SPMU_LAST + 1] = {324 [GAUDI_SPMU_MME0_ACC] = mmMME0_ACC_SPMU_BASE,325 [GAUDI_SPMU_MME0_SBAB] = mmMME0_SBAB_SPMU_BASE,326 [GAUDI_SPMU_MME0_CTRL] = mmMME0_CTRL_SPMU_BASE,327 [GAUDI_SPMU_MME1_ACC] = mmMME1_ACC_SPMU_BASE,328 [GAUDI_SPMU_MME1_SBAB] = mmMME1_SBAB_SPMU_BASE,329 [GAUDI_SPMU_MME1_CTRL] = mmMME1_CTRL_SPMU_BASE,330 [GAUDI_SPMU_MME2_MME2_ACC] = mmMME2_ACC_SPMU_BASE,331 [GAUDI_SPMU_MME2_SBAB] = mmMME2_SBAB_SPMU_BASE,332 [GAUDI_SPMU_MME2_CTRL] = mmMME2_CTRL_SPMU_BASE,333 [GAUDI_SPMU_MME3_ACC] = mmMME3_ACC_SPMU_BASE,334 [GAUDI_SPMU_MME3_SBAB] = mmMME3_SBAB_SPMU_BASE,335 [GAUDI_SPMU_MME3_CTRL] = mmMME3_CTRL_SPMU_BASE,336 [GAUDI_SPMU_DMA_CH_0_CS] = mmDMA_CH_0_CS_SPMU_BASE,337 [GAUDI_SPMU_DMA_CH_1_CS] = mmDMA_CH_1_CS_SPMU_BASE,338 [GAUDI_SPMU_DMA_CH_2_CS] = mmDMA_CH_2_CS_SPMU_BASE,339 [GAUDI_SPMU_DMA_CH_3_CS] = mmDMA_CH_3_CS_SPMU_BASE,340 [GAUDI_SPMU_DMA_CH_4_CS] = mmDMA_CH_4_CS_SPMU_BASE,341 [GAUDI_SPMU_DMA_CH_5_CS] = mmDMA_CH_5_CS_SPMU_BASE,342 [GAUDI_SPMU_DMA_CH_6_CS] = mmDMA_CH_6_CS_SPMU_BASE,343 [GAUDI_SPMU_DMA_CH_7_CS] = mmDMA_CH_7_CS_SPMU_BASE,344 [GAUDI_SPMU_PCIE] = mmPCIE_SPMU_BASE,345 [GAUDI_SPMU_MMU_CS] = mmMMU_CS_SPMU_BASE,346 [GAUDI_SPMU_NIC0_0] = mmSPMU_0_NIC0_DBG_BASE,347 [GAUDI_SPMU_NIC0_1] = mmSPMU_1_NIC0_DBG_BASE,348 [GAUDI_SPMU_NIC1_0] = mmSPMU_0_NIC1_DBG_BASE,349 [GAUDI_SPMU_NIC1_1] = mmSPMU_1_NIC1_DBG_BASE,350 [GAUDI_SPMU_NIC2_0] = mmSPMU_0_NIC2_DBG_BASE,351 [GAUDI_SPMU_NIC2_1] = mmSPMU_1_NIC2_DBG_BASE,352 [GAUDI_SPMU_NIC3_0] = mmSPMU_0_NIC3_DBG_BASE,353 [GAUDI_SPMU_NIC3_1] = mmSPMU_1_NIC3_DBG_BASE,354 [GAUDI_SPMU_NIC4_0] = mmSPMU_0_NIC4_DBG_BASE,355 [GAUDI_SPMU_NIC4_1] = mmSPMU_1_NIC4_DBG_BASE,356 [GAUDI_SPMU_TPC0_EML] = mmTPC0_EML_SPMU_BASE,357 [GAUDI_SPMU_TPC1_EML] = mmTPC1_EML_SPMU_BASE,358 [GAUDI_SPMU_TPC2_EML] = mmTPC2_EML_SPMU_BASE,359 [GAUDI_SPMU_TPC3_EML] = mmTPC3_EML_SPMU_BASE,360 [GAUDI_SPMU_TPC4_EML] = mmTPC4_EML_SPMU_BASE,361 [GAUDI_SPMU_TPC5_EML] = mmTPC5_EML_SPMU_BASE,362 [GAUDI_SPMU_TPC6_EML] = mmTPC6_EML_SPMU_BASE,363 [GAUDI_SPMU_TPC7_EML] = mmTPC7_EML_SPMU_BASE364};365 366static int gaudi_coresight_timeout(struct hl_device *hdev, u64 addr,367 int position, bool up)368{369 int rc;370 u32 val;371 372 rc = hl_poll_timeout(373 hdev,374 addr,375 val,376 up ? val & BIT(position) : !(val & BIT(position)),377 1000,378 CORESIGHT_TIMEOUT_USEC);379 380 if (rc) {381 dev_err(hdev->dev,382 "Timeout while waiting for coresight, addr: 0x%llx, position: %d, up: %d\n",383 addr, position, up);384 return -EFAULT;385 }386 387 return 0;388}389 390static int gaudi_config_stm(struct hl_device *hdev,391 struct hl_debug_params *params)392{393 struct hl_debug_params_stm *input;394 u64 base_reg;395 u32 frequency;396 int rc;397 398 if (params->reg_idx >= ARRAY_SIZE(debug_stm_regs)) {399 dev_err(hdev->dev, "Invalid register index in STM\n");400 return -EINVAL;401 }402 403 base_reg = debug_stm_regs[params->reg_idx] - CFG_BASE;404 405 WREG32(base_reg + 0xFB0, CORESIGHT_UNLOCK);406 407 if (params->enable) {408 input = params->input;409 410 if (!input)411 return -EINVAL;412 413 WREG32(base_reg + 0xE80, 0x80004);414 WREG32(base_reg + 0xD64, 7);415 WREG32(base_reg + 0xD60, 0);416 WREG32(base_reg + 0xD00, lower_32_bits(input->he_mask));417 WREG32(base_reg + 0xD60, 1);418 WREG32(base_reg + 0xD00, upper_32_bits(input->he_mask));419 WREG32(base_reg + 0xE70, 0x10);420 WREG32(base_reg + 0xE60, 0);421 WREG32(base_reg + 0xE00, lower_32_bits(input->sp_mask));422 WREG32(base_reg + 0xEF4, input->id);423 WREG32(base_reg + 0xDF4, 0x80);424 frequency = hdev->asic_prop.psoc_timestamp_frequency;425 if (frequency == 0)426 frequency = input->frequency;427 WREG32(base_reg + 0xE8C, frequency);428 WREG32(base_reg + 0xE90, 0x1F00);429 430 /* SW-2176 - SW WA for HW bug */431 if ((CFG_BASE + base_reg) >= mmDMA_CH_0_CS_STM_BASE &&432 (CFG_BASE + base_reg) <= mmDMA_CH_7_CS_STM_BASE) {433 434 WREG32(base_reg + 0xE68, 0xffff8005);435 WREG32(base_reg + 0xE6C, 0x0);436 }437 438 WREG32(base_reg + 0xE80, 0x23 | (input->id << 16));439 } else {440 WREG32(base_reg + 0xE80, 4);441 WREG32(base_reg + 0xD64, 0);442 WREG32(base_reg + 0xD60, 1);443 WREG32(base_reg + 0xD00, 0);444 WREG32(base_reg + 0xD20, 0);445 WREG32(base_reg + 0xD60, 0);446 WREG32(base_reg + 0xE20, 0);447 WREG32(base_reg + 0xE00, 0);448 WREG32(base_reg + 0xDF4, 0x80);449 WREG32(base_reg + 0xE70, 0);450 WREG32(base_reg + 0xE60, 0);451 WREG32(base_reg + 0xE64, 0);452 WREG32(base_reg + 0xE8C, 0);453 454 rc = gaudi_coresight_timeout(hdev, base_reg + 0xE80, 23, false);455 if (rc) {456 dev_err(hdev->dev,457 "Failed to disable STM on timeout, error %d\n",458 rc);459 return rc;460 }461 462 WREG32(base_reg + 0xE80, 4);463 }464 465 return 0;466}467 468static int gaudi_config_etf(struct hl_device *hdev,469 struct hl_debug_params *params)470{471 struct hl_debug_params_etf *input;472 u64 base_reg;473 u32 val;474 int rc;475 476 if (params->reg_idx >= ARRAY_SIZE(debug_etf_regs)) {477 dev_err(hdev->dev, "Invalid register index in ETF\n");478 return -EINVAL;479 }480 481 base_reg = debug_etf_regs[params->reg_idx] - CFG_BASE;482 483 WREG32(base_reg + 0xFB0, CORESIGHT_UNLOCK);484 485 val = RREG32(base_reg + 0x20);486 487 if ((!params->enable && val == 0x0) || (params->enable && val != 0x0))488 return 0;489 490 val = RREG32(base_reg + 0x304);491 val |= 0x1000;492 WREG32(base_reg + 0x304, val);493 val |= 0x40;494 WREG32(base_reg + 0x304, val);495 496 rc = gaudi_coresight_timeout(hdev, base_reg + 0x304, 6, false);497 if (rc) {498 dev_err(hdev->dev,499 "Failed to %s ETF on timeout, error %d\n",500 params->enable ? "enable" : "disable", rc);501 return rc;502 }503 504 rc = gaudi_coresight_timeout(hdev, base_reg + 0xC, 2, true);505 if (rc) {506 dev_err(hdev->dev,507 "Failed to %s ETF on timeout, error %d\n",508 params->enable ? "enable" : "disable", rc);509 return rc;510 }511 512 WREG32(base_reg + 0x20, 0);513 514 if (params->enable) {515 input = params->input;516 517 if (!input)518 return -EINVAL;519 520 WREG32(base_reg + 0x34, 0x3FFC);521 WREG32(base_reg + 0x28, input->sink_mode);522 WREG32(base_reg + 0x304, 0x4001);523 WREG32(base_reg + 0x308, 0xA);524 WREG32(base_reg + 0x20, 1);525 } else {526 WREG32(base_reg + 0x34, 0);527 WREG32(base_reg + 0x28, 0);528 WREG32(base_reg + 0x304, 0);529 }530 531 return 0;532}533 534static bool gaudi_etr_validate_address(struct hl_device *hdev, u64 addr,535 u64 size, bool *is_host)536{537 struct asic_fixed_properties *prop = &hdev->asic_prop;538 struct gaudi_device *gaudi = hdev->asic_specific;539 540 /* maximum address length is 50 bits */541 if (addr >> 50) {542 dev_err(hdev->dev,543 "ETR buffer address shouldn't exceed 50 bits\n");544 return false;545 }546 547 if (addr > (addr + size)) {548 dev_err(hdev->dev,549 "ETR buffer size %llu overflow\n", size);550 return false;551 }552 553 /* PMMU and HPMMU addresses are equal, check only one of them */554 if ((gaudi->hw_cap_initialized & HW_CAP_MMU) &&555 hl_mem_area_inside_range(addr, size,556 prop->pmmu.start_addr,557 prop->pmmu.end_addr)) {558 *is_host = true;559 return true;560 }561 562 if (hl_mem_area_inside_range(addr, size,563 prop->dram_user_base_address,564 prop->dram_end_address))565 return true;566 567 if (hl_mem_area_inside_range(addr, size,568 prop->sram_user_base_address,569 prop->sram_end_address))570 return true;571 572 if (!(gaudi->hw_cap_initialized & HW_CAP_MMU))573 dev_err(hdev->dev, "ETR buffer should be in SRAM/DRAM\n");574 575 return false;576}577 578static int gaudi_config_etr(struct hl_device *hdev,579 struct hl_debug_params *params)580{581 struct hl_debug_params_etr *input;582 u64 msb;583 u32 val;584 int rc;585 586 WREG32(mmPSOC_ETR_LAR, CORESIGHT_UNLOCK);587 588 val = RREG32(mmPSOC_ETR_CTL);589 590 if ((!params->enable && val == 0x0) || (params->enable && val != 0x0))591 return 0;592 593 594 595 val = RREG32(mmPSOC_ETR_FFCR);596 val |= 0x1000;597 WREG32(mmPSOC_ETR_FFCR, val);598 val |= 0x40;599 WREG32(mmPSOC_ETR_FFCR, val);600 601 rc = gaudi_coresight_timeout(hdev, mmPSOC_ETR_FFCR, 6, false);602 if (rc) {603 dev_err(hdev->dev, "Failed to %s ETR on timeout, error %d\n",604 params->enable ? "enable" : "disable", rc);605 return rc;606 }607 608 rc = gaudi_coresight_timeout(hdev, mmPSOC_ETR_STS, 2, true);609 if (rc) {610 dev_err(hdev->dev, "Failed to %s ETR on timeout, error %d\n",611 params->enable ? "enable" : "disable", rc);612 return rc;613 }614 615 WREG32(mmPSOC_ETR_CTL, 0);616 617 if (params->enable) {618 bool is_host = false;619 620 input = params->input;621 622 if (!input)623 return -EINVAL;624 625 if (input->buffer_size == 0) {626 dev_err(hdev->dev,627 "ETR buffer size should be bigger than 0\n");628 return -EINVAL;629 }630 631 if (!gaudi_etr_validate_address(hdev,632 input->buffer_address, input->buffer_size,633 &is_host)) {634 dev_err(hdev->dev, "ETR buffer address is invalid\n");635 return -EINVAL;636 }637 638 msb = upper_32_bits(input->buffer_address) >> 8;639 msb &= PSOC_GLOBAL_CONF_TRACE_ADDR_MSB_MASK;640 WREG32(mmPSOC_GLOBAL_CONF_TRACE_ADDR, msb);641 642 WREG32(mmPSOC_ETR_BUFWM, 0x3FFC);643 WREG32(mmPSOC_ETR_RSZ, input->buffer_size);644 WREG32(mmPSOC_ETR_MODE, input->sink_mode);645 if (!hdev->asic_prop.fw_security_enabled) {646 /* make ETR not privileged */647 val = FIELD_PREP(648 PSOC_ETR_AXICTL_PROTCTRLBIT0_MASK, 0);649 /* make ETR non-secured (inverted logic) */650 val |= FIELD_PREP(651 PSOC_ETR_AXICTL_PROTCTRLBIT1_MASK, 1);652 /*653 * Workaround for H3 #HW-2075 bug: use small data654 * chunks655 */656 val |= FIELD_PREP(PSOC_ETR_AXICTL_WRBURSTLEN_MASK,657 is_host ? 0 : 7);658 WREG32(mmPSOC_ETR_AXICTL, val);659 }660 WREG32(mmPSOC_ETR_DBALO,661 lower_32_bits(input->buffer_address));662 WREG32(mmPSOC_ETR_DBAHI,663 upper_32_bits(input->buffer_address));664 WREG32(mmPSOC_ETR_FFCR, 3);665 WREG32(mmPSOC_ETR_PSCR, 0xA);666 WREG32(mmPSOC_ETR_CTL, 1);667 } else {668 WREG32(mmPSOC_ETR_BUFWM, 0);669 WREG32(mmPSOC_ETR_RSZ, 0x400);670 WREG32(mmPSOC_ETR_DBALO, 0);671 WREG32(mmPSOC_ETR_DBAHI, 0);672 WREG32(mmPSOC_ETR_PSCR, 0);673 WREG32(mmPSOC_ETR_MODE, 0);674 WREG32(mmPSOC_ETR_FFCR, 0);675 676 if (params->output_size >= sizeof(u64)) {677 u32 rwp, rwphi;678 679 /*680 * The trace buffer address is 50 bits wide. The end of681 * the buffer is set in the RWP register (lower 32682 * bits), and in the RWPHI register (upper 8 bits).683 * The 10 msb of the 50-bit address are stored in a684 * global configuration register.685 */686 rwp = RREG32(mmPSOC_ETR_RWP);687 rwphi = RREG32(mmPSOC_ETR_RWPHI) & 0xff;688 msb = RREG32(mmPSOC_GLOBAL_CONF_TRACE_ADDR) &689 PSOC_GLOBAL_CONF_TRACE_ADDR_MSB_MASK;690 *(u64 *) params->output = ((u64) msb << 40) |691 ((u64) rwphi << 32) | rwp;692 }693 }694 695 return 0;696}697 698static int gaudi_config_funnel(struct hl_device *hdev,699 struct hl_debug_params *params)700{701 u64 base_reg;702 703 if (params->reg_idx >= ARRAY_SIZE(debug_funnel_regs)) {704 dev_err(hdev->dev, "Invalid register index in FUNNEL\n");705 return -EINVAL;706 }707 708 base_reg = debug_funnel_regs[params->reg_idx] - CFG_BASE;709 710 WREG32(base_reg + 0xFB0, CORESIGHT_UNLOCK);711 712 WREG32(base_reg, params->enable ? 0x33F : 0);713 714 return 0;715}716 717static int gaudi_config_bmon(struct hl_device *hdev,718 struct hl_debug_params *params)719{720 struct hl_debug_params_bmon *input;721 u64 base_reg;722 723 if (params->reg_idx >= ARRAY_SIZE(debug_bmon_regs)) {724 dev_err(hdev->dev, "Invalid register index in BMON\n");725 return -EINVAL;726 }727 728 base_reg = debug_bmon_regs[params->reg_idx] - CFG_BASE;729 730 WREG32(base_reg + 0x104, 1);731 732 if (params->enable) {733 input = params->input;734 735 if (!input)736 return -EINVAL;737 738 WREG32(base_reg + 0x200, lower_32_bits(input->start_addr0));739 WREG32(base_reg + 0x204, upper_32_bits(input->start_addr0));740 WREG32(base_reg + 0x208, lower_32_bits(input->addr_mask0));741 WREG32(base_reg + 0x20C, upper_32_bits(input->addr_mask0));742 WREG32(base_reg + 0x240, lower_32_bits(input->start_addr1));743 WREG32(base_reg + 0x244, upper_32_bits(input->start_addr1));744 WREG32(base_reg + 0x248, lower_32_bits(input->addr_mask1));745 WREG32(base_reg + 0x24C, upper_32_bits(input->addr_mask1));746 WREG32(base_reg + 0x224, 0);747 WREG32(base_reg + 0x234, 0);748 WREG32(base_reg + 0x30C, input->bw_win);749 WREG32(base_reg + 0x308, input->win_capture);750 WREG32(base_reg + 0x700, 0xA000B00 | (input->id << 12));751 WREG32(base_reg + 0x708, 0xA000A00 | (input->id << 12));752 WREG32(base_reg + 0x70C, 0xA000C00 | (input->id << 12));753 WREG32(base_reg + 0x100, 0x11);754 WREG32(base_reg + 0x304, 0x1);755 } else {756 WREG32(base_reg + 0x200, 0);757 WREG32(base_reg + 0x204, 0);758 WREG32(base_reg + 0x208, 0xFFFFFFFF);759 WREG32(base_reg + 0x20C, 0xFFFFFFFF);760 WREG32(base_reg + 0x240, 0);761 WREG32(base_reg + 0x244, 0);762 WREG32(base_reg + 0x248, 0xFFFFFFFF);763 WREG32(base_reg + 0x24C, 0xFFFFFFFF);764 WREG32(base_reg + 0x224, 0xFFFFFFFF);765 WREG32(base_reg + 0x234, 0x1070F);766 WREG32(base_reg + 0x30C, 0);767 WREG32(base_reg + 0x308, 0xFFFF);768 WREG32(base_reg + 0x700, 0xA000B00);769 WREG32(base_reg + 0x708, 0xA000A00);770 WREG32(base_reg + 0x70C, 0xA000C00);771 WREG32(base_reg + 0x100, 1);772 WREG32(base_reg + 0x304, 0);773 WREG32(base_reg + 0x104, 0);774 }775 776 return 0;777}778 779static int gaudi_config_spmu(struct hl_device *hdev,780 struct hl_debug_params *params)781{782 u64 base_reg;783 struct hl_debug_params_spmu *input = params->input;784 u64 *output;785 u32 output_arr_len;786 u32 events_num;787 u32 overflow_idx;788 u32 cycle_cnt_idx;789 int i;790 791 if (params->reg_idx >= ARRAY_SIZE(debug_spmu_regs)) {792 dev_err(hdev->dev, "Invalid register index in SPMU\n");793 return -EINVAL;794 }795 796 base_reg = debug_spmu_regs[params->reg_idx] - CFG_BASE;797 798 if (params->enable) {799 input = params->input;800 801 if (!input)802 return -EINVAL;803 804 if (input->event_types_num < 3) {805 dev_err(hdev->dev,806 "not enough event types values for SPMU enable\n");807 return -EINVAL;808 }809 810 if (input->event_types_num > SPMU_MAX_COUNTERS) {811 dev_err(hdev->dev,812 "too many event types values for SPMU enable\n");813 return -EINVAL;814 }815 816 WREG32(base_reg + 0xE04, 0x41013046);817 WREG32(base_reg + 0xE04, 0x41013040);818 819 for (i = 0 ; i < input->event_types_num ; i++)820 WREG32(base_reg + SPMU_EVENT_TYPES_OFFSET + i * 4,821 input->event_types[i]);822 823 WREG32(base_reg + 0xE04, 0x41013041);824 WREG32(base_reg + 0xC00, 0x8000003F);825 } else {826 output = params->output;827 output_arr_len = params->output_size / 8;828 events_num = output_arr_len - 2;829 overflow_idx = output_arr_len - 2;830 cycle_cnt_idx = output_arr_len - 1;831 832 if (!output)833 return -EINVAL;834 835 if (output_arr_len < 3) {836 dev_err(hdev->dev,837 "not enough values for SPMU disable\n");838 return -EINVAL;839 }840 841 if (events_num > SPMU_MAX_COUNTERS) {842 dev_err(hdev->dev,843 "too many events values for SPMU disable\n");844 return -EINVAL;845 }846 847 WREG32(base_reg + 0xE04, 0x41013040);848 849 for (i = 0 ; i < events_num ; i++)850 output[i] = RREG32(base_reg + i * 8);851 852 output[overflow_idx] = RREG32(base_reg + 0xCC0);853 854 output[cycle_cnt_idx] = RREG32(base_reg + 0xFC);855 output[cycle_cnt_idx] <<= 32;856 output[cycle_cnt_idx] |= RREG32(base_reg + 0xF8);857 858 WREG32(base_reg + 0xCC0, 0);859 }860 861 return 0;862}863 864int gaudi_debug_coresight(struct hl_device *hdev, struct hl_ctx *ctx, void *data)865{866 struct hl_debug_params *params = data;867 int rc = 0;868 869 switch (params->op) {870 case HL_DEBUG_OP_STM:871 rc = gaudi_config_stm(hdev, params);872 break;873 case HL_DEBUG_OP_ETF:874 rc = gaudi_config_etf(hdev, params);875 break;876 case HL_DEBUG_OP_ETR:877 rc = gaudi_config_etr(hdev, params);878 break;879 case HL_DEBUG_OP_FUNNEL:880 rc = gaudi_config_funnel(hdev, params);881 break;882 case HL_DEBUG_OP_BMON:883 rc = gaudi_config_bmon(hdev, params);884 break;885 case HL_DEBUG_OP_SPMU:886 rc = gaudi_config_spmu(hdev, params);887 break;888 case HL_DEBUG_OP_TIMESTAMP:889 /* Do nothing as this opcode is deprecated */890 break;891 892 default:893 dev_err(hdev->dev, "Unknown coresight id %d\n", params->op);894 return -EINVAL;895 }896 897 /* Perform read from the device to flush all configuration */898 RREG32(mmHW_STATE);899 900 return rc;901}902 903void gaudi_halt_coresight(struct hl_device *hdev, struct hl_ctx *ctx)904{905 struct hl_debug_params params = {};906 int i, rc;907 908 for (i = GAUDI_ETF_FIRST ; i <= GAUDI_ETF_LAST ; i++) {909 params.reg_idx = i;910 rc = gaudi_config_etf(hdev, ¶ms);911 if (rc)912 dev_err(hdev->dev, "halt ETF failed, %d/%d\n", rc, i);913 }914 915 rc = gaudi_config_etr(hdev, ¶ms);916 if (rc)917 dev_err(hdev->dev, "halt ETR failed, %d\n", rc);918}919