1064 lines · c
1/* SPDX-License-Identifier: GPL-2.02 *3 * Copyright 2020 HabanaLabs, Ltd.4 * All Rights Reserved.5 *6 */7#ifndef GAUDI2_CORESIGHT_REGS_DRV_H_8#define GAUDI2_CORESIGHT_REGS_DRV_H_9 10#include "gaudi2_masks.h"11#include "../include/gaudi2/gaudi2_coresight.h"12#include "gaudi2P.h"13 14/* FUNNEL Offsets - same offsets for all funnels*/15#define mmFUNNEL_CTRL_REG_OFFSET \16 (mmDCORE0_TPC0_EML_FUNNEL_CTRL_REG - \17 mmDCORE0_TPC0_EML_FUNNEL_BASE)18 19#define mmFUNNEL_PRIORITY_CTRL_REG_OFFSET \20 (mmDCORE0_TPC0_EML_FUNNEL_PRIORITY_CTRL_REG - \21 mmDCORE0_TPC0_EML_FUNNEL_BASE)22 23#define mmFUNNEL_ITATBDATA0_OFFSET \24 (mmDCORE0_TPC0_EML_FUNNEL_ITATBDATA0 - \25 mmDCORE0_TPC0_EML_FUNNEL_BASE)26 27#define mmFUNNEL_ITATBCTR2_OFFSET \28 (mmDCORE0_TPC0_EML_FUNNEL_ITATBCTR2 - \29 mmDCORE0_TPC0_EML_FUNNEL_BASE)30 31#define mmFUNNEL_ITATBCTR1_OFFSET \32 (mmDCORE0_TPC0_EML_FUNNEL_ITATBCTR1 - \33 mmDCORE0_TPC0_EML_FUNNEL_BASE)34 35#define mmFUNNEL_ITATBCTR0_OFFSET \36 (mmDCORE0_TPC0_EML_FUNNEL_ITATBCTR0 - \37 mmDCORE0_TPC0_EML_FUNNEL_BASE)38 39#define mmFUNNEL_ITCTRL_OFFSET \40 (mmDCORE0_TPC0_EML_FUNNEL_ITCTRL - \41 mmDCORE0_TPC0_EML_FUNNEL_BASE)42 43#define mmFUNNEL_CLAIMSET_OFFSET \44 (mmDCORE0_TPC0_EML_FUNNEL_CLAIMSET - \45 mmDCORE0_TPC0_EML_FUNNEL_BASE)46 47#define mmFUNNEL_CLAIMCLR_OFFSET \48 (mmDCORE0_TPC0_EML_FUNNEL_CLAIMCLR - \49 mmDCORE0_TPC0_EML_FUNNEL_BASE)50 51#define mmFUNNEL_LOCKACCESS_OFFSET \52 (mmDCORE0_TPC0_EML_FUNNEL_LOCKACCESS - \53 mmDCORE0_TPC0_EML_FUNNEL_BASE)54 55#define mmFUNNEL_LOCKSTATUS_OFFSET \56 (mmDCORE0_TPC0_EML_FUNNEL_LOCKSTATUS - \57 mmDCORE0_TPC0_EML_FUNNEL_BASE)58 59#define mmFUNNEL_AUTHSTATUS_OFFSET \60 (mmDCORE0_TPC0_EML_FUNNEL_AUTHSTATUS - \61 mmDCORE0_TPC0_EML_FUNNEL_BASE)62 63#define mmFUNNEL_DEVID_OFFSET \64 (mmDCORE0_TPC0_EML_FUNNEL_DEVID - \65 mmDCORE0_TPC0_EML_FUNNEL_BASE)66 67#define mmFUNNEL_DEVTYPE_OFFSET \68 (mmDCORE0_TPC0_EML_FUNNEL_DEVTYPE - \69 mmDCORE0_TPC0_EML_FUNNEL_BASE)70 71#define mmFUNNEL_PIDR4_OFFSET \72 (mmDCORE0_TPC0_EML_FUNNEL_PIDR4 - \73 mmDCORE0_TPC0_EML_FUNNEL_BASE)74 75#define mmFUNNEL_PERIPHID5_OFFSET \76 (mmDCORE0_TPC0_EML_FUNNEL_PERIPHID5 - \77 mmDCORE0_TPC0_EML_FUNNEL_BASE)78 79#define mmFUNNEL_PERIPHID6_OFFSET \80 (mmDCORE0_TPC0_EML_FUNNEL_PERIPHID6 - \81 mmDCORE0_TPC0_EML_FUNNEL_BASE)82 83#define mmFUNNEL_PERIPHID7_OFFSET \84 (mmDCORE0_TPC0_EML_FUNNEL_PERIPHID7 - \85 mmDCORE0_TPC0_EML_FUNNEL_BASE)86 87#define mmFUNNEL_PIDR0_OFFSET \88 (mmDCORE0_TPC0_EML_FUNNEL_PIDR0 - \89 mmDCORE0_TPC0_EML_FUNNEL_BASE)90 91#define mmFUNNEL_PIDR1_OFFSET \92 (mmDCORE0_TPC0_EML_FUNNEL_PIDR1 - \93 mmDCORE0_TPC0_EML_FUNNEL_BASE)94 95#define mmFUNNEL_PIDR2_OFFSET \96 (mmDCORE0_TPC0_EML_FUNNEL_PIDR2 - \97 mmDCORE0_TPC0_EML_FUNNEL_BASE)98 99#define mmFUNNEL_PIDR3_OFFSET \100 (mmDCORE0_TPC0_EML_FUNNEL_PIDR3 - \101 mmDCORE0_TPC0_EML_FUNNEL_BASE)102 103#define mmFUNNEL_CID0_OFFSET \104 (mmDCORE0_TPC0_EML_FUNNEL_CID0 - \105 mmDCORE0_TPC0_EML_FUNNEL_BASE)106 107#define mmFUNNEL_CID1_OFFSET \108 (mmDCORE0_TPC0_EML_FUNNEL_CID1 - \109 mmDCORE0_TPC0_EML_FUNNEL_BASE)110 111#define mmFUNNEL_CID2_OFFSET \112 (mmDCORE0_TPC0_EML_FUNNEL_CID2 - \113 mmDCORE0_TPC0_EML_FUNNEL_BASE)114 115#define mmFUNNEL_CID3_OFFSET \116 (mmDCORE0_TPC0_EML_FUNNEL_CID3 - \117 mmDCORE0_TPC0_EML_FUNNEL_BASE)118 119/* ETF Offsets - same offsets for all etfs */120#define mmETF_RSZ_OFFSET \121 (mmDCORE0_TPC0_EML_ETF_RSZ - \122 mmDCORE0_TPC0_EML_ETF_BASE)123 124#define mmETF_STS_OFFSET \125 (mmDCORE0_TPC0_EML_ETF_STS - \126 mmDCORE0_TPC0_EML_ETF_BASE)127 128#define mmETF_RRD_OFFSET \129 (mmDCORE0_TPC0_EML_ETF_RRD - \130 mmDCORE0_TPC0_EML_ETF_BASE)131 132#define mmETF_RRP_OFFSET \133 (mmDCORE0_TPC0_EML_ETF_RRP - \134 mmDCORE0_TPC0_EML_ETF_BASE)135 136#define mmETF_RWP_OFFSET \137 (mmDCORE0_TPC0_EML_ETF_RWP - \138 mmDCORE0_TPC0_EML_ETF_BASE)139 140#define mmETF_TRG_OFFSET \141 (mmDCORE0_TPC0_EML_ETF_TRG - \142 mmDCORE0_TPC0_EML_ETF_BASE)143 144#define mmETF_CTL_OFFSET \145 (mmDCORE0_TPC0_EML_ETF_CTL - \146 mmDCORE0_TPC0_EML_ETF_BASE)147 148#define mmETF_RWD_OFFSET \149 (mmDCORE0_TPC0_EML_ETF_RWD - \150 mmDCORE0_TPC0_EML_ETF_BASE)151 152#define mmETF_MODE_OFFSET \153 (mmDCORE0_TPC0_EML_ETF_MODE - \154 mmDCORE0_TPC0_EML_ETF_BASE)155 156#define mmETF_LBUFLEVEL_OFFSET \157 (mmDCORE0_TPC0_EML_ETF_LBUFLEVEL - \158 mmDCORE0_TPC0_EML_ETF_BASE)159 160#define mmETF_CBUFLEVEL_OFFSET \161 (mmDCORE0_TPC0_EML_ETF_CBUFLEVEL - \162 mmDCORE0_TPC0_EML_ETF_BASE)163 164#define mmETF_BUFWM_OFFSET \165 (mmDCORE0_TPC0_EML_ETF_BUFWM - \166 mmDCORE0_TPC0_EML_ETF_BASE)167 168#define mmETF_FFSR_OFFSET \169 (mmDCORE0_TPC0_EML_ETF_FFSR - \170 mmDCORE0_TPC0_EML_ETF_BASE)171 172#define mmETF_FFCR_OFFSET \173 (mmDCORE0_TPC0_EML_ETF_FFCR - \174 mmDCORE0_TPC0_EML_ETF_BASE)175 176#define mmETF_PSCR_OFFSET \177 (mmDCORE0_TPC0_EML_ETF_PSCR - \178 mmDCORE0_TPC0_EML_ETF_BASE)179 180#define mmETF_ITATBMDATA0_OFFSET \181 (mmDCORE0_TPC0_EML_ETF_ITATBMDATA0 - \182 mmDCORE0_TPC0_EML_ETF_BASE)183 184#define mmETF_ITATBMCTR2_OFFSET \185 (mmDCORE0_TPC0_EML_ETF_ITATBMCTR2 - \186 mmDCORE0_TPC0_EML_ETF_BASE)187 188#define mmETF_ITATBMCTR1_OFFSET \189 (mmDCORE0_TPC0_EML_ETF_ITATBMCTR1 - \190 mmDCORE0_TPC0_EML_ETF_BASE)191 192#define mmETF_ITATBMCTR0_OFFSET \193 (mmDCORE0_TPC0_EML_ETF_ITATBMCTR0 - \194 mmDCORE0_TPC0_EML_ETF_BASE)195 196#define mmETF_ITMISCOP0_OFFSET \197 (mmDCORE0_TPC0_EML_ETF_ITMISCOP0 - \198 mmDCORE0_TPC0_EML_ETF_BASE)199 200#define mmETF_ITTRFLIN_OFFSET \201 (mmDCORE0_TPC0_EML_ETF_ITTRFLIN - \202 mmDCORE0_TPC0_EML_ETF_BASE)203 204#define mmETF_ITATBDATA0_OFFSET \205 (mmDCORE0_TPC0_EML_ETF_ITATBDATA0 - \206 mmDCORE0_TPC0_EML_ETF_BASE)207 208#define mmETF_ITATBCTR2_OFFSET \209 (mmDCORE0_TPC0_EML_ETF_ITATBCTR2 - \210 mmDCORE0_TPC0_EML_ETF_BASE)211 212#define mmETF_ITATBCTR1_OFFSET \213 (mmDCORE0_TPC0_EML_ETF_ITATBCTR1 - \214 mmDCORE0_TPC0_EML_ETF_BASE)215 216#define mmETF_ITATBCTR0_OFFSET \217 (mmDCORE0_TPC0_EML_ETF_ITATBCTR0 - \218 mmDCORE0_TPC0_EML_ETF_BASE)219 220#define mmETF_ITCTRL_OFFSET \221 (mmDCORE0_TPC0_EML_ETF_ITCTRL - \222 mmDCORE0_TPC0_EML_ETF_BASE)223 224#define mmETF_CLAIMSET_OFFSET \225 (mmDCORE0_TPC0_EML_ETF_CLAIMSET - \226 mmDCORE0_TPC0_EML_ETF_BASE)227 228#define mmETF_CLAIMCLR_OFFSET \229 (mmDCORE0_TPC0_EML_ETF_CLAIMCLR - \230 mmDCORE0_TPC0_EML_ETF_BASE)231 232#define mmETF_LAR_OFFSET \233 (mmDCORE0_TPC0_EML_ETF_LAR - \234 mmDCORE0_TPC0_EML_ETF_BASE)235 236#define mmETF_LSR_OFFSET \237 (mmDCORE0_TPC0_EML_ETF_LSR - \238 mmDCORE0_TPC0_EML_ETF_BASE)239 240#define mmETF_AUTHSTATUS_OFFSET \241 (mmDCORE0_TPC0_EML_ETF_AUTHSTATUS - \242 mmDCORE0_TPC0_EML_ETF_BASE)243 244#define mmETF_DEVID_OFFSET \245 (mmDCORE0_TPC0_EML_ETF_DEVID - \246 mmDCORE0_TPC0_EML_ETF_BASE)247 248#define mmETF_DEVTYPE_OFFSET \249 (mmDCORE0_TPC0_EML_ETF_DEVTYPE - \250 mmDCORE0_TPC0_EML_ETF_BASE)251 252#define mmETF_PERIPHID4_OFFSET \253 (mmDCORE0_TPC0_EML_ETF_PERIPHID4 - \254 mmDCORE0_TPC0_EML_ETF_BASE)255 256#define mmETF_PERIPHID5_OFFSET \257 (mmDCORE0_TPC0_EML_ETF_PERIPHID5 - \258 mmDCORE0_TPC0_EML_ETF_BASE)259 260#define mmETF_PERIPHID6_OFFSET \261 (mmDCORE0_TPC0_EML_ETF_PERIPHID6 - \262 mmDCORE0_TPC0_EML_ETF_BASE)263 264#define mmETF_PERIPHID7_OFFSET \265 (mmDCORE0_TPC0_EML_ETF_PERIPHID7 - \266 mmDCORE0_TPC0_EML_ETF_BASE)267 268#define mmETF_PERIPHID0_OFFSET \269 (mmDCORE0_TPC0_EML_ETF_PERIPHID0 - \270 mmDCORE0_TPC0_EML_ETF_BASE)271 272#define mmETF_PERIPHID1_OFFSET \273 (mmDCORE0_TPC0_EML_ETF_PERIPHID1 - \274 mmDCORE0_TPC0_EML_ETF_BASE)275 276#define mmETF_PERIPHID2_OFFSET \277 (mmDCORE0_TPC0_EML_ETF_PERIPHID2 - \278 mmDCORE0_TPC0_EML_ETF_BASE)279 280#define mmETF_PERIPHID3_OFFSET \281 (mmDCORE0_TPC0_EML_ETF_PERIPHID3 - \282 mmDCORE0_TPC0_EML_ETF_BASE)283 284#define mmETF_COMPID0_OFFSET \285 (mmDCORE0_TPC0_EML_ETF_COMPID0 - \286 mmDCORE0_TPC0_EML_ETF_BASE)287 288#define mmETF_COMPID1_OFFSET \289 (mmDCORE0_TPC0_EML_ETF_COMPID1 - \290 mmDCORE0_TPC0_EML_ETF_BASE)291 292#define mmETF_COMPID2_OFFSET \293 (mmDCORE0_TPC0_EML_ETF_COMPID2 - \294 mmDCORE0_TPC0_EML_ETF_BASE)295 296#define mmETF_COMPID3_OFFSET \297 (mmDCORE0_TPC0_EML_ETF_COMPID3 - \298 mmDCORE0_TPC0_EML_ETF_BASE)299 300 301/* STM OFFSETS - same offsets for all stms */302#define mmSTM_STMDMASTARTR_OFFSET \303 (mmDCORE0_TPC0_EML_STM_STMDMASTARTR - \304 mmDCORE0_TPC0_EML_STM_BASE)305 306#define mmSTM_STMDMASTOPR_OFFSET \307 (mmDCORE0_TPC0_EML_STM_STMDMASTOPR - \308 mmDCORE0_TPC0_EML_STM_BASE)309 310#define mmSTM_STMDMASTATR_OFFSET \311 (mmDCORE0_TPC0_EML_STM_STMDMASTATR - \312 mmDCORE0_TPC0_EML_STM_BASE)313 314#define mmSTM_STMDMACTLR_OFFSET \315 (mmDCORE0_TPC0_EML_STM_STMDMACTLR - \316 mmDCORE0_TPC0_EML_STM_BASE)317 318#define mmSTM_STMDMAIDR_OFFSET \319 (mmDCORE0_TPC0_EML_STM_STMDMAIDR - \320 mmDCORE0_TPC0_EML_STM_BASE)321 322#define mmSTM_STMHEER_OFFSET \323 (mmDCORE0_TPC0_EML_STM_STMHEER - \324 mmDCORE0_TPC0_EML_STM_BASE)325 326#define mmSTM_STMHETER_OFFSET \327 (mmDCORE0_TPC0_EML_STM_STMHETER - \328 mmDCORE0_TPC0_EML_STM_BASE)329 330#define mmSTM_STMHEBSR_OFFSET \331 (mmDCORE0_TPC0_EML_STM_STMHEBSR - \332 mmDCORE0_TPC0_EML_STM_BASE)333 334#define mmSTM_STMHEMCR_OFFSET \335 (mmDCORE0_TPC0_EML_STM_STMHEMCR - \336 mmDCORE0_TPC0_EML_STM_BASE)337 338#define mmSTM_STMHEEXTMUXR_OFFSET \339 (mmDCORE0_TPC0_EML_STM_STMHEEXTMUXR - \340 mmDCORE0_TPC0_EML_STM_BASE)341 342#define mmSTM_STMHEMASTR_OFFSET \343 (mmDCORE0_TPC0_EML_STM_STMHEMASTR - \344 mmDCORE0_TPC0_EML_STM_BASE)345 346#define mmSTM_STMHEFEAT1R_OFFSET \347 (mmDCORE0_TPC0_EML_STM_STMHEFEAT1R - \348 mmDCORE0_TPC0_EML_STM_BASE)349 350#define mmSTM_STMHEIDR_OFFSET \351 (mmDCORE0_TPC0_EML_STM_STMHEIDR - \352 mmDCORE0_TPC0_EML_STM_BASE)353 354#define mmSTM_STMSPER_OFFSET \355 (mmDCORE0_TPC0_EML_STM_STMSPER - \356 mmDCORE0_TPC0_EML_STM_BASE)357 358#define mmSTM_STMSPTER_OFFSET \359 (mmDCORE0_TPC0_EML_STM_STMSPTER - \360 mmDCORE0_TPC0_EML_STM_BASE)361 362#define mmSTM_STMSPSCR_OFFSET \363 (mmDCORE0_TPC0_EML_STM_STMSPSCR - \364 mmDCORE0_TPC0_EML_STM_BASE)365 366#define mmSTM_STMSPMSCR_OFFSET \367 (mmDCORE0_TPC0_EML_STM_STMSPMSCR - \368 mmDCORE0_TPC0_EML_STM_BASE)369 370#define mmSTM_STMSPOVERRIDER_OFFSET \371 (mmDCORE0_TPC0_EML_STM_STMSPOVERRIDER - \372 mmDCORE0_TPC0_EML_STM_BASE)373 374#define mmSTM_STMSPMOVERRIDER_OFFSET \375 (mmDCORE0_TPC0_EML_STM_STMSPMOVERRIDER - \376 mmDCORE0_TPC0_EML_STM_BASE)377 378#define mmSTM_STMSPTRIGCSR_OFFSET \379 (mmDCORE0_TPC0_EML_STM_STMSPTRIGCSR - \380 mmDCORE0_TPC0_EML_STM_BASE)381 382#define mmSTM_STMTCSR_OFFSET \383 (mmDCORE0_TPC0_EML_STM_STMTCSR - \384 mmDCORE0_TPC0_EML_STM_BASE)385 386#define mmSTM_STMTSSTIMR_OFFSET \387 (mmDCORE0_TPC0_EML_STM_STMTSSTIMR - \388 mmDCORE0_TPC0_EML_STM_BASE)389 390#define mmSTM_STMTSFREQR_OFFSET \391 (mmDCORE0_TPC0_EML_STM_STMTSFREQR - \392 mmDCORE0_TPC0_EML_STM_BASE)393 394#define mmSTM_STMSYNCR_OFFSET \395 (mmDCORE0_TPC0_EML_STM_STMSYNCR - \396 mmDCORE0_TPC0_EML_STM_BASE)397 398#define mmSTM_STMAUXCR_OFFSET \399 (mmDCORE0_TPC0_EML_STM_STMAUXCR - \400 mmDCORE0_TPC0_EML_STM_BASE)401 402#define mmSTM_STMFEAT1R_OFFSET \403 (mmDCORE0_TPC0_EML_STM_STMFEAT1R - \404 mmDCORE0_TPC0_EML_STM_BASE)405 406#define mmSTM_STMFEAT2R_OFFSET \407 (mmDCORE0_TPC0_EML_STM_STMFEAT2R - \408 mmDCORE0_TPC0_EML_STM_BASE)409 410#define mmSTM_STMFEAT3R_OFFSET \411 (mmDCORE0_TPC0_EML_STM_STMFEAT3R - \412 mmDCORE0_TPC0_EML_STM_BASE)413 414#define mmSTM_STMITTRIGGER_OFFSET \415 (mmDCORE0_TPC0_EML_STM_STMITTRIGGER - \416 mmDCORE0_TPC0_EML_STM_BASE)417 418#define mmSTM_STMITATBDATA0_OFFSET \419 (mmDCORE0_TPC0_EML_STM_STMITATBDATA0 - \420 mmDCORE0_TPC0_EML_STM_BASE)421 422#define mmSTM_STMITATBCTR2_OFFSET \423 (mmDCORE0_TPC0_EML_STM_STMITATBCTR2 - \424 mmDCORE0_TPC0_EML_STM_BASE)425 426#define mmSTM_STMITATBID_OFFSET \427 (mmDCORE0_TPC0_EML_STM_STMITATBID - \428 mmDCORE0_TPC0_EML_STM_BASE)429 430#define mmSTM_STMITATBCTR0_OFFSET \431 (mmDCORE0_TPC0_EML_STM_STMITATBCTR0 - \432 mmDCORE0_TPC0_EML_STM_BASE)433 434#define mmSTM_STMITCTRL_OFFSET \435 (mmDCORE0_TPC0_EML_STM_STMITCTRL - \436 mmDCORE0_TPC0_EML_STM_BASE)437 438#define mmSTM_STMCLAIMSET_OFFSET \439 (mmDCORE0_TPC0_EML_STM_STMCLAIMSET - \440 mmDCORE0_TPC0_EML_STM_BASE)441 442#define mmSTM_STMCLAIMCLR_OFFSET \443 (mmDCORE0_TPC0_EML_STM_STMCLAIMCLR - \444 mmDCORE0_TPC0_EML_STM_BASE)445 446#define mmSTM_STMLAR_OFFSET \447 (mmDCORE0_TPC0_EML_STM_STMLAR - \448 mmDCORE0_TPC0_EML_STM_BASE)449 450#define mmSTM_STMLSR_OFFSET \451 (mmDCORE0_TPC0_EML_STM_STMLSR - \452 mmDCORE0_TPC0_EML_STM_BASE)453 454#define mmSTM_STMAUTHSTATUS_OFFSET \455 (mmDCORE0_TPC0_EML_STM_STMAUTHSTATUS - \456 mmDCORE0_TPC0_EML_STM_BASE)457 458#define mmSTM_STMDEVARCH_OFFSET \459 (mmDCORE0_TPC0_EML_STM_STMDEVARCH - \460 mmDCORE0_TPC0_EML_STM_BASE)461 462#define mmSTM_STMDEVID_OFFSET \463 (mmDCORE0_TPC0_EML_STM_STMDEVID - \464 mmDCORE0_TPC0_EML_STM_BASE)465 466#define mmSTM_STMDEVTYPE_OFFSET \467 (mmDCORE0_TPC0_EML_STM_STMDEVTYPE - \468 mmDCORE0_TPC0_EML_STM_BASE)469 470#define mmSTM_STMPIDR4_OFFSET \471 (mmDCORE0_TPC0_EML_STM_STMPIDR4 - \472 mmDCORE0_TPC0_EML_STM_BASE)473 474#define mmSTM_STMPIDR5_OFFSET \475 (mmDCORE0_TPC0_EML_STM_STMPIDR5 - \476 mmDCORE0_TPC0_EML_STM_BASE)477 478#define mmSTM_STMPIDR6_OFFSET \479 (mmDCORE0_TPC0_EML_STM_STMPIDR6 - \480 mmDCORE0_TPC0_EML_STM_BASE)481 482#define mmSTM_STMPIDR7_OFFSET \483 (mmDCORE0_TPC0_EML_STM_STMPIDR7 - \484 mmDCORE0_TPC0_EML_STM_BASE)485 486#define mmSTM_STMPIDR0_OFFSET \487 (mmDCORE0_TPC0_EML_STM_STMPIDR0 - \488 mmDCORE0_TPC0_EML_STM_BASE)489 490#define mmSTM_STMPIDR1_OFFSET \491 (mmDCORE0_TPC0_EML_STM_STMPIDR1 - \492 mmDCORE0_TPC0_EML_STM_BASE)493 494#define mmSTM_STMPIDR2_OFFSET \495 (mmDCORE0_TPC0_EML_STM_STMPIDR2 - \496 mmDCORE0_TPC0_EML_STM_BASE)497 498#define mmSTM_STMPIDR3_OFFSET \499 (mmDCORE0_TPC0_EML_STM_STMPIDR3 - \500 mmDCORE0_TPC0_EML_STM_BASE)501 502#define mmSTM_STMCIDR0_OFFSET \503 (mmDCORE0_TPC0_EML_STM_STMCIDR0 - \504 mmDCORE0_TPC0_EML_STM_BASE)505 506#define mmSTM_STMCIDR1_OFFSET \507 (mmDCORE0_TPC0_EML_STM_STMCIDR1 - \508 mmDCORE0_TPC0_EML_STM_BASE)509 510#define mmSTM_STMCIDR2_OFFSET \511 (mmDCORE0_TPC0_EML_STM_STMCIDR2 - \512 mmDCORE0_TPC0_EML_STM_BASE)513 514#define mmSTM_STMCIDR3_OFFSET \515 (mmDCORE0_TPC0_EML_STM_STMCIDR3 - \516 mmDCORE0_TPC0_EML_STM_BASE)517 518 519/* SPMU OFFSETS - same offsets for all SPMUs */520#define mmSPMU_PMEVCNTR0_EL0_OFFSET \521 (mmDCORE0_TPC0_EML_SPMU_PMEVCNTR0_EL0 - \522 mmDCORE0_TPC0_EML_SPMU_BASE)523 524#define mmSPMU_PMEVCNTR1_EL0_OFFSET \525 (mmDCORE0_TPC0_EML_SPMU_PMEVCNTR1_EL0 - \526 mmDCORE0_TPC0_EML_SPMU_BASE)527 528#define mmSPMU_PMEVCNTR2_EL0_OFFSET \529 (mmDCORE0_TPC0_EML_SPMU_PMEVCNTR2_EL0 - \530 mmDCORE0_TPC0_EML_SPMU_BASE)531 532#define mmSPMU_PMEVCNTR3_EL0_OFFSET \533 (mmDCORE0_TPC0_EML_SPMU_PMEVCNTR3_EL0 - \534 mmDCORE0_TPC0_EML_SPMU_BASE)535 536#define mmSPMU_PMEVCNTR4_EL0_OFFSET \537 (mmDCORE0_TPC0_EML_SPMU_PMEVCNTR4_EL0 - \538 mmDCORE0_TPC0_EML_SPMU_BASE)539 540#define mmSPMU_PMEVCNTR5_EL0_OFFSET \541 (mmDCORE0_TPC0_EML_SPMU_PMEVCNTR5_EL0 - \542 mmDCORE0_TPC0_EML_SPMU_BASE)543 544#define mmSPMU_PMCCNTR_L_EL0_OFFSET \545 (mmDCORE0_TPC0_EML_SPMU_PMCCNTR_L_EL0 - \546 mmDCORE0_TPC0_EML_SPMU_BASE)547 548#define mmSPMU_PMCCNTR_H_EL0_OFFSET \549 (mmDCORE0_TPC0_EML_SPMU_PMCCNTR_H_EL0 - \550 mmDCORE0_TPC0_EML_SPMU_BASE)551 552#define mmSPMU_PMTRC_OFFSET \553 (mmDCORE0_TPC0_EML_SPMU_PMTRC - \554 mmDCORE0_TPC0_EML_SPMU_BASE)555 556#define mmSPMU_TRC_CTRL_HOST_OFFSET \557 (mmDCORE0_TPC0_EML_SPMU_TRC_CTRL_HOST - \558 mmDCORE0_TPC0_EML_SPMU_BASE)559 560#define mmSPMU_TRC_STAT_HOST_OFFSET \561 (mmDCORE0_TPC0_EML_SPMU_TRC_STAT_HOST - \562 mmDCORE0_TPC0_EML_SPMU_BASE)563 564#define mmSPMU_TRC_EN_HOST_OFFSET \565 (mmDCORE0_TPC0_EML_SPMU_TRC_EN_HOST - \566 mmDCORE0_TPC0_EML_SPMU_BASE)567 568#define mmSPMU_PMEVTYPER0_EL0_OFFSET \569 (mmDCORE0_TPC0_EML_SPMU_PMEVTYPER0_EL0 - \570 mmDCORE0_TPC0_EML_SPMU_BASE)571 572#define mmSPMU_PMEVTYPER1_EL0_OFFSET \573 (mmDCORE0_TPC0_EML_SPMU_PMEVTYPER1_EL0 - \574 mmDCORE0_TPC0_EML_SPMU_BASE)575 576#define mmSPMU_PMEVTYPER2_EL0_OFFSET \577 (mmDCORE0_TPC0_EML_SPMU_PMEVTYPER2_EL0 - \578 mmDCORE0_TPC0_EML_SPMU_BASE)579 580#define mmSPMU_PMEVTYPER3_EL0_OFFSET \581 (mmDCORE0_TPC0_EML_SPMU_PMEVTYPER3_EL0 - \582 mmDCORE0_TPC0_EML_SPMU_BASE)583 584#define mmSPMU_PMEVTYPER4_EL0_OFFSET \585 (mmDCORE0_TPC0_EML_SPMU_PMEVTYPER4_EL0 - \586 mmDCORE0_TPC0_EML_SPMU_BASE)587 588#define mmSPMU_PMEVTYPER5_EL0_OFFSET \589 (mmDCORE0_TPC0_EML_SPMU_PMEVTYPER5_EL0 - \590 mmDCORE0_TPC0_EML_SPMU_BASE)591 592#define mmSPMU_PMSSR_OFFSET \593 (mmDCORE0_TPC0_EML_SPMU_PMSSR - \594 mmDCORE0_TPC0_EML_SPMU_BASE)595 596#define mmSPMU_PMOVSSR_OFFSET \597 (mmDCORE0_TPC0_EML_SPMU_PMOVSSR - \598 mmDCORE0_TPC0_EML_SPMU_BASE)599 600#define mmSPMU_PMCCNTSR_L_OFFSET \601 (mmDCORE0_TPC0_EML_SPMU_PMCCNTSR_L - \602 mmDCORE0_TPC0_EML_SPMU_BASE)603 604#define mmSPMU_PMCCNTSR_H_OFFSET \605 (mmDCORE0_TPC0_EML_SPMU_PMCCNTSR_H - \606 mmDCORE0_TPC0_EML_SPMU_BASE)607 608#define mmSPMU_PMEVCNTSR0_OFFSET \609 (mmDCORE0_TPC0_EML_SPMU_PMEVCNTSR0 - \610 mmDCORE0_TPC0_EML_SPMU_BASE)611 612#define mmSPMU_PMEVCNTSR1_OFFSET \613 (mmDCORE0_TPC0_EML_SPMU_PMEVCNTSR1 - \614 mmDCORE0_TPC0_EML_SPMU_BASE)615 616#define mmSPMU_PMEVCNTSR2_OFFSET \617 (mmDCORE0_TPC0_EML_SPMU_PMEVCNTSR2 - \618 mmDCORE0_TPC0_EML_SPMU_BASE)619 620#define mmSPMU_PMEVCNTSR3_OFFSET \621 (mmDCORE0_TPC0_EML_SPMU_PMEVCNTSR3 - \622 mmDCORE0_TPC0_EML_SPMU_BASE)623 624#define mmSPMU_PMEVCNTSR4_OFFSET \625 (mmDCORE0_TPC0_EML_SPMU_PMEVCNTSR4 - \626 mmDCORE0_TPC0_EML_SPMU_BASE)627 628#define mmSPMU_PMEVCNTSR5_OFFSET \629 (mmDCORE0_TPC0_EML_SPMU_PMEVCNTSR5 - \630 mmDCORE0_TPC0_EML_SPMU_BASE)631 632#define mmSPMU_PMSCR_OFFSET \633 (mmDCORE0_TPC0_EML_SPMU_PMSCR - \634 mmDCORE0_TPC0_EML_SPMU_BASE)635 636#define mmSPMU_PMSRR_OFFSET \637 (mmDCORE0_TPC0_EML_SPMU_PMSRR - \638 mmDCORE0_TPC0_EML_SPMU_BASE)639 640#define mmSPMU_PMCNTENSET_EL0_OFFSET \641 (mmDCORE0_TPC0_EML_SPMU_PMCNTENSET_EL0 - \642 mmDCORE0_TPC0_EML_SPMU_BASE)643 644#define mmSPMU_PMCNTENCLR_EL0_OFFSET \645 (mmDCORE0_TPC0_EML_SPMU_PMCNTENCLR_EL0 - \646 mmDCORE0_TPC0_EML_SPMU_BASE)647 648#define mmSPMU_PMINTENSET_EL1_OFFSET \649 (mmDCORE0_TPC0_EML_SPMU_PMINTENSET_EL1 - \650 mmDCORE0_TPC0_EML_SPMU_BASE)651 652#define mmSPMU_PMINTENCLR_EL1_OFFSET \653 (mmDCORE0_TPC0_EML_SPMU_PMINTENCLR_EL1 - \654 mmDCORE0_TPC0_EML_SPMU_BASE)655 656#define mmSPMU_PMOVSCLR_EL0_OFFSET \657 (mmDCORE0_TPC0_EML_SPMU_PMOVSCLR_EL0 - \658 mmDCORE0_TPC0_EML_SPMU_BASE)659 660#define mmSPMU_PMSWINC_EL0_OFFSET \661 (mmDCORE0_TPC0_EML_SPMU_PMSWINC_EL0 - \662 mmDCORE0_TPC0_EML_SPMU_BASE)663 664#define mmSPMU_PMOVSSET_EL0_OFFSET \665 (mmDCORE0_TPC0_EML_SPMU_PMOVSSET_EL0 - \666 mmDCORE0_TPC0_EML_SPMU_BASE)667 668#define mmSPMU_PMCFGR_OFFSET \669 (mmDCORE0_TPC0_EML_SPMU_PMCFGR - \670 mmDCORE0_TPC0_EML_SPMU_BASE)671 672#define mmSPMU_PMCR_EL0_OFFSET \673 (mmDCORE0_TPC0_EML_SPMU_PMCR_EL0 - \674 mmDCORE0_TPC0_EML_SPMU_BASE)675 676#define mmSPMU_PMITCTRL_OFFSET \677 (mmDCORE0_TPC0_EML_SPMU_PMITCTRL - \678 mmDCORE0_TPC0_EML_SPMU_BASE)679 680#define mmSPMU_PMCLAIMSET_OFFSET \681 (mmDCORE0_TPC0_EML_SPMU_PMCLAIMSET - \682 mmDCORE0_TPC0_EML_SPMU_BASE)683 684#define mmSPMU_PMCLAIMCLR_OFFSET \685 (mmDCORE0_TPC0_EML_SPMU_PMCLAIMCLR - \686 mmDCORE0_TPC0_EML_SPMU_BASE)687 688#define mmSPMU_PMDEVAFF0_OFFSET \689 (mmDCORE0_TPC0_EML_SPMU_PMDEVAFF0 - \690 mmDCORE0_TPC0_EML_SPMU_BASE)691 692#define mmSPMU_PMDEVAFF1_OFFSET \693 (mmDCORE0_TPC0_EML_SPMU_PMDEVAFF1 - \694 mmDCORE0_TPC0_EML_SPMU_BASE)695 696#define mmSPMU_PMLAR_OFFSET \697 (mmDCORE0_TPC0_EML_SPMU_PMLAR - \698 mmDCORE0_TPC0_EML_SPMU_BASE)699 700#define mmSPMU_PMLSR_OFFSET \701 (mmDCORE0_TPC0_EML_SPMU_PMLSR - \702 mmDCORE0_TPC0_EML_SPMU_BASE)703 704#define mmSPMU_PMAUTHSTATUS_OFFSET \705 (mmDCORE0_TPC0_EML_SPMU_PMAUTHSTATUS - \706 mmDCORE0_TPC0_EML_SPMU_BASE)707 708#define mmSPMU_PMDEVARCH_OFFSET \709 (mmDCORE0_TPC0_EML_SPMU_PMDEVARCH - \710 mmDCORE0_TPC0_EML_SPMU_BASE)711 712#define mmSPMU_PMDEVID2_OFFSET \713 (mmDCORE0_TPC0_EML_SPMU_PMDEVID2 - \714 mmDCORE0_TPC0_EML_SPMU_BASE)715 716#define mmSPMU_PMDEVID1_OFFSET \717 (mmDCORE0_TPC0_EML_SPMU_PMDEVID1 - \718 mmDCORE0_TPC0_EML_SPMU_BASE)719 720#define mmSPMU_PMDEVID_OFFSET \721 (mmDCORE0_TPC0_EML_SPMU_PMDEVID - \722 mmDCORE0_TPC0_EML_SPMU_BASE)723 724#define mmSPMU_PMDEVTYPE_OFFSET \725 (mmDCORE0_TPC0_EML_SPMU_PMDEVTYPE - \726 mmDCORE0_TPC0_EML_SPMU_BASE)727 728#define mmSPMU_PMPIDR4_OFFSET \729 (mmDCORE0_TPC0_EML_SPMU_PMPIDR4 - \730 mmDCORE0_TPC0_EML_SPMU_BASE)731 732#define mmSPMU_PMPIDR5_OFFSET \733 (mmDCORE0_TPC0_EML_SPMU_PMPIDR5 - \734 mmDCORE0_TPC0_EML_SPMU_BASE)735 736#define mmSPMU_PMPIDR6_OFFSET \737 (mmDCORE0_TPC0_EML_SPMU_PMPIDR6 - \738 mmDCORE0_TPC0_EML_SPMU_BASE)739 740#define mmSPMU_PMPIDR7_OFFSET \741 (mmDCORE0_TPC0_EML_SPMU_PMPIDR7 - \742 mmDCORE0_TPC0_EML_SPMU_BASE)743 744#define mmSPMU_PMPIDR0_OFFSET \745 (mmDCORE0_TPC0_EML_SPMU_PMPIDR0 - \746 mmDCORE0_TPC0_EML_SPMU_BASE)747 748#define mmSPMU_PMPIDR1_OFFSET \749 (mmDCORE0_TPC0_EML_SPMU_PMPIDR1 - \750 mmDCORE0_TPC0_EML_SPMU_BASE)751 752#define mmSPMU_PMPIDR2_OFFSET \753 (mmDCORE0_TPC0_EML_SPMU_PMPIDR2 - \754 mmDCORE0_TPC0_EML_SPMU_BASE)755 756#define mmSPMU_PMPIDR3_OFFSET \757 (mmDCORE0_TPC0_EML_SPMU_PMPIDR3 - \758 mmDCORE0_TPC0_EML_SPMU_BASE)759 760#define mmSPMU_PMCIDR0_OFFSET \761 (mmDCORE0_TPC0_EML_SPMU_PMCIDR0 - \762 mmDCORE0_TPC0_EML_SPMU_BASE)763 764#define mmSPMU_PMCIDR1_OFFSET \765 (mmDCORE0_TPC0_EML_SPMU_PMCIDR1 - \766 mmDCORE0_TPC0_EML_SPMU_BASE)767 768#define mmSPMU_PMCIDR2_OFFSET \769 (mmDCORE0_TPC0_EML_SPMU_PMCIDR2 - \770 mmDCORE0_TPC0_EML_SPMU_BASE)771 772#define mmSPMU_PMCIDR3_OFFSET \773 (mmDCORE0_TPC0_EML_SPMU_PMCIDR3 - \774 mmDCORE0_TPC0_EML_SPMU_BASE)775 776 777/* BMON OFFSETS - same offsets for all BMONs*/778#define mmBMON_CR_OFFSET \779 (mmDCORE0_TPC0_EML_BUSMON_0_CR - \780 mmDCORE0_TPC0_EML_BUSMON_0_BASE)781 782#define mmBMON_RESET_OFFSET \783 (mmDCORE0_TPC0_EML_BUSMON_0_REG_RESET - \784 mmDCORE0_TPC0_EML_BUSMON_0_BASE)785 786#define mmBMON_INT_CLR_OFFSET \787 (mmDCORE0_TPC0_EML_BUSMON_0_INT_CLR - \788 mmDCORE0_TPC0_EML_BUSMON_0_BASE)789 790#define mmBMON_TRIG_TH_OFFSET \791 (mmDCORE0_TPC0_EML_BUSMON_0_TRIG_TH - \792 mmDCORE0_TPC0_EML_BUSMON_0_BASE)793 794#define mmBMON_ADDRL_S0_OFFSET \795 (mmDCORE0_TPC0_EML_BUSMON_0_ADDRL_S0 - \796 mmDCORE0_TPC0_EML_BUSMON_0_BASE)797 798#define mmBMON_ADDRH_S0_OFFSET \799 (mmDCORE0_TPC0_EML_BUSMON_0_ADDRH_S0 - \800 mmDCORE0_TPC0_EML_BUSMON_0_BASE)801 802#define mmBMON_ADDRL_E0_OFFSET \803 (mmDCORE0_TPC0_EML_BUSMON_0_ADDRL_E0 - \804 mmDCORE0_TPC0_EML_BUSMON_0_BASE)805 806#define mmBMON_ADDRH_E0_OFFSET \807 (mmDCORE0_TPC0_EML_BUSMON_0_ADDRH_E0 - \808 mmDCORE0_TPC0_EML_BUSMON_0_BASE)809 810#define mmBMON_ADDRL_S1_OFFSET \811 (mmDCORE0_TPC0_EML_BUSMON_0_ADDRL_S1 - \812 mmDCORE0_TPC0_EML_BUSMON_0_BASE)813 814#define mmBMON_ADDRH_S1_OFFSET \815 (mmDCORE0_TPC0_EML_BUSMON_0_ADDRH_S1 - \816 mmDCORE0_TPC0_EML_BUSMON_0_BASE)817 818#define mmBMON_ADDRL_E1_OFFSET \819 (mmDCORE0_TPC0_EML_BUSMON_0_ADDRL_E1 - \820 mmDCORE0_TPC0_EML_BUSMON_0_BASE)821 822#define mmBMON_ADDRH_E1_OFFSET \823 (mmDCORE0_TPC0_EML_BUSMON_0_ADDRH_E1 - \824 mmDCORE0_TPC0_EML_BUSMON_0_BASE)825 826#define mmBMON_ADDRL_S2_OFFSET \827 (mmDCORE0_TPC0_EML_BUSMON_0_ADDRL_S2 - \828 mmDCORE0_TPC0_EML_BUSMON_0_BASE)829 830#define mmBMON_ADDRH_S2_OFFSET \831 (mmDCORE0_TPC0_EML_BUSMON_0_ADDRH_S2 - \832 mmDCORE0_TPC0_EML_BUSMON_0_BASE)833 834#define mmBMON_ADDRL_E2_OFFSET \835 (mmDCORE0_TPC0_EML_BUSMON_0_ADDRL_E2 - \836 mmDCORE0_TPC0_EML_BUSMON_0_BASE)837 838#define mmBMON_ADDRH_E2_OFFSET \839 (mmDCORE0_TPC0_EML_BUSMON_0_ADDRH_E2 - \840 mmDCORE0_TPC0_EML_BUSMON_0_BASE)841 842#define mmBMON_ADDRL_S3_OFFSET \843 (mmDCORE0_TPC0_EML_BUSMON_0_ADDRL_S3 - \844 mmDCORE0_TPC0_EML_BUSMON_0_BASE)845 846#define mmBMON_ADDRH_S3_OFFSET \847 (mmDCORE0_TPC0_EML_BUSMON_0_ADDRH_S3 - \848 mmDCORE0_TPC0_EML_BUSMON_0_BASE)849 850#define mmBMON_ADDRL_E3_OFFSET \851 (mmDCORE0_TPC0_EML_BUSMON_0_ADDRL_E3 - \852 mmDCORE0_TPC0_EML_BUSMON_0_BASE)853 854#define mmBMON_ADDRH_E3_OFFSET \855 (mmDCORE0_TPC0_EML_BUSMON_0_ADDRH_E3 - \856 mmDCORE0_TPC0_EML_BUSMON_0_BASE)857 858#define mmBMON_REDUCTION_OFFSET \859 (mmDCORE0_TPC0_EML_BUSMON_0_REDUCTION - \860 mmDCORE0_TPC0_EML_BUSMON_0_BASE)861 862#define mmBMON_IDL_OFFSET \863 (mmDCORE0_TPC0_EML_BUSMON_0_IDL - \864 mmDCORE0_TPC0_EML_BUSMON_0_BASE)865 866#define mmBMON_IDH_OFFSET \867 (mmDCORE0_TPC0_EML_BUSMON_0_IDH - \868 mmDCORE0_TPC0_EML_BUSMON_0_BASE)869 870#define mmBMON_IDENL_OFFSET \871 (mmDCORE0_TPC0_EML_BUSMON_0_IDENL - \872 mmDCORE0_TPC0_EML_BUSMON_0_BASE)873 874#define mmBMON_IDENH_OFFSET \875 (mmDCORE0_TPC0_EML_BUSMON_0_IDENH - \876 mmDCORE0_TPC0_EML_BUSMON_0_BASE)877 878#define mmBMON_LATENCY_SMP_OFFSET \879 (mmDCORE0_TPC0_EML_BUSMON_0_LATENCY_SMP - \880 mmDCORE0_TPC0_EML_BUSMON_0_BASE)881 882#define mmBMON_ATTR_OFFSET \883 (mmDCORE0_TPC0_EML_BUSMON_0_ATTR - \884 mmDCORE0_TPC0_EML_BUSMON_0_BASE)885 886#define mmBMON_ATTREN_OFFSET \887 (mmDCORE0_TPC0_EML_BUSMON_0_ATTREN - \888 mmDCORE0_TPC0_EML_BUSMON_0_BASE)889 890#define mmBMON_USRENL_OFFSET \891 (mmDCORE0_TPC0_EML_BUSMON_0_USRENL - \892 mmDCORE0_TPC0_EML_BUSMON_0_BASE)893 894#define mmBMON_USRL_OFFSET \895 (mmDCORE0_TPC0_EML_BUSMON_0_USRL - \896 mmDCORE0_TPC0_EML_BUSMON_0_BASE)897 898#define mmBMON_USRENH_OFFSET \899 (mmDCORE0_TPC0_EML_BUSMON_0_USRENH - \900 mmDCORE0_TPC0_EML_BUSMON_0_BASE)901 902#define mmBMON_USRH_OFFSET \903 (mmDCORE0_TPC0_EML_BUSMON_0_USRH - \904 mmDCORE0_TPC0_EML_BUSMON_0_BASE)905 906#define mmBMON_CAPTURE_OFFSET \907 (mmDCORE0_TPC0_EML_BUSMON_0_CAPTURE - \908 mmDCORE0_TPC0_EML_BUSMON_0_BASE)909 910#define mmBMON_RELEASE_OFFSET \911 (mmDCORE0_TPC0_EML_BUSMON_0_RELEASE - \912 mmDCORE0_TPC0_EML_BUSMON_0_BASE)913 914#define mmBMON_WIN_CAPTURE_OFFSET \915 (mmDCORE0_TPC0_EML_BUSMON_0_WIN_CAPTURE - \916 mmDCORE0_TPC0_EML_BUSMON_0_BASE)917 918#define mmBMON_BW_WIN_OFFSET \919 (mmDCORE0_TPC0_EML_BUSMON_0_BW_WIN - \920 mmDCORE0_TPC0_EML_BUSMON_0_BASE)921 922#define mmBMON_MATCH_CNT_SOD_OFFSET \923 (mmDCORE0_TPC0_EML_BUSMON_0_MATCH_CNT_SOD - \924 mmDCORE0_TPC0_EML_BUSMON_0_BASE)925 926#define mmBMON_MATCH_CNT_WIN_OFFSET \927 (mmDCORE0_TPC0_EML_BUSMON_0_MATCH_CNT_WIN - \928 mmDCORE0_TPC0_EML_BUSMON_0_BASE)929 930#define mmBMON_CYCCNT_L_OFFSET \931 (mmDCORE0_TPC0_EML_BUSMON_0_CYCCNT_L - \932 mmDCORE0_TPC0_EML_BUSMON_0_BASE)933 934#define mmBMON_CYCCNT_H_OFFSET \935 (mmDCORE0_TPC0_EML_BUSMON_0_CYCCNT_H - \936 mmDCORE0_TPC0_EML_BUSMON_0_BASE)937 938#define mmBMON_MAXLAT_SOD_OFFSET \939 (mmDCORE0_TPC0_EML_BUSMON_0_MAXLAT_SOD - \940 mmDCORE0_TPC0_EML_BUSMON_0_BASE)941 942#define mmBMON_MINLAT_SOD_OFFSET \943 (mmDCORE0_TPC0_EML_BUSMON_0_MINLAT_SOD - \944 mmDCORE0_TPC0_EML_BUSMON_0_BASE)945 946#define mmBMON_MAXBW_SOD_OFFSET \947 (mmDCORE0_TPC0_EML_BUSMON_0_MAXBW_SOD - \948 mmDCORE0_TPC0_EML_BUSMON_0_BASE)949 950#define mmBMON_MINBW_SOD_OFFSET \951 (mmDCORE0_TPC0_EML_BUSMON_0_MINBW_SOD - \952 mmDCORE0_TPC0_EML_BUSMON_0_BASE)953 954#define mmBMON_MAXOS_SOD_OFFSET \955 (mmDCORE0_TPC0_EML_BUSMON_0_MAXOS_SOD - \956 mmDCORE0_TPC0_EML_BUSMON_0_BASE)957 958#define mmBMON_MINOS_SOD_OFFSET \959 (mmDCORE0_TPC0_EML_BUSMON_0_MINOS_SOD - \960 mmDCORE0_TPC0_EML_BUSMON_0_BASE)961 962#define mmBMON_ADDRL_SNAPSHOT_OFFSET \963 (mmDCORE0_TPC0_EML_BUSMON_0_ADDRL_SNAPSHOT - \964 mmDCORE0_TPC0_EML_BUSMON_0_BASE)965 966#define mmBMON_ADDRH_SNAPSHOT_OFFSET \967 (mmDCORE0_TPC0_EML_BUSMON_0_ADDRH_SNAPSHOT - \968 mmDCORE0_TPC0_EML_BUSMON_0_BASE)969 970#define mmBMON_IDL_SNAPSHOT_OFFSET \971 (mmDCORE0_TPC0_EML_BUSMON_0_IDL_SNAPSHOT - \972 mmDCORE0_TPC0_EML_BUSMON_0_BASE)973 974#define mmBMON_IDH_SNAPSHOT_OFFSET \975 (mmDCORE0_TPC0_EML_BUSMON_0_IDH_SNAPSHOT - \976 mmDCORE0_TPC0_EML_BUSMON_0_BASE)977 978#define mmBMON_ATTR_SNAPSHOT_OFFSET \979 (mmDCORE0_TPC0_EML_BUSMON_0_ATTR_SNAPSHOT - \980 mmDCORE0_TPC0_EML_BUSMON_0_BASE)981 982#define mmBMON_STM_TRC_OFFSET \983 (mmDCORE0_TPC0_EML_BUSMON_0_STM_TRC - \984 mmDCORE0_TPC0_EML_BUSMON_0_BASE)985 986#define mmBMON_STM_TRC_DROP_OFFSET \987 (mmDCORE0_TPC0_EML_BUSMON_0_STM_TRC_DROP - \988 mmDCORE0_TPC0_EML_BUSMON_0_BASE)989 990#define mmBMON_DEVARCH_OFFSET \991 (mmDCORE0_TPC0_EML_BUSMON_0_DEVARCH - \992 mmDCORE0_TPC0_EML_BUSMON_0_BASE)993 994#define mmBMON_PMDEVID2_OFFSET \995 (mmDCORE0_TPC0_EML_BUSMON_0_PMDEVID2 - \996 mmDCORE0_TPC0_EML_BUSMON_0_BASE)997 998#define mmBMON_PMDEVID1_OFFSET \999 (mmDCORE0_TPC0_EML_BUSMON_0_PMDEVID1 - \1000 mmDCORE0_TPC0_EML_BUSMON_0_BASE)1001 1002#define mmBMON_PMDEVID_OFFSET \1003 (mmDCORE0_TPC0_EML_BUSMON_0_PMDEVID - \1004 mmDCORE0_TPC0_EML_BUSMON_0_BASE)1005 1006#define mmBMON_DEVTYPE_OFFSET \1007 (mmDCORE0_TPC0_EML_BUSMON_0_DEVTYPE - \1008 mmDCORE0_TPC0_EML_BUSMON_0_BASE)1009 1010#define mmBMON_PIDR4_OFFSET \1011 (mmDCORE0_TPC0_EML_BUSMON_0_PIDR4 - \1012 mmDCORE0_TPC0_EML_BUSMON_0_BASE)1013 1014#define mmBMON_PIDR5_OFFSET \1015 (mmDCORE0_TPC0_EML_BUSMON_0_PIDR5 - \1016 mmDCORE0_TPC0_EML_BUSMON_0_BASE)1017 1018#define mmBMON_PIDR6_OFFSET \1019 (mmDCORE0_TPC0_EML_BUSMON_0_PIDR6 - \1020 mmDCORE0_TPC0_EML_BUSMON_0_BASE)1021 1022#define mmBMON_PIDR7_OFFSET \1023 (mmDCORE0_TPC0_EML_BUSMON_0_PIDR7 - \1024 mmDCORE0_TPC0_EML_BUSMON_0_BASE)1025 1026#define mmBMON_PIDR0_OFFSET \1027 (mmDCORE0_TPC0_EML_BUSMON_0_PIDR0 - \1028 mmDCORE0_TPC0_EML_BUSMON_0_BASE)1029 1030#define mmBMON_PIDR1_OFFSET \1031 (mmDCORE0_TPC0_EML_BUSMON_0_PIDR1 - \1032 mmDCORE0_TPC0_EML_BUSMON_0_BASE)1033 1034#define mmBMON_PIDR2_OFFSET \1035 (mmDCORE0_TPC0_EML_BUSMON_0_PIDR2 - \1036 mmDCORE0_TPC0_EML_BUSMON_0_BASE)1037 1038#define mmBMON_PIDR3_OFFSET \1039 (mmDCORE0_TPC0_EML_BUSMON_0_PIDR3 - \1040 mmDCORE0_TPC0_EML_BUSMON_0_BASE)1041 1042#define mmBMON_CIDR0_OFFSET \1043 (mmDCORE0_TPC0_EML_BUSMON_0_CIDR0 - \1044 mmDCORE0_TPC0_EML_BUSMON_0_BASE)1045 1046#define mmBMON_CIDR1_OFFSET \1047 (mmDCORE0_TPC0_EML_BUSMON_0_CIDR1 - \1048 mmDCORE0_TPC0_EML_BUSMON_0_BASE)1049 1050#define mmBMON_CIDR2_OFFSET \1051 (mmDCORE0_TPC0_EML_BUSMON_0_CIDR2 - \1052 mmDCORE0_TPC0_EML_BUSMON_0_BASE)1053 1054#define mmBMON_CIDR3_OFFSET \1055 (mmDCORE0_TPC0_EML_BUSMON_0_CIDR3 - \1056 mmDCORE0_TPC0_EML_BUSMON_0_BASE)1057 1058 1059/* Coresight unlock offset */1060#define mmCORESIGHT_UNLOCK_REGISTER_OFFSET mmSTM_STMLAR_OFFSET1061#define mmCORESIGHT_UNLOCK_STATUS_REGISTER_OFFSET mmSTM_STMLSR_OFFSET1062 1063#endif /* GAUDI2_CORESIGHT_REGS_DRV_H_ */1064