brintos / linux-shallow public Read only

1// SPDX-License-Identifier: GPL-2.02 3/*4 * Copyright 2020-2022 HabanaLabs, Ltd.5 * All Rights Reserved.6 */7 8#include "gaudi2P.h"9#include "../include/gaudi2/asic_reg/gaudi2_regs.h"10 11#define UNSET_GLBL_SEC_BIT(array, b) ((array)[((b) / 32)] |= (1 << ((b) % 32)))12 13#define SPECIAL_GLBL_ERR_CAUSE_APB_PRIV_RD PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_APB_PRIV_RD_MASK14#define SPECIAL_GLBL_ERR_CAUSE_APB_SEC_RD PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_APB_SEC_RD_MASK15#define SPECIAL_GLBL_ERR_CAUSE_APB_PRIV_WR PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_APB_PRIV_WR_MASK16#define SPECIAL_GLBL_ERR_CAUSE_APB_SEC_WR PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_APB_SEC_WR_MASK17#define SPECIAL_GLBL_ERR_CAUSE_EXT_SEC_WR PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_EXT_SEC_WR_MASK18#define SPECIAL_GLBL_ERR_CAUSE_APB_UNMAPPED_RD \19		PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_APB_UNMAPPED_RD_MASK20#define SPECIAL_GLBL_ERR_CAUSE_APB_UNMAPPED_WR \21		PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_APB_UNMAPPED_WR_MASK22#define SPECIAL_GLBL_ERR_CAUSE_EXT_UNMAPPED_WR \23		PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_EXT_UNMAPPED_WR_MASK24 25/* LBW RR */26#define SFT_NUM_OF_LBW_RTR		127#define SFT_LBW_RTR_OFFSET		028#define RR_LBW_LONG_MASK		0x7FFFFFFull29#define RR_LBW_SHORT_MASK		0x7FFF000ull30 31/* HBW RR */32#define SFT_NUM_OF_HBW_RTR		233#define RR_HBW_SHORT_LO_MASK		0xFFFFFFFF000ull34#define RR_HBW_SHORT_HI_MASK		0xF00000000000ull35#define RR_HBW_LONG_LO_MASK		0xFFFFFFFF000ull36#define RR_HBW_LONG_HI_MASK		0xFFFFF00000000000ull37 38struct rr_config {39	u64 min;40	u64 max;41	u32 index;42	u8 type;43};44 45struct gaudi2_atypical_bp_blocks {46	u32 mm_block_base_addr;47	u32 block_size;48	u32 glbl_sec_offset;49	u32 glbl_sec_length;50};51 52static const struct gaudi2_atypical_bp_blocks gaudi2_pb_dcr0_sm_objs = {53	mmDCORE0_SYNC_MNGR_OBJS_BASE,54	128 * 1024,55	SM_OBJS_PROT_BITS_OFFS,56	64057};58 59static const u32 gaudi2_pb_sft0[] = {60	mmSFT0_HBW_RTR_IF0_RTR_CTRL_BASE,61	mmSFT0_HBW_RTR_IF0_RTR_H3_BASE,62	mmSFT0_HBW_RTR_IF0_MSTR_IF_RR_SHRD_HBW_BASE,63	mmSFT0_HBW_RTR_IF0_ADDR_DEC_HBW_BASE,64	mmSFT0_HBW_RTR_IF1_RTR_CTRL_BASE,65	mmSFT0_HBW_RTR_IF1_RTR_H3_BASE,66	mmSFT0_HBW_RTR_IF1_MSTR_IF_RR_SHRD_HBW_BASE,67	mmSFT0_HBW_RTR_IF1_ADDR_DEC_HBW_BASE,68	mmSFT0_LBW_RTR_IF_RTR_CTRL_BASE,69	mmSFT0_LBW_RTR_IF_RTR_H3_BASE,70	mmSFT0_LBW_RTR_IF_MSTR_IF_RR_SHRD_HBW_BASE,71	mmSFT0_LBW_RTR_IF_ADDR_DEC_HBW_BASE,72	mmSFT0_BASE,73};74 75static const u32 gaudi2_pb_dcr0_hif[] = {76	mmDCORE0_HIF0_BASE,77};78 79static const u32 gaudi2_pb_dcr0_rtr0[] = {80	mmDCORE0_RTR0_CTRL_BASE,81	mmDCORE0_RTR0_H3_BASE,82	mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE,83	mmDCORE0_RTR0_ADD_DEC_HBW_BASE,84	mmDCORE0_RTR0_BASE,85	mmDCORE0_RTR0_DBG_ADDR_BASE,86};87 88static const u32 gaudi2_pb_dcr0_hmmu0[] = {89	mmDCORE0_HMMU0_MMU_BASE,90	mmDCORE0_HMMU0_MSTR_IF_RR_SHRD_HBW_BASE,91	mmDCORE0_HMMU0_SCRAMB_OUT_BASE,92	mmDCORE0_HMMU0_STLB_BASE,93};94 95static const u32 gaudi2_pb_cpu_if[] = {96	mmCPU_IF_BASE,97};98 99static const u32 gaudi2_pb_cpu[] = {100	mmCPU_CA53_CFG_BASE,101	mmCPU_MSTR_IF_RR_SHRD_HBW_BASE,102};103 104static const u32 gaudi2_pb_kdma[] = {105	mmARC_FARM_KDMA_BASE,106	mmARC_FARM_KDMA_MSTR_IF_RR_SHRD_HBW_BASE,107};108 109static const u32 gaudi2_pb_pdma0[] = {110	mmPDMA0_CORE_BASE,111	mmPDMA0_MSTR_IF_RR_SHRD_HBW_BASE,112	mmPDMA0_QM_BASE,113};114 115static const u32 gaudi2_pb_pdma0_arc[] = {116	mmPDMA0_QM_ARC_AUX_BASE,117};118 119static const struct range gaudi2_pb_pdma0_arc_unsecured_regs[] = {120	{mmPDMA0_QM_ARC_AUX_RUN_HALT_REQ, mmPDMA0_QM_ARC_AUX_RUN_HALT_ACK},121	{mmPDMA0_QM_ARC_AUX_CLUSTER_NUM, mmPDMA0_QM_ARC_AUX_WAKE_UP_EVENT},122	{mmPDMA0_QM_ARC_AUX_ARC_RST_REQ, mmPDMA0_QM_ARC_AUX_CID_OFFSET_7},123	{mmPDMA0_QM_ARC_AUX_SCRATCHPAD_0, mmPDMA0_QM_ARC_AUX_INFLIGHT_LBU_RD_CNT},124	{mmPDMA0_QM_ARC_AUX_CBU_EARLY_BRESP_EN, mmPDMA0_QM_ARC_AUX_CBU_EARLY_BRESP_EN},125	{mmPDMA0_QM_ARC_AUX_LBU_EARLY_BRESP_EN, mmPDMA0_QM_ARC_AUX_LBU_EARLY_BRESP_EN},126	{mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_0, mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_ALERT_MSG},127	{mmPDMA0_QM_ARC_AUX_DCCM_Q_PUSH_FIFO_CNT, mmPDMA0_QM_ARC_AUX_QMAN_ARC_CQ_SHADOW_CI},128	{mmPDMA0_QM_ARC_AUX_ARC_AXI_ORDERING_WR_IF_CNT, mmPDMA0_QM_ARC_AUX_MME_ARC_UPPER_DCCM_EN},129};130 131static const u32 gaudi2_pb_pdma0_unsecured_regs[] = {132	mmPDMA0_CORE_CTX_AXUSER_HB_WR_REDUCTION,133	mmPDMA0_CORE_CTX_WR_COMP_ADDR_HI,134	mmPDMA0_CORE_CTX_WR_COMP_ADDR_LO,135	mmPDMA0_CORE_CTX_WR_COMP_WDATA,136	mmPDMA0_CORE_CTX_SRC_BASE_LO,137	mmPDMA0_CORE_CTX_SRC_BASE_HI,138	mmPDMA0_CORE_CTX_DST_BASE_LO,139	mmPDMA0_CORE_CTX_DST_BASE_HI,140	mmPDMA0_CORE_CTX_SRC_TSIZE_0,141	mmPDMA0_CORE_CTX_SRC_TSIZE_1,142	mmPDMA0_CORE_CTX_SRC_TSIZE_2,143	mmPDMA0_CORE_CTX_SRC_TSIZE_3,144	mmPDMA0_CORE_CTX_SRC_TSIZE_4,145	mmPDMA0_CORE_CTX_SRC_STRIDE_1,146	mmPDMA0_CORE_CTX_SRC_STRIDE_2,147	mmPDMA0_CORE_CTX_SRC_STRIDE_3,148	mmPDMA0_CORE_CTX_SRC_STRIDE_4,149	mmPDMA0_CORE_CTX_SRC_OFFSET_LO,150	mmPDMA0_CORE_CTX_SRC_OFFSET_HI,151	mmPDMA0_CORE_CTX_DST_TSIZE_0,152	mmPDMA0_CORE_CTX_DST_TSIZE_1,153	mmPDMA0_CORE_CTX_DST_TSIZE_2,154	mmPDMA0_CORE_CTX_DST_TSIZE_3,155	mmPDMA0_CORE_CTX_DST_TSIZE_4,156	mmPDMA0_CORE_CTX_DST_STRIDE_1,157	mmPDMA0_CORE_CTX_DST_STRIDE_2,158	mmPDMA0_CORE_CTX_DST_STRIDE_3,159	mmPDMA0_CORE_CTX_DST_STRIDE_4,160	mmPDMA0_CORE_CTX_DST_OFFSET_LO,161	mmPDMA0_CORE_CTX_DST_OFFSET_HI,162	mmPDMA0_CORE_CTX_COMMIT,163	mmPDMA0_CORE_CTX_CTRL,164	mmPDMA0_CORE_CTX_TE_NUMROWS,165	mmPDMA0_CORE_CTX_IDX,166	mmPDMA0_CORE_CTX_IDX_INC,167	mmPDMA0_QM_CQ_CFG0_0,168	mmPDMA0_QM_CQ_CFG0_1,169	mmPDMA0_QM_CQ_CFG0_2,170	mmPDMA0_QM_CQ_CFG0_3,171	mmPDMA0_QM_CQ_CFG0_4,172	mmPDMA0_QM_CP_FENCE0_RDATA_0,173	mmPDMA0_QM_CP_FENCE0_RDATA_1,174	mmPDMA0_QM_CP_FENCE0_RDATA_2,175	mmPDMA0_QM_CP_FENCE0_RDATA_3,176	mmPDMA0_QM_CP_FENCE0_RDATA_4,177	mmPDMA0_QM_CP_FENCE1_RDATA_0,178	mmPDMA0_QM_CP_FENCE1_RDATA_1,179	mmPDMA0_QM_CP_FENCE1_RDATA_2,180	mmPDMA0_QM_CP_FENCE1_RDATA_3,181	mmPDMA0_QM_CP_FENCE1_RDATA_4,182	mmPDMA0_QM_CP_FENCE2_RDATA_0,183	mmPDMA0_QM_CP_FENCE2_RDATA_1,184	mmPDMA0_QM_CP_FENCE2_RDATA_2,185	mmPDMA0_QM_CP_FENCE2_RDATA_3,186	mmPDMA0_QM_CP_FENCE2_RDATA_4,187	mmPDMA0_QM_CP_FENCE3_RDATA_0,188	mmPDMA0_QM_CP_FENCE3_RDATA_1,189	mmPDMA0_QM_CP_FENCE3_RDATA_2,190	mmPDMA0_QM_CP_FENCE3_RDATA_3,191	mmPDMA0_QM_CP_FENCE3_RDATA_4,192	mmPDMA0_QM_CP_FENCE0_CNT_0,193	mmPDMA0_QM_CP_FENCE0_CNT_1,194	mmPDMA0_QM_CP_FENCE0_CNT_2,195	mmPDMA0_QM_CP_FENCE0_CNT_3,196	mmPDMA0_QM_CP_FENCE0_CNT_4,197	mmPDMA0_QM_CP_FENCE1_CNT_0,198	mmPDMA0_QM_CP_FENCE1_CNT_1,199	mmPDMA0_QM_CP_FENCE1_CNT_2,200	mmPDMA0_QM_CP_FENCE1_CNT_3,201	mmPDMA0_QM_CP_FENCE1_CNT_4,202	mmPDMA0_QM_CP_FENCE2_CNT_0,203	mmPDMA0_QM_CP_FENCE2_CNT_1,204	mmPDMA0_QM_CP_FENCE2_CNT_2,205	mmPDMA0_QM_CP_FENCE2_CNT_3,206	mmPDMA0_QM_CP_FENCE2_CNT_4,207	mmPDMA0_QM_CP_FENCE3_CNT_0,208	mmPDMA0_QM_CP_FENCE3_CNT_1,209	mmPDMA0_QM_CP_FENCE3_CNT_2,210	mmPDMA0_QM_CP_FENCE3_CNT_3,211	mmPDMA0_QM_CP_FENCE3_CNT_4,212	mmPDMA0_QM_CQ_PTR_LO_0,213	mmPDMA0_QM_CQ_PTR_HI_0,214	mmPDMA0_QM_CQ_TSIZE_0,215	mmPDMA0_QM_CQ_CTL_0,216	mmPDMA0_QM_CQ_PTR_LO_1,217	mmPDMA0_QM_CQ_PTR_HI_1,218	mmPDMA0_QM_CQ_TSIZE_1,219	mmPDMA0_QM_CQ_CTL_1,220	mmPDMA0_QM_CQ_PTR_LO_2,221	mmPDMA0_QM_CQ_PTR_HI_2,222	mmPDMA0_QM_CQ_TSIZE_2,223	mmPDMA0_QM_CQ_CTL_2,224	mmPDMA0_QM_CQ_PTR_LO_3,225	mmPDMA0_QM_CQ_PTR_HI_3,226	mmPDMA0_QM_CQ_TSIZE_3,227	mmPDMA0_QM_CQ_CTL_3,228	mmPDMA0_QM_CQ_PTR_LO_4,229	mmPDMA0_QM_CQ_PTR_HI_4,230	mmPDMA0_QM_CQ_TSIZE_4,231	mmPDMA0_QM_CQ_CTL_4,232	mmPDMA0_QM_QMAN_WR64_BASE_ADDR0_BASE,233	mmPDMA0_QM_QMAN_WR64_BASE_ADDR0_BASE + 4,234	mmPDMA0_QM_QMAN_WR64_BASE_ADDR1_BASE,235	mmPDMA0_QM_QMAN_WR64_BASE_ADDR1_BASE + 4,236	mmPDMA0_QM_QMAN_WR64_BASE_ADDR2_BASE,237	mmPDMA0_QM_QMAN_WR64_BASE_ADDR2_BASE + 4,238	mmPDMA0_QM_QMAN_WR64_BASE_ADDR3_BASE,239	mmPDMA0_QM_QMAN_WR64_BASE_ADDR3_BASE + 4,240	mmPDMA0_QM_QMAN_WR64_BASE_ADDR4_BASE,241	mmPDMA0_QM_QMAN_WR64_BASE_ADDR4_BASE + 4,242	mmPDMA0_QM_QMAN_WR64_BASE_ADDR5_BASE,243	mmPDMA0_QM_QMAN_WR64_BASE_ADDR5_BASE + 4,244	mmPDMA0_QM_QMAN_WR64_BASE_ADDR6_BASE,245	mmPDMA0_QM_QMAN_WR64_BASE_ADDR6_BASE + 4,246	mmPDMA0_QM_QMAN_WR64_BASE_ADDR7_BASE,247	mmPDMA0_QM_QMAN_WR64_BASE_ADDR7_BASE + 4,248	mmPDMA0_QM_QMAN_WR64_BASE_ADDR8_BASE,249	mmPDMA0_QM_QMAN_WR64_BASE_ADDR8_BASE + 4,250	mmPDMA0_QM_QMAN_WR64_BASE_ADDR9_BASE,251	mmPDMA0_QM_QMAN_WR64_BASE_ADDR9_BASE + 4,252	mmPDMA0_QM_QMAN_WR64_BASE_ADDR10_BASE,253	mmPDMA0_QM_QMAN_WR64_BASE_ADDR10_BASE + 4,254	mmPDMA0_QM_QMAN_WR64_BASE_ADDR11_BASE,255	mmPDMA0_QM_QMAN_WR64_BASE_ADDR11_BASE + 4,256	mmPDMA0_QM_QMAN_WR64_BASE_ADDR12_BASE,257	mmPDMA0_QM_QMAN_WR64_BASE_ADDR12_BASE + 4,258	mmPDMA0_QM_QMAN_WR64_BASE_ADDR13_BASE,259	mmPDMA0_QM_QMAN_WR64_BASE_ADDR13_BASE + 4,260	mmPDMA0_QM_QMAN_WR64_BASE_ADDR14_BASE,261	mmPDMA0_QM_QMAN_WR64_BASE_ADDR14_BASE + 4,262	mmPDMA0_QM_QMAN_WR64_BASE_ADDR15_BASE,263	mmPDMA0_QM_QMAN_WR64_BASE_ADDR15_BASE + 4,264	mmPDMA0_QM_ARC_CQ_PTR_LO,265	mmPDMA0_QM_ARC_CQ_PTR_LO_STS,266	mmPDMA0_QM_ARC_CQ_PTR_HI,267	mmPDMA0_QM_ARC_CQ_PTR_HI_STS,268	mmPDMA0_QM_ARB_CFG_0,269	mmPDMA0_QM_ARB_MST_QUIET_PER,270	mmPDMA0_QM_ARB_CHOICE_Q_PUSH,271	mmPDMA0_QM_ARB_WRR_WEIGHT_0,272	mmPDMA0_QM_ARB_WRR_WEIGHT_1,273	mmPDMA0_QM_ARB_WRR_WEIGHT_2,274	mmPDMA0_QM_ARB_WRR_WEIGHT_3,275	mmPDMA0_QM_ARB_BASE_LO,276	mmPDMA0_QM_ARB_BASE_HI,277	mmPDMA0_QM_ARB_MST_SLAVE_EN,278	mmPDMA0_QM_ARB_MST_SLAVE_EN_1,279	mmPDMA0_QM_ARB_MST_CRED_INC,280	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_0,281	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_1,282	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_2,283	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_3,284	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_4,285	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_5,286	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_6,287	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_7,288	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_8,289	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_9,290	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_10,291	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_11,292	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_12,293	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_13,294	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_14,295	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_15,296	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_16,297	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_17,298	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_18,299	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_19,300	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_20,301	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_21,302	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_22,303	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_23,304	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_24,305	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_25,306	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_26,307	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_27,308	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_28,309	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_29,310	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_30,311	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_31,312	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_32,313	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_33,314	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_34,315	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_35,316	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_36,317	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_37,318	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_38,319	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_39,320	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_40,321	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_41,322	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_42,323	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_43,324	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_44,325	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_45,326	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_46,327	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_47,328	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_48,329	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_49,330	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_50,331	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_51,332	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_52,333	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_53,334	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_54,335	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_55,336	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_56,337	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_57,338	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_58,339	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_59,340	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_60,341	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_61,342	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_62,343	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_63,344	mmPDMA0_QM_ARB_SLV_ID,345	mmPDMA0_QM_ARB_SLV_MASTER_INC_CRED_OFST,346	mmPDMA0_QM_ARC_CQ_CFG0,347	mmPDMA0_QM_CQ_IFIFO_CI_0,348	mmPDMA0_QM_CQ_IFIFO_CI_1,349	mmPDMA0_QM_CQ_IFIFO_CI_2,350	mmPDMA0_QM_CQ_IFIFO_CI_3,351	mmPDMA0_QM_CQ_IFIFO_CI_4,352	mmPDMA0_QM_ARC_CQ_IFIFO_CI,353	mmPDMA0_QM_CQ_CTL_CI_0,354	mmPDMA0_QM_CQ_CTL_CI_1,355	mmPDMA0_QM_CQ_CTL_CI_2,356	mmPDMA0_QM_CQ_CTL_CI_3,357	mmPDMA0_QM_CQ_CTL_CI_4,358	mmPDMA0_QM_ARC_CQ_CTL_CI,359	mmPDMA0_QM_ARC_CQ_TSIZE,360	mmPDMA0_QM_ARC_CQ_CTL,361	mmPDMA0_QM_CP_SWITCH_WD_SET,362	mmPDMA0_QM_CP_EXT_SWITCH,363	mmPDMA0_QM_CP_PRED_0,364	mmPDMA0_QM_CP_PRED_1,365	mmPDMA0_QM_CP_PRED_2,366	mmPDMA0_QM_CP_PRED_3,367	mmPDMA0_QM_CP_PRED_4,368	mmPDMA0_QM_CP_PRED_UPEN_0,369	mmPDMA0_QM_CP_PRED_UPEN_1,370	mmPDMA0_QM_CP_PRED_UPEN_2,371	mmPDMA0_QM_CP_PRED_UPEN_3,372	mmPDMA0_QM_CP_PRED_UPEN_4,373	mmPDMA0_QM_CP_MSG_BASE0_ADDR_LO_0,374	mmPDMA0_QM_CP_MSG_BASE0_ADDR_LO_1,375	mmPDMA0_QM_CP_MSG_BASE0_ADDR_LO_2,376	mmPDMA0_QM_CP_MSG_BASE0_ADDR_LO_3,377	mmPDMA0_QM_CP_MSG_BASE0_ADDR_LO_4,378	mmPDMA0_QM_CP_MSG_BASE0_ADDR_HI_0,379	mmPDMA0_QM_CP_MSG_BASE0_ADDR_HI_1,380	mmPDMA0_QM_CP_MSG_BASE0_ADDR_HI_2,381	mmPDMA0_QM_CP_MSG_BASE0_ADDR_HI_3,382	mmPDMA0_QM_CP_MSG_BASE0_ADDR_HI_4,383	mmPDMA0_QM_CP_MSG_BASE1_ADDR_LO_0,384	mmPDMA0_QM_CP_MSG_BASE1_ADDR_LO_1,385	mmPDMA0_QM_CP_MSG_BASE1_ADDR_LO_2,386	mmPDMA0_QM_CP_MSG_BASE1_ADDR_LO_3,387	mmPDMA0_QM_CP_MSG_BASE1_ADDR_LO_4,388	mmPDMA0_QM_CP_MSG_BASE1_ADDR_HI_0,389	mmPDMA0_QM_CP_MSG_BASE1_ADDR_HI_1,390	mmPDMA0_QM_CP_MSG_BASE1_ADDR_HI_2,391	mmPDMA0_QM_CP_MSG_BASE1_ADDR_HI_3,392	mmPDMA0_QM_CP_MSG_BASE1_ADDR_HI_4,393	mmPDMA0_QM_CP_MSG_BASE2_ADDR_LO_0,394	mmPDMA0_QM_CP_MSG_BASE2_ADDR_LO_1,395	mmPDMA0_QM_CP_MSG_BASE2_ADDR_LO_2,396	mmPDMA0_QM_CP_MSG_BASE2_ADDR_LO_3,397	mmPDMA0_QM_CP_MSG_BASE2_ADDR_LO_4,398	mmPDMA0_QM_CP_MSG_BASE2_ADDR_HI_0,399	mmPDMA0_QM_CP_MSG_BASE2_ADDR_HI_1,400	mmPDMA0_QM_CP_MSG_BASE2_ADDR_HI_2,401	mmPDMA0_QM_CP_MSG_BASE2_ADDR_HI_3,402	mmPDMA0_QM_CP_MSG_BASE2_ADDR_HI_4,403	mmPDMA0_QM_CP_MSG_BASE3_ADDR_LO_0,404	mmPDMA0_QM_CP_MSG_BASE3_ADDR_LO_1,405	mmPDMA0_QM_CP_MSG_BASE3_ADDR_LO_2,406	mmPDMA0_QM_CP_MSG_BASE3_ADDR_LO_3,407	mmPDMA0_QM_CP_MSG_BASE3_ADDR_LO_4,408	mmPDMA0_QM_CP_MSG_BASE3_ADDR_HI_0,409	mmPDMA0_QM_CP_MSG_BASE3_ADDR_HI_1,410	mmPDMA0_QM_CP_MSG_BASE3_ADDR_HI_2,411	mmPDMA0_QM_CP_MSG_BASE3_ADDR_HI_3,412	mmPDMA0_QM_CP_MSG_BASE3_ADDR_HI_4,413	mmPDMA0_QM_ARC_CQ_IFIFO_MSG_BASE_LO,414	mmPDMA0_QM_ARC_CQ_CTL_MSG_BASE_LO,415	mmPDMA0_QM_CQ_IFIFO_MSG_BASE_LO,416	mmPDMA0_QM_CQ_CTL_MSG_BASE_LO417};418 419static const u32 gaudi2_pb_dcr0_edma0[] = {420	mmDCORE0_EDMA0_CORE_BASE,421	mmDCORE0_EDMA0_MSTR_IF_RR_SHRD_HBW_BASE,422	mmDCORE0_EDMA0_QM_BASE,423};424 425static const u32 gaudi2_pb_dcr0_edma0_arc[] = {426	mmDCORE0_EDMA0_QM_ARC_AUX_BASE,427};428 429static const struct range gaudi2_pb_dcr0_edma0_arc_unsecured_regs[] = {430	{mmDCORE0_EDMA0_QM_ARC_AUX_RUN_HALT_REQ, mmDCORE0_EDMA0_QM_ARC_AUX_RUN_HALT_ACK},431	{mmDCORE0_EDMA0_QM_ARC_AUX_CLUSTER_NUM, mmDCORE0_EDMA0_QM_ARC_AUX_WAKE_UP_EVENT},432	{mmDCORE0_EDMA0_QM_ARC_AUX_ARC_RST_REQ, mmDCORE0_EDMA0_QM_ARC_AUX_CID_OFFSET_7},433	{mmDCORE0_EDMA0_QM_ARC_AUX_SCRATCHPAD_0, mmDCORE0_EDMA0_QM_ARC_AUX_INFLIGHT_LBU_RD_CNT},434	{mmDCORE0_EDMA0_QM_ARC_AUX_CBU_EARLY_BRESP_EN,435		mmDCORE0_EDMA0_QM_ARC_AUX_CBU_EARLY_BRESP_EN},436	{mmDCORE0_EDMA0_QM_ARC_AUX_LBU_EARLY_BRESP_EN,437		mmDCORE0_EDMA0_QM_ARC_AUX_LBU_EARLY_BRESP_EN},438	{mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_0,439		mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_ALERT_MSG},440	{mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_Q_PUSH_FIFO_CNT,441		mmDCORE0_EDMA0_QM_ARC_AUX_QMAN_ARC_CQ_SHADOW_CI},442	{mmDCORE0_EDMA0_QM_ARC_AUX_ARC_AXI_ORDERING_WR_IF_CNT,443		mmDCORE0_EDMA0_QM_ARC_AUX_MME_ARC_UPPER_DCCM_EN},444};445 446static const u32 gaudi2_pb_dcr0_edma0_unsecured_regs[] = {447	mmDCORE0_EDMA0_CORE_CTX_AXUSER_HB_WR_REDUCTION,448	mmDCORE0_EDMA0_CORE_CTX_WR_COMP_ADDR_HI,449	mmDCORE0_EDMA0_CORE_CTX_WR_COMP_ADDR_LO,450	mmDCORE0_EDMA0_CORE_CTX_WR_COMP_WDATA,451	mmDCORE0_EDMA0_CORE_CTX_SRC_BASE_LO,452	mmDCORE0_EDMA0_CORE_CTX_SRC_BASE_HI,453	mmDCORE0_EDMA0_CORE_CTX_DST_BASE_LO,454	mmDCORE0_EDMA0_CORE_CTX_DST_BASE_HI,455	mmDCORE0_EDMA0_CORE_CTX_SRC_TSIZE_0,456	mmDCORE0_EDMA0_CORE_CTX_SRC_TSIZE_1,457	mmDCORE0_EDMA0_CORE_CTX_SRC_TSIZE_2,458	mmDCORE0_EDMA0_CORE_CTX_SRC_TSIZE_3,459	mmDCORE0_EDMA0_CORE_CTX_SRC_TSIZE_4,460	mmDCORE0_EDMA0_CORE_CTX_SRC_STRIDE_1,461	mmDCORE0_EDMA0_CORE_CTX_SRC_STRIDE_2,462	mmDCORE0_EDMA0_CORE_CTX_SRC_STRIDE_3,463	mmDCORE0_EDMA0_CORE_CTX_SRC_STRIDE_4,464	mmDCORE0_EDMA0_CORE_CTX_SRC_OFFSET_LO,465	mmDCORE0_EDMA0_CORE_CTX_SRC_OFFSET_HI,466	mmDCORE0_EDMA0_CORE_CTX_DST_TSIZE_0,467	mmDCORE0_EDMA0_CORE_CTX_DST_TSIZE_1,468	mmDCORE0_EDMA0_CORE_CTX_DST_TSIZE_2,469	mmDCORE0_EDMA0_CORE_CTX_DST_TSIZE_3,470	mmDCORE0_EDMA0_CORE_CTX_DST_TSIZE_4,471	mmDCORE0_EDMA0_CORE_CTX_DST_STRIDE_1,472	mmDCORE0_EDMA0_CORE_CTX_DST_STRIDE_2,473	mmDCORE0_EDMA0_CORE_CTX_DST_STRIDE_3,474	mmDCORE0_EDMA0_CORE_CTX_DST_STRIDE_4,475	mmDCORE0_EDMA0_CORE_CTX_DST_OFFSET_LO,476	mmDCORE0_EDMA0_CORE_CTX_DST_OFFSET_HI,477	mmDCORE0_EDMA0_CORE_CTX_COMMIT,478	mmDCORE0_EDMA0_CORE_CTX_CTRL,479	mmDCORE0_EDMA0_CORE_CTX_TE_NUMROWS,480	mmDCORE0_EDMA0_CORE_CTX_IDX,481	mmDCORE0_EDMA0_CORE_CTX_IDX_INC,482	mmDCORE0_EDMA0_CORE_WR_COMP_MAX_OUTSTAND,483	mmDCORE0_EDMA0_CORE_RD_LBW_RATE_LIM_CFG,484	mmDCORE0_EDMA0_QM_CQ_CFG0_0,485	mmDCORE0_EDMA0_QM_CQ_CFG0_1,486	mmDCORE0_EDMA0_QM_CQ_CFG0_2,487	mmDCORE0_EDMA0_QM_CQ_CFG0_3,488	mmDCORE0_EDMA0_QM_CQ_CFG0_4,489	mmDCORE0_EDMA0_QM_CP_FENCE0_RDATA_0,490	mmDCORE0_EDMA0_QM_CP_FENCE0_RDATA_1,491	mmDCORE0_EDMA0_QM_CP_FENCE0_RDATA_2,492	mmDCORE0_EDMA0_QM_CP_FENCE0_RDATA_3,493	mmDCORE0_EDMA0_QM_CP_FENCE0_RDATA_4,494	mmDCORE0_EDMA0_QM_CP_FENCE1_RDATA_0,495	mmDCORE0_EDMA0_QM_CP_FENCE1_RDATA_1,496	mmDCORE0_EDMA0_QM_CP_FENCE1_RDATA_2,497	mmDCORE0_EDMA0_QM_CP_FENCE1_RDATA_3,498	mmDCORE0_EDMA0_QM_CP_FENCE1_RDATA_4,499	mmDCORE0_EDMA0_QM_CP_FENCE2_RDATA_0,500	mmDCORE0_EDMA0_QM_CP_FENCE2_RDATA_1,501	mmDCORE0_EDMA0_QM_CP_FENCE2_RDATA_2,502	mmDCORE0_EDMA0_QM_CP_FENCE2_RDATA_3,503	mmDCORE0_EDMA0_QM_CP_FENCE2_RDATA_4,504	mmDCORE0_EDMA0_QM_CP_FENCE3_RDATA_0,505	mmDCORE0_EDMA0_QM_CP_FENCE3_RDATA_1,506	mmDCORE0_EDMA0_QM_CP_FENCE3_RDATA_2,507	mmDCORE0_EDMA0_QM_CP_FENCE3_RDATA_3,508	mmDCORE0_EDMA0_QM_CP_FENCE3_RDATA_4,509	mmDCORE0_EDMA0_QM_CP_FENCE0_CNT_0,510	mmDCORE0_EDMA0_QM_CP_FENCE0_CNT_1,511	mmDCORE0_EDMA0_QM_CP_FENCE0_CNT_2,512	mmDCORE0_EDMA0_QM_CP_FENCE0_CNT_3,513	mmDCORE0_EDMA0_QM_CP_FENCE0_CNT_4,514	mmDCORE0_EDMA0_QM_CP_FENCE1_CNT_0,515	mmDCORE0_EDMA0_QM_CP_FENCE1_CNT_1,516	mmDCORE0_EDMA0_QM_CP_FENCE1_CNT_2,517	mmDCORE0_EDMA0_QM_CP_FENCE1_CNT_3,518	mmDCORE0_EDMA0_QM_CP_FENCE1_CNT_4,519	mmDCORE0_EDMA0_QM_CP_FENCE2_CNT_0,520	mmDCORE0_EDMA0_QM_CP_FENCE2_CNT_1,521	mmDCORE0_EDMA0_QM_CP_FENCE2_CNT_2,522	mmDCORE0_EDMA0_QM_CP_FENCE2_CNT_3,523	mmDCORE0_EDMA0_QM_CP_FENCE2_CNT_4,524	mmDCORE0_EDMA0_QM_CP_FENCE3_CNT_0,525	mmDCORE0_EDMA0_QM_CP_FENCE3_CNT_1,526	mmDCORE0_EDMA0_QM_CP_FENCE3_CNT_2,527	mmDCORE0_EDMA0_QM_CP_FENCE3_CNT_3,528	mmDCORE0_EDMA0_QM_CP_FENCE3_CNT_4,529	mmDCORE0_EDMA0_QM_CQ_PTR_LO_0,530	mmDCORE0_EDMA0_QM_CQ_PTR_HI_0,531	mmDCORE0_EDMA0_QM_CQ_TSIZE_0,532	mmDCORE0_EDMA0_QM_CQ_CTL_0,533	mmDCORE0_EDMA0_QM_CQ_PTR_LO_1,534	mmDCORE0_EDMA0_QM_CQ_PTR_HI_1,535	mmDCORE0_EDMA0_QM_CQ_TSIZE_1,536	mmDCORE0_EDMA0_QM_CQ_CTL_1,537	mmDCORE0_EDMA0_QM_CQ_PTR_LO_2,538	mmDCORE0_EDMA0_QM_CQ_PTR_HI_2,539	mmDCORE0_EDMA0_QM_CQ_TSIZE_2,540	mmDCORE0_EDMA0_QM_CQ_CTL_2,541	mmDCORE0_EDMA0_QM_CQ_PTR_LO_3,542	mmDCORE0_EDMA0_QM_CQ_PTR_HI_3,543	mmDCORE0_EDMA0_QM_CQ_TSIZE_3,544	mmDCORE0_EDMA0_QM_CQ_CTL_3,545	mmDCORE0_EDMA0_QM_CQ_PTR_LO_4,546	mmDCORE0_EDMA0_QM_CQ_PTR_HI_4,547	mmDCORE0_EDMA0_QM_CQ_TSIZE_4,548	mmDCORE0_EDMA0_QM_CQ_CTL_4,549	mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR0_BASE,550	mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR0_BASE + 4,551	mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR1_BASE,552	mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR1_BASE + 4,553	mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR2_BASE,554	mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR2_BASE + 4,555	mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR3_BASE,556	mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR3_BASE + 4,557	mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR4_BASE,558	mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR4_BASE + 4,559	mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR5_BASE,560	mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR5_BASE + 4,561	mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR6_BASE,562	mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR6_BASE + 4,563	mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR7_BASE,564	mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR7_BASE + 4,565	mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR8_BASE,566	mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR8_BASE + 4,567	mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR9_BASE,568	mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR9_BASE + 4,569	mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR10_BASE,570	mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR10_BASE + 4,571	mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR11_BASE,572	mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR11_BASE + 4,573	mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR12_BASE,574	mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR12_BASE + 4,575	mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR13_BASE,576	mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR13_BASE + 4,577	mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR14_BASE,578	mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR14_BASE + 4,579	mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR15_BASE,580	mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR15_BASE + 4,581	mmDCORE0_EDMA0_QM_ARC_CQ_PTR_LO,582	mmDCORE0_EDMA0_QM_ARC_CQ_PTR_LO_STS,583	mmDCORE0_EDMA0_QM_ARC_CQ_PTR_HI,584	mmDCORE0_EDMA0_QM_ARC_CQ_PTR_HI_STS,585	mmDCORE0_EDMA0_QM_ARB_CFG_0,586	mmDCORE0_EDMA0_QM_ARB_MST_QUIET_PER,587	mmDCORE0_EDMA0_QM_ARB_CHOICE_Q_PUSH,588	mmDCORE0_EDMA0_QM_ARB_WRR_WEIGHT_0,589	mmDCORE0_EDMA0_QM_ARB_WRR_WEIGHT_1,590	mmDCORE0_EDMA0_QM_ARB_WRR_WEIGHT_2,591	mmDCORE0_EDMA0_QM_ARB_WRR_WEIGHT_3,592	mmDCORE0_EDMA0_QM_ARB_BASE_LO,593	mmDCORE0_EDMA0_QM_ARB_BASE_HI,594	mmDCORE0_EDMA0_QM_ARB_MST_SLAVE_EN,595	mmDCORE0_EDMA0_QM_ARB_MST_SLAVE_EN_1,596	mmDCORE0_EDMA0_QM_ARB_MST_CRED_INC,597	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_0,598	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_1,599	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_2,600	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_3,601	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_4,602	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_5,603	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_6,604	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_7,605	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_8,606	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_9,607	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_10,608	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_11,609	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_12,610	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_13,611	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_14,612	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_15,613	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_16,614	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_17,615	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_18,616	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_19,617	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_20,618	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_21,619	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_22,620	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_23,621	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_24,622	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_25,623	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_26,624	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_27,625	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_28,626	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_29,627	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_30,628	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_31,629	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_32,630	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_33,631	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_34,632	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_35,633	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_36,634	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_37,635	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_38,636	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_39,637	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_40,638	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_41,639	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_42,640	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_43,641	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_44,642	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_45,643	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_46,644	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_47,645	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_48,646	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_49,647	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_50,648	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_51,649	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_52,650	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_53,651	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_54,652	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_55,653	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_56,654	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_57,655	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_58,656	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_59,657	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_60,658	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_61,659	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_62,660	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_63,661	mmDCORE0_EDMA0_QM_ARB_SLV_ID,662	mmDCORE0_EDMA0_QM_ARB_SLV_MASTER_INC_CRED_OFST,663	mmDCORE0_EDMA0_QM_ARC_CQ_CFG0,664	mmDCORE0_EDMA0_QM_CQ_IFIFO_CI_0,665	mmDCORE0_EDMA0_QM_CQ_IFIFO_CI_1,666	mmDCORE0_EDMA0_QM_CQ_IFIFO_CI_2,667	mmDCORE0_EDMA0_QM_CQ_IFIFO_CI_3,668	mmDCORE0_EDMA0_QM_CQ_IFIFO_CI_4,669	mmDCORE0_EDMA0_QM_ARC_CQ_IFIFO_CI,670	mmDCORE0_EDMA0_QM_CQ_CTL_CI_0,671	mmDCORE0_EDMA0_QM_CQ_CTL_CI_1,672	mmDCORE0_EDMA0_QM_CQ_CTL_CI_2,673	mmDCORE0_EDMA0_QM_CQ_CTL_CI_3,674	mmDCORE0_EDMA0_QM_CQ_CTL_CI_4,675	mmDCORE0_EDMA0_QM_ARC_CQ_CTL_CI,676	mmDCORE0_EDMA0_QM_ARC_CQ_TSIZE,677	mmDCORE0_EDMA0_QM_ARC_CQ_CTL,678	mmDCORE0_EDMA0_QM_CP_SWITCH_WD_SET,679	mmDCORE0_EDMA0_QM_CP_EXT_SWITCH,680	mmDCORE0_EDMA0_QM_CP_PRED_0,681	mmDCORE0_EDMA0_QM_CP_PRED_1,682	mmDCORE0_EDMA0_QM_CP_PRED_2,683	mmDCORE0_EDMA0_QM_CP_PRED_3,684	mmDCORE0_EDMA0_QM_CP_PRED_4,685	mmDCORE0_EDMA0_QM_CP_PRED_UPEN_0,686	mmDCORE0_EDMA0_QM_CP_PRED_UPEN_1,687	mmDCORE0_EDMA0_QM_CP_PRED_UPEN_2,688	mmDCORE0_EDMA0_QM_CP_PRED_UPEN_3,689	mmDCORE0_EDMA0_QM_CP_PRED_UPEN_4,690	mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_LO_0,691	mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_LO_1,692	mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_LO_2,693	mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_LO_3,694	mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_LO_4,695	mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_HI_0,696	mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_HI_1,697	mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_HI_2,698	mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_HI_3,699	mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_HI_4,700	mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_LO_0,701	mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_LO_1,702	mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_LO_2,703	mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_LO_3,704	mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_LO_4,705	mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_HI_0,706	mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_HI_1,707	mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_HI_2,708	mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_HI_3,709	mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_HI_4,710	mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_LO_0,711	mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_LO_1,712	mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_LO_2,713	mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_LO_3,714	mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_LO_4,715	mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_HI_0,716	mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_HI_1,717	mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_HI_2,718	mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_HI_3,719	mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_HI_4,720	mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_LO_0,721	mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_LO_1,722	mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_LO_2,723	mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_LO_3,724	mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_LO_4,725	mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_HI_0,726	mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_HI_1,727	mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_HI_2,728	mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_HI_3,729	mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_HI_4,730	mmDCORE0_EDMA0_QM_ARC_CQ_IFIFO_MSG_BASE_LO,731	mmDCORE0_EDMA0_QM_ARC_CQ_CTL_MSG_BASE_LO,732	mmDCORE0_EDMA0_QM_CQ_IFIFO_MSG_BASE_LO,733	mmDCORE0_EDMA0_QM_CQ_CTL_MSG_BASE_LO734};735 736static const u32 gaudi2_pb_dcr0_mme_sbte[] = {737	mmDCORE0_MME_SBTE0_BASE,738	mmDCORE0_MME_SBTE0_MSTR_IF_RR_SHRD_HBW_BASE,739};740 741static const u32 gaudi2_pb_dcr0_mme_qm[] = {742	mmDCORE0_MME_QM_BASE,743};744 745static const u32 gaudi2_pb_dcr0_mme_eng[] = {746	mmDCORE0_MME_ACC_BASE,747	mmDCORE0_MME_CTRL_HI_BASE,748	mmDCORE0_MME_CTRL_LO_BASE,749	mmDCORE0_MME_CTRL_MSTR_IF_RR_SHRD_HBW_BASE,750	mmDCORE0_MME_WB0_MSTR_IF_RR_SHRD_HBW_BASE,751	mmDCORE0_MME_WB1_MSTR_IF_RR_SHRD_HBW_BASE,752};753 754static const u32 gaudi2_pb_dcr0_mme_arc[] = {755	mmDCORE0_MME_QM_ARC_AUX_BASE,756	mmDCORE0_MME_QM_ARC_DUP_ENG_BASE,757};758 759static const struct range gaudi2_pb_dcr0_mme_arc_unsecured_regs[] = {760	{mmDCORE0_MME_QM_ARC_AUX_RUN_HALT_REQ, mmDCORE0_MME_QM_ARC_AUX_RUN_HALT_ACK},761	{mmDCORE0_MME_QM_ARC_AUX_CLUSTER_NUM, mmDCORE0_MME_QM_ARC_AUX_WAKE_UP_EVENT},762	{mmDCORE0_MME_QM_ARC_AUX_ARC_RST_REQ, mmDCORE0_MME_QM_ARC_AUX_CID_OFFSET_7},763	{mmDCORE0_MME_QM_ARC_AUX_SCRATCHPAD_0, mmDCORE0_MME_QM_ARC_AUX_INFLIGHT_LBU_RD_CNT},764	{mmDCORE0_MME_QM_ARC_AUX_CBU_EARLY_BRESP_EN, mmDCORE0_MME_QM_ARC_AUX_CBU_EARLY_BRESP_EN},765	{mmDCORE0_MME_QM_ARC_AUX_LBU_EARLY_BRESP_EN, mmDCORE0_MME_QM_ARC_AUX_LBU_EARLY_BRESP_EN},766	{mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_0,767		mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_ALERT_MSG},768	{mmDCORE0_MME_QM_ARC_AUX_DCCM_Q_PUSH_FIFO_CNT,769		mmDCORE0_MME_QM_ARC_AUX_QMAN_ARC_CQ_SHADOW_CI},770	{mmDCORE0_MME_QM_ARC_AUX_ARC_AXI_ORDERING_WR_IF_CNT,771		mmDCORE0_MME_QM_ARC_AUX_MME_ARC_UPPER_DCCM_EN},772	{mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_ADDR_0,773		mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_63},774	{mmDCORE0_MME_QM_ARC_DUP_ENG_AXUSER_HB_STRONG_ORDER,775		mmDCORE0_MME_QM_ARC_DUP_ENG_AXUSER_LB_OVRD},776};777 778static const u32 gaudi2_pb_dcr0_mme_qm_unsecured_regs[] = {779	mmDCORE0_MME_QM_CQ_CFG0_0,780	mmDCORE0_MME_QM_CQ_CFG0_1,781	mmDCORE0_MME_QM_CQ_CFG0_2,782	mmDCORE0_MME_QM_CQ_CFG0_3,783	mmDCORE0_MME_QM_CQ_CFG0_4,784	mmDCORE0_MME_QM_CP_FENCE0_RDATA_0,785	mmDCORE0_MME_QM_CP_FENCE0_RDATA_1,786	mmDCORE0_MME_QM_CP_FENCE0_RDATA_2,787	mmDCORE0_MME_QM_CP_FENCE0_RDATA_3,788	mmDCORE0_MME_QM_CP_FENCE0_RDATA_4,789	mmDCORE0_MME_QM_CP_FENCE1_RDATA_0,790	mmDCORE0_MME_QM_CP_FENCE1_RDATA_1,791	mmDCORE0_MME_QM_CP_FENCE1_RDATA_2,792	mmDCORE0_MME_QM_CP_FENCE1_RDATA_3,793	mmDCORE0_MME_QM_CP_FENCE1_RDATA_4,794	mmDCORE0_MME_QM_CP_FENCE2_RDATA_0,795	mmDCORE0_MME_QM_CP_FENCE2_RDATA_1,796	mmDCORE0_MME_QM_CP_FENCE2_RDATA_2,797	mmDCORE0_MME_QM_CP_FENCE2_RDATA_3,798	mmDCORE0_MME_QM_CP_FENCE2_RDATA_4,799	mmDCORE0_MME_QM_CP_FENCE3_RDATA_0,800	mmDCORE0_MME_QM_CP_FENCE3_RDATA_1,801	mmDCORE0_MME_QM_CP_FENCE3_RDATA_2,802	mmDCORE0_MME_QM_CP_FENCE3_RDATA_3,803	mmDCORE0_MME_QM_CP_FENCE3_RDATA_4,804	mmDCORE0_MME_QM_CP_FENCE0_CNT_0,805	mmDCORE0_MME_QM_CP_FENCE0_CNT_1,806	mmDCORE0_MME_QM_CP_FENCE0_CNT_2,807	mmDCORE0_MME_QM_CP_FENCE0_CNT_3,808	mmDCORE0_MME_QM_CP_FENCE0_CNT_4,809	mmDCORE0_MME_QM_CP_FENCE1_CNT_0,810	mmDCORE0_MME_QM_CP_FENCE1_CNT_1,811	mmDCORE0_MME_QM_CP_FENCE1_CNT_2,812	mmDCORE0_MME_QM_CP_FENCE1_CNT_3,813	mmDCORE0_MME_QM_CP_FENCE1_CNT_4,814	mmDCORE0_MME_QM_CP_FENCE2_CNT_0,815	mmDCORE0_MME_QM_CP_FENCE2_CNT_1,816	mmDCORE0_MME_QM_CP_FENCE2_CNT_2,817	mmDCORE0_MME_QM_CP_FENCE2_CNT_3,818	mmDCORE0_MME_QM_CP_FENCE2_CNT_4,819	mmDCORE0_MME_QM_CP_FENCE3_CNT_0,820	mmDCORE0_MME_QM_CP_FENCE3_CNT_1,821	mmDCORE0_MME_QM_CP_FENCE3_CNT_2,822	mmDCORE0_MME_QM_CP_FENCE3_CNT_3,823	mmDCORE0_MME_QM_CP_FENCE3_CNT_4,824	mmDCORE0_MME_QM_CQ_PTR_LO_0,825	mmDCORE0_MME_QM_CQ_PTR_HI_0,826	mmDCORE0_MME_QM_CQ_TSIZE_0,827	mmDCORE0_MME_QM_CQ_CTL_0,828	mmDCORE0_MME_QM_CQ_PTR_LO_1,829	mmDCORE0_MME_QM_CQ_PTR_HI_1,830	mmDCORE0_MME_QM_CQ_TSIZE_1,831	mmDCORE0_MME_QM_CQ_CTL_1,832	mmDCORE0_MME_QM_CQ_PTR_LO_2,833	mmDCORE0_MME_QM_CQ_PTR_HI_2,834	mmDCORE0_MME_QM_CQ_TSIZE_2,835	mmDCORE0_MME_QM_CQ_CTL_2,836	mmDCORE0_MME_QM_CQ_PTR_LO_3,837	mmDCORE0_MME_QM_CQ_PTR_HI_3,838	mmDCORE0_MME_QM_CQ_TSIZE_3,839	mmDCORE0_MME_QM_CQ_CTL_3,840	mmDCORE0_MME_QM_CQ_PTR_LO_4,841	mmDCORE0_MME_QM_CQ_PTR_HI_4,842	mmDCORE0_MME_QM_CQ_TSIZE_4,843	mmDCORE0_MME_QM_CQ_CTL_4,844	mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR0_BASE,845	mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR0_BASE + 4,846	mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR1_BASE,847	mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR1_BASE + 4,848	mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR2_BASE,849	mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR2_BASE + 4,850	mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR3_BASE,851	mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR3_BASE + 4,852	mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR4_BASE,853	mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR4_BASE + 4,854	mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR5_BASE,855	mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR5_BASE + 4,856	mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR6_BASE,857	mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR6_BASE + 4,858	mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR7_BASE,859	mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR7_BASE + 4,860	mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR8_BASE,861	mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR8_BASE + 4,862	mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR9_BASE,863	mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR9_BASE + 4,864	mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR10_BASE,865	mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR10_BASE + 4,866	mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR11_BASE,867	mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR11_BASE + 4,868	mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR12_BASE,869	mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR12_BASE + 4,870	mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR13_BASE,871	mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR13_BASE + 4,872	mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR14_BASE,873	mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR14_BASE + 4,874	mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR15_BASE,875	mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR15_BASE + 4,876	mmDCORE0_MME_QM_ARC_CQ_PTR_LO,877	mmDCORE0_MME_QM_ARC_CQ_PTR_LO_STS,878	mmDCORE0_MME_QM_ARC_CQ_PTR_HI,879	mmDCORE0_MME_QM_ARC_CQ_PTR_HI_STS,880	mmDCORE0_MME_QM_ARB_CFG_0,881	mmDCORE0_MME_QM_ARB_MST_QUIET_PER,882	mmDCORE0_MME_QM_ARB_CHOICE_Q_PUSH,883	mmDCORE0_MME_QM_ARB_WRR_WEIGHT_0,884	mmDCORE0_MME_QM_ARB_WRR_WEIGHT_1,885	mmDCORE0_MME_QM_ARB_WRR_WEIGHT_2,886	mmDCORE0_MME_QM_ARB_WRR_WEIGHT_3,887	mmDCORE0_MME_QM_ARB_BASE_LO,888	mmDCORE0_MME_QM_ARB_BASE_HI,889	mmDCORE0_MME_QM_ARB_MST_SLAVE_EN,890	mmDCORE0_MME_QM_ARB_MST_SLAVE_EN_1,891	mmDCORE0_MME_QM_ARB_MST_CRED_INC,892	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_0,893	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_1,894	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_2,895	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_3,896	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_4,897	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_5,898	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_6,899	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_7,900	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_8,901	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_9,902	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_10,903	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_11,904	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_12,905	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_13,906	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_14,907	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_15,908	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_16,909	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_17,910	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_18,911	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_19,912	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_20,913	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_21,914	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_22,915	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_23,916	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_24,917	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_25,918	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_26,919	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_27,920	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_28,921	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_29,922	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_30,923	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_31,924	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_32,925	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_33,926	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_34,927	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_35,928	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_36,929	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_37,930	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_38,931	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_39,932	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_40,933	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_41,934	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_42,935	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_43,936	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_44,937	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_45,938	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_46,939	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_47,940	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_48,941	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_49,942	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_50,943	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_51,944	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_52,945	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_53,946	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_54,947	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_55,948	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_56,949	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_57,950	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_58,951	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_59,952	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_60,953	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_61,954	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_62,955	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_63,956	mmDCORE0_MME_QM_ARB_SLV_ID,957	mmDCORE0_MME_QM_ARB_SLV_MASTER_INC_CRED_OFST,958	mmDCORE0_MME_QM_ARC_CQ_CFG0,959	mmDCORE0_MME_QM_CQ_IFIFO_CI_0,960	mmDCORE0_MME_QM_CQ_IFIFO_CI_1,961	mmDCORE0_MME_QM_CQ_IFIFO_CI_2,962	mmDCORE0_MME_QM_CQ_IFIFO_CI_3,963	mmDCORE0_MME_QM_CQ_IFIFO_CI_4,964	mmDCORE0_MME_QM_ARC_CQ_IFIFO_CI,965	mmDCORE0_MME_QM_CQ_CTL_CI_0,966	mmDCORE0_MME_QM_CQ_CTL_CI_1,967	mmDCORE0_MME_QM_CQ_CTL_CI_2,968	mmDCORE0_MME_QM_CQ_CTL_CI_3,969	mmDCORE0_MME_QM_CQ_CTL_CI_4,970	mmDCORE0_MME_QM_ARC_CQ_CTL_CI,971	mmDCORE0_MME_QM_ARC_CQ_TSIZE,972	mmDCORE0_MME_QM_ARC_CQ_CTL,973	mmDCORE0_MME_QM_CP_SWITCH_WD_SET,974	mmDCORE0_MME_QM_CP_EXT_SWITCH,975	mmDCORE0_MME_QM_CP_PRED_0,976	mmDCORE0_MME_QM_CP_PRED_1,977	mmDCORE0_MME_QM_CP_PRED_2,978	mmDCORE0_MME_QM_CP_PRED_3,979	mmDCORE0_MME_QM_CP_PRED_4,980	mmDCORE0_MME_QM_CP_PRED_UPEN_0,981	mmDCORE0_MME_QM_CP_PRED_UPEN_1,982	mmDCORE0_MME_QM_CP_PRED_UPEN_2,983	mmDCORE0_MME_QM_CP_PRED_UPEN_3,984	mmDCORE0_MME_QM_CP_PRED_UPEN_4,985	mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_LO_0,986	mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_LO_1,987	mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_LO_2,988	mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_LO_3,989	mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_LO_4,990	mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_HI_0,991	mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_HI_1,992	mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_HI_2,993	mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_HI_3,994	mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_HI_4,995	mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_LO_0,996	mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_LO_1,997	mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_LO_2,998	mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_LO_3,999	mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_LO_4,1000	mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_HI_0,1001	mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_HI_1,1002	mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_HI_2,1003	mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_HI_3,1004	mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_HI_4,1005	mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_LO_0,1006	mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_LO_1,1007	mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_LO_2,1008	mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_LO_3,1009	mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_LO_4,1010	mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_HI_0,1011	mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_HI_1,1012	mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_HI_2,1013	mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_HI_3,1014	mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_HI_4,1015	mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_LO_0,1016	mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_LO_1,1017	mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_LO_2,1018	mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_LO_3,1019	mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_LO_4,1020	mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_HI_0,1021	mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_HI_1,1022	mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_HI_2,1023	mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_HI_3,1024	mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_HI_4,1025	mmDCORE0_MME_QM_ARC_CQ_IFIFO_MSG_BASE_LO,1026	mmDCORE0_MME_QM_ARC_CQ_CTL_MSG_BASE_LO,1027	mmDCORE0_MME_QM_CQ_IFIFO_MSG_BASE_LO,1028	mmDCORE0_MME_QM_CQ_CTL_MSG_BASE_LO1029};1030 1031static const u32 gaudi2_pb_dcr0_mme_eng_unsecured_regs[] = {1032	mmDCORE0_MME_CTRL_LO_CMD,1033	mmDCORE0_MME_CTRL_LO_AGU,1034	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_ROI_BASE_OFFSET_0,1035	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_ROI_BASE_OFFSET_1,1036	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_ROI_BASE_OFFSET_2,1037	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_ROI_BASE_OFFSET_3,1038	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_ROI_BASE_OFFSET_4,1039	mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_ROI_BASE_OFFSET_0,1040	mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_ROI_BASE_OFFSET_1,1041	mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_ROI_BASE_OFFSET_2,1042	mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_ROI_BASE_OFFSET_3,1043	mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_ROI_BASE_OFFSET_4,1044	mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_START_BRAINS_LOW,1045	mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_START_BRAINS_HIGH,1046	mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_START_HEADER_LOW,1047	mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_START_HEADER_HIGH,1048	mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_START_EUS_MASTER,1049	mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_START_EUS_SLAVE,1050	mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_CONV_KERNEL_SIZE_MINUS_1,1051	mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_CONV_LOW,1052	mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_CONV_HIGH,1053	mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_OUTER_LOOP,1054	mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_NUM_ITERATIONS_MINUS_1,1055	mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SB_REPEAT,1056	mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_FP8_BIAS,1057	mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_RATE_LIMITER,1058	mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_USER_DATA,1059	mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_PERF_EVT_IN,1060	mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_PERF_EVT_OUT,1061	mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_PCU,1062	mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SLAVE_SYNC_OBJ0_ADDR,1063	mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SLAVE_SYNC_OBJ1_ADDR,1064	mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_POWER_LOOP,1065	mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SPARE0_MASTER,1066	mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SPARE1_MASTER,1067	mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SPARE2_MASTER,1068	mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SPARE3_MASTER,1069	mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SPARE0_SLAVE,1070	mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SPARE1_SLAVE,1071	mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SPARE2_SLAVE,1072	mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SPARE3_SLAVE,1073	mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_WKL_ID,1074	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_ROI_BASE_OFFSET_0,1075	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_ROI_BASE_OFFSET_1,1076	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_ROI_BASE_OFFSET_2,1077	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_ROI_BASE_OFFSET_3,1078	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_ROI_BASE_OFFSET_4,1079	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_ROI_BASE_OFFSET_0,1080	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_ROI_BASE_OFFSET_1,1081	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_ROI_BASE_OFFSET_2,1082	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_ROI_BASE_OFFSET_3,1083	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_ROI_BASE_OFFSET_4,1084	mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_ROI_BASE_OFFSET_0,1085	mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_ROI_BASE_OFFSET_1,1086	mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_ROI_BASE_OFFSET_2,1087	mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_ROI_BASE_OFFSET_3,1088	mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_ROI_BASE_OFFSET_4,1089	mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_ROI_BASE_OFFSET_0,1090	mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_ROI_BASE_OFFSET_1,1091	mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_ROI_BASE_OFFSET_2,1092	mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_ROI_BASE_OFFSET_3,1093	mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_ROI_BASE_OFFSET_4,1094	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_ROI_BASE_OFFSET_0,1095	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_ROI_BASE_OFFSET_1,1096	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_ROI_BASE_OFFSET_2,1097	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_ROI_BASE_OFFSET_3,1098	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_ROI_BASE_OFFSET_4,1099	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_ROI_BASE_OFFSET_0,1100	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_ROI_BASE_OFFSET_1,1101	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_ROI_BASE_OFFSET_2,1102	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_ROI_BASE_OFFSET_3,1103	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_ROI_BASE_OFFSET_4,1104	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_VALID_ELEMENTS_0,1105	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_VALID_ELEMENTS_1,1106	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_VALID_ELEMENTS_2,1107	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_VALID_ELEMENTS_3,1108	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_VALID_ELEMENTS_4,1109	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_LOOP_STRIDE_0,1110	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_LOOP_STRIDE_1,1111	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_LOOP_STRIDE_2,1112	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_LOOP_STRIDE_3,1113	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_LOOP_STRIDE_4,1114	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_ROI_SIZE_0,1115	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_ROI_SIZE_1,1116	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_ROI_SIZE_2,1117	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_ROI_SIZE_3,1118	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_SPATIAL_STRIDES_0,1119	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_SPATIAL_STRIDES_1,1120	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_SPATIAL_STRIDES_2,1121	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_SPATIAL_STRIDES_3,1122	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_START_OFFSET_0,1123	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_START_OFFSET_1,1124	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_START_OFFSET_2,1125	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_START_OFFSET_3,1126	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_ROI_BASE_OFFSET_0,1127	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_ROI_BASE_OFFSET_1,1128	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_ROI_BASE_OFFSET_2,1129	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_ROI_BASE_OFFSET_3,1130	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_ROI_BASE_OFFSET_4,1131	mmDCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_COUT1_LOW,1132	mmDCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_COUT1_HIGH,1133	mmDCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_COUT0_LOW,1134	mmDCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_COUT0_HIGH,1135	mmDCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_A_LOW,1136	mmDCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_A_HIGH,1137	mmDCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_B_LOW,1138	mmDCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_B_HIGH,1139	mmDCORE0_MME_CTRL_LO_ARCH_STATUS,1140	mmDCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0,1141	mmDCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_ADDR0,1142	mmDCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL0,1143	mmDCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_ADDR1,1144	mmDCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL1,1145	mmDCORE0_MME_CTRL_LO_ARCH_A_SS,1146	mmDCORE0_MME_CTRL_LO_ARCH_B_SS,1147	mmDCORE0_MME_CTRL_LO_ARCH_COUT_SS,1148	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_ROI_BASE_OFFSET_0,1149	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_ROI_BASE_OFFSET_1,1150	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_ROI_BASE_OFFSET_2,1151	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_ROI_BASE_OFFSET_3,1152	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_ROI_BASE_OFFSET_4,1153	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_ROI_BASE_OFFSET_0,1154	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_ROI_BASE_OFFSET_1,1155	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_ROI_BASE_OFFSET_2,1156	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_ROI_BASE_OFFSET_3,1157	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_ROI_BASE_OFFSET_4,1158	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_VALID_ELEMENTS_0,1159	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_VALID_ELEMENTS_1,1160	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_VALID_ELEMENTS_2,1161	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_VALID_ELEMENTS_3,1162	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_VALID_ELEMENTS_4,1163	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_LOOP_STRIDE_0,1164	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_LOOP_STRIDE_1,1165	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_LOOP_STRIDE_2,1166	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_LOOP_STRIDE_3,1167	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_LOOP_STRIDE_4,1168	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_ROI_SIZE_0,1169	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_ROI_SIZE_1,1170	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_ROI_SIZE_2,1171	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_ROI_SIZE_3,1172	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_SPATIAL_STRIDES_0,1173	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_SPATIAL_STRIDES_1,1174	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_SPATIAL_STRIDES_2,1175	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_SPATIAL_STRIDES_3,1176	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_START_OFFSET_0,1177	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_START_OFFSET_1,1178	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_START_OFFSET_2,1179	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_START_OFFSET_3,1180	mmDCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_BASE,1181	mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_START_BASE,1182	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_BASE,1183	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_BASE,1184	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_BASE,1185	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_BASE,1186	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_BASE,1187	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_BASE,1188	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_BASE,1189	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_BASE,1190	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_BASE,1191	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_BASE,1192	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_BASE,1193	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_BASE,1194	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_BASE,1195	mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_BASE,1196	mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_BASE,1197	mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_BASE,1198	mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_BASE,1199	mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_BASE,1200	mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_ROI_BASE_OFFSET_0,1201	mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_ROI_BASE_OFFSET_1,1202	mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_ROI_BASE_OFFSET_2,1203	mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_ROI_BASE_OFFSET_3,1204	mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_ROI_BASE_OFFSET_4,1205	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_ROI_BASE_OFFSET_0,1206	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_ROI_BASE_OFFSET_1,1207	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_ROI_BASE_OFFSET_2,1208	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_ROI_BASE_OFFSET_3,1209	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_ROI_BASE_OFFSET_4,1210	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_VALID_ELEMENTS_0,1211	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_VALID_ELEMENTS_1,1212	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_VALID_ELEMENTS_2,1213	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_VALID_ELEMENTS_3,1214	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_VALID_ELEMENTS_4,1215	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_LOOP_STRIDE_0,1216	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_LOOP_STRIDE_1,1217	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_LOOP_STRIDE_2,1218	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_LOOP_STRIDE_3,1219	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_LOOP_STRIDE_4,1220	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_ROI_SIZE_0,1221	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_ROI_SIZE_1,1222	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_ROI_SIZE_2,1223	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_ROI_SIZE_3,1224	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_SPATIAL_STRIDES_0,1225	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_SPATIAL_STRIDES_1,1226	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_SPATIAL_STRIDES_2,1227	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_SPATIAL_STRIDES_3,1228	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_START_OFFSET_0,1229	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_START_OFFSET_1,1230	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_START_OFFSET_2,1231	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_START_OFFSET_3,1232	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_ROI_BASE_OFFSET_0,1233	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_ROI_BASE_OFFSET_1,1234	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_ROI_BASE_OFFSET_2,1235	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_ROI_BASE_OFFSET_3,1236	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_ROI_BASE_OFFSET_4,1237	mmDCORE0_MME_ACC_AP_LFSR_POLY,1238	mmDCORE0_MME_ACC_AP_LFSR_SEED_WDATA,1239	mmDCORE0_MME_ACC_AP_LFSR_SEED_SEL,1240	mmDCORE0_MME_ACC_AP_LFSR_SEED_RDATA,1241	mmDCORE0_MME_ACC_AP_LFSR_CLOSE_CGATE_DLY,1242	mmDCORE0_MME_ACC_WBC_SRC_BP,1243};1244 1245static const u32 gaudi2_pb_dcr0_tpc0[] = {1246	mmDCORE0_TPC0_QM_BASE,1247	mmDCORE0_TPC0_CFG_BASE,1248	mmDCORE0_TPC0_MSTR_IF_RR_SHRD_HBW_BASE,1249};1250 1251static const u32 gaudi2_pb_dcr0_tpc0_arc[] = {1252	mmDCORE0_TPC0_QM_ARC_AUX_BASE,1253};1254 1255static const struct range gaudi2_pb_dcr0_tpc0_arc_unsecured_regs[] = {1256	{mmDCORE0_TPC0_QM_ARC_AUX_RUN_HALT_REQ, mmDCORE0_TPC0_QM_ARC_AUX_RUN_HALT_ACK},1257	{mmDCORE0_TPC0_QM_ARC_AUX_CLUSTER_NUM, mmDCORE0_TPC0_QM_ARC_AUX_WAKE_UP_EVENT},1258	{mmDCORE0_TPC0_QM_ARC_AUX_ARC_RST_REQ, mmDCORE0_TPC0_QM_ARC_AUX_CID_OFFSET_7},1259	{mmDCORE0_TPC0_QM_ARC_AUX_SCRATCHPAD_0, mmDCORE0_TPC0_QM_ARC_AUX_INFLIGHT_LBU_RD_CNT},1260	{mmDCORE0_TPC0_QM_ARC_AUX_CBU_EARLY_BRESP_EN, mmDCORE0_TPC0_QM_ARC_AUX_CBU_EARLY_BRESP_EN},1261	{mmDCORE0_TPC0_QM_ARC_AUX_LBU_EARLY_BRESP_EN, mmDCORE0_TPC0_QM_ARC_AUX_LBU_EARLY_BRESP_EN},1262	{mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_0,1263		mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_ALERT_MSG},1264	{mmDCORE0_TPC0_QM_ARC_AUX_DCCM_Q_PUSH_FIFO_CNT,1265		mmDCORE0_TPC0_QM_ARC_AUX_QMAN_ARC_CQ_SHADOW_CI},1266	{mmDCORE0_TPC0_QM_ARC_AUX_ARC_AXI_ORDERING_WR_IF_CNT,1267		mmDCORE0_TPC0_QM_ARC_AUX_MME_ARC_UPPER_DCCM_EN},1268};1269 1270static const u32 gaudi2_pb_dcr0_tpc0_unsecured_regs[] = {1271	mmDCORE0_TPC0_QM_CQ_CFG0_0,1272	mmDCORE0_TPC0_QM_CQ_CFG0_1,1273	mmDCORE0_TPC0_QM_CQ_CFG0_2,1274	mmDCORE0_TPC0_QM_CQ_CFG0_3,1275	mmDCORE0_TPC0_QM_CQ_CFG0_4,1276	mmDCORE0_TPC0_QM_CP_FENCE0_RDATA_0,1277	mmDCORE0_TPC0_QM_CP_FENCE0_RDATA_1,1278	mmDCORE0_TPC0_QM_CP_FENCE0_RDATA_2,1279	mmDCORE0_TPC0_QM_CP_FENCE0_RDATA_3,1280	mmDCORE0_TPC0_QM_CP_FENCE0_RDATA_4,1281	mmDCORE0_TPC0_QM_CP_FENCE1_RDATA_0,1282	mmDCORE0_TPC0_QM_CP_FENCE1_RDATA_1,1283	mmDCORE0_TPC0_QM_CP_FENCE1_RDATA_2,1284	mmDCORE0_TPC0_QM_CP_FENCE1_RDATA_3,1285	mmDCORE0_TPC0_QM_CP_FENCE1_RDATA_4,1286	mmDCORE0_TPC0_QM_CP_FENCE2_RDATA_0,1287	mmDCORE0_TPC0_QM_CP_FENCE2_RDATA_1,1288	mmDCORE0_TPC0_QM_CP_FENCE2_RDATA_2,1289	mmDCORE0_TPC0_QM_CP_FENCE2_RDATA_3,1290	mmDCORE0_TPC0_QM_CP_FENCE2_RDATA_4,1291	mmDCORE0_TPC0_QM_CP_FENCE3_RDATA_0,1292	mmDCORE0_TPC0_QM_CP_FENCE3_RDATA_1,1293	mmDCORE0_TPC0_QM_CP_FENCE3_RDATA_2,1294	mmDCORE0_TPC0_QM_CP_FENCE3_RDATA_3,1295	mmDCORE0_TPC0_QM_CP_FENCE3_RDATA_4,1296	mmDCORE0_TPC0_QM_CP_FENCE0_CNT_0,1297	mmDCORE0_TPC0_QM_CP_FENCE0_CNT_1,1298	mmDCORE0_TPC0_QM_CP_FENCE0_CNT_2,1299	mmDCORE0_TPC0_QM_CP_FENCE0_CNT_3,1300	mmDCORE0_TPC0_QM_CP_FENCE0_CNT_4,1301	mmDCORE0_TPC0_QM_CP_FENCE1_CNT_0,1302	mmDCORE0_TPC0_QM_CP_FENCE1_CNT_1,1303	mmDCORE0_TPC0_QM_CP_FENCE1_CNT_2,1304	mmDCORE0_TPC0_QM_CP_FENCE1_CNT_3,1305	mmDCORE0_TPC0_QM_CP_FENCE1_CNT_4,1306	mmDCORE0_TPC0_QM_CP_FENCE2_CNT_0,1307	mmDCORE0_TPC0_QM_CP_FENCE2_CNT_1,1308	mmDCORE0_TPC0_QM_CP_FENCE2_CNT_2,1309	mmDCORE0_TPC0_QM_CP_FENCE2_CNT_3,1310	mmDCORE0_TPC0_QM_CP_FENCE2_CNT_4,1311	mmDCORE0_TPC0_QM_CP_FENCE3_CNT_0,1312	mmDCORE0_TPC0_QM_CP_FENCE3_CNT_1,1313	mmDCORE0_TPC0_QM_CP_FENCE3_CNT_2,1314	mmDCORE0_TPC0_QM_CP_FENCE3_CNT_3,1315	mmDCORE0_TPC0_QM_CP_FENCE3_CNT_4,1316	mmDCORE0_TPC0_QM_CQ_PTR_LO_0,1317	mmDCORE0_TPC0_QM_CQ_PTR_HI_0,1318	mmDCORE0_TPC0_QM_CQ_TSIZE_0,1319	mmDCORE0_TPC0_QM_CQ_CTL_0,1320	mmDCORE0_TPC0_QM_CQ_PTR_LO_1,1321	mmDCORE0_TPC0_QM_CQ_PTR_HI_1,1322	mmDCORE0_TPC0_QM_CQ_TSIZE_1,1323	mmDCORE0_TPC0_QM_CQ_CTL_1,1324	mmDCORE0_TPC0_QM_CQ_PTR_LO_2,1325	mmDCORE0_TPC0_QM_CQ_PTR_HI_2,1326	mmDCORE0_TPC0_QM_CQ_TSIZE_2,1327	mmDCORE0_TPC0_QM_CQ_CTL_2,1328	mmDCORE0_TPC0_QM_CQ_PTR_LO_3,1329	mmDCORE0_TPC0_QM_CQ_PTR_HI_3,1330	mmDCORE0_TPC0_QM_CQ_TSIZE_3,1331	mmDCORE0_TPC0_QM_CQ_CTL_3,1332	mmDCORE0_TPC0_QM_CQ_PTR_LO_4,1333	mmDCORE0_TPC0_QM_CQ_PTR_HI_4,1334	mmDCORE0_TPC0_QM_CQ_TSIZE_4,1335	mmDCORE0_TPC0_QM_CQ_CTL_4,1336	mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR0_BASE,1337	mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR0_BASE + 4,1338	mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR1_BASE,1339	mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR1_BASE + 4,1340	mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR2_BASE,1341	mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR2_BASE + 4,1342	mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR3_BASE,1343	mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR3_BASE + 4,1344	mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR4_BASE,1345	mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR4_BASE + 4,1346	mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR5_BASE,1347	mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR5_BASE + 4,1348	mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR6_BASE,1349	mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR6_BASE + 4,1350	mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR7_BASE,1351	mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR7_BASE + 4,1352	mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR8_BASE,1353	mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR8_BASE + 4,1354	mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR9_BASE,1355	mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR9_BASE + 4,1356	mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR10_BASE,1357	mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR10_BASE + 4,1358	mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR11_BASE,1359	mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR11_BASE + 4,1360	mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR12_BASE,1361	mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR12_BASE + 4,1362	mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR13_BASE,1363	mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR13_BASE + 4,1364	mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR14_BASE,1365	mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR14_BASE + 4,1366	mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR15_BASE,1367	mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR15_BASE + 4,1368	mmDCORE0_TPC0_QM_ARC_CQ_PTR_LO,1369	mmDCORE0_TPC0_QM_ARC_CQ_PTR_LO_STS,1370	mmDCORE0_TPC0_QM_ARC_CQ_PTR_HI,1371	mmDCORE0_TPC0_QM_ARC_CQ_PTR_HI_STS,1372	mmDCORE0_TPC0_QM_ARB_CFG_0,1373	mmDCORE0_TPC0_QM_ARB_MST_QUIET_PER,1374	mmDCORE0_TPC0_QM_ARB_CHOICE_Q_PUSH,1375	mmDCORE0_TPC0_QM_ARB_WRR_WEIGHT_0,1376	mmDCORE0_TPC0_QM_ARB_WRR_WEIGHT_1,1377	mmDCORE0_TPC0_QM_ARB_WRR_WEIGHT_2,1378	mmDCORE0_TPC0_QM_ARB_WRR_WEIGHT_3,1379	mmDCORE0_TPC0_QM_ARB_BASE_LO,1380	mmDCORE0_TPC0_QM_ARB_BASE_HI,1381	mmDCORE0_TPC0_QM_ARB_MST_SLAVE_EN,1382	mmDCORE0_TPC0_QM_ARB_MST_SLAVE_EN_1,1383	mmDCORE0_TPC0_QM_ARB_MST_CRED_INC,1384	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_0,1385	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_1,1386	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_2,1387	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_3,1388	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_4,1389	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_5,1390	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_6,1391	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_7,1392	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_8,1393	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_9,1394	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_10,1395	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_11,1396	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_12,1397	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_13,1398	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_14,1399	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_15,1400	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_16,1401	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_17,1402	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_18,1403	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_19,1404	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_20,1405	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_21,1406	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_22,1407	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_23,1408	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_24,1409	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_25,1410	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_26,1411	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_27,1412	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_28,1413	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_29,1414	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_30,1415	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_31,1416	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_32,1417	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_33,1418	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_34,1419	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_35,1420	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_36,1421	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_37,1422	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_38,1423	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_39,1424	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_40,1425	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_41,1426	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_42,1427	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_43,1428	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_44,1429	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_45,1430	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_46,1431	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_47,1432	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_48,1433	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_49,1434	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_50,1435	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_51,1436	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_52,1437	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_53,1438	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_54,1439	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_55,1440	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_56,1441	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_57,1442	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_58,1443	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_59,1444	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_60,1445	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_61,1446	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_62,1447	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_63,1448	mmDCORE0_TPC0_QM_ARB_SLV_ID,1449	mmDCORE0_TPC0_QM_ARB_SLV_MASTER_INC_CRED_OFST,1450	mmDCORE0_TPC0_QM_ARC_CQ_CFG0,1451	mmDCORE0_TPC0_QM_CQ_IFIFO_CI_0,1452	mmDCORE0_TPC0_QM_CQ_IFIFO_CI_1,1453	mmDCORE0_TPC0_QM_CQ_IFIFO_CI_2,1454	mmDCORE0_TPC0_QM_CQ_IFIFO_CI_3,1455	mmDCORE0_TPC0_QM_CQ_IFIFO_CI_4,1456	mmDCORE0_TPC0_QM_ARC_CQ_IFIFO_CI,1457	mmDCORE0_TPC0_QM_CQ_CTL_CI_0,1458	mmDCORE0_TPC0_QM_CQ_CTL_CI_1,1459	mmDCORE0_TPC0_QM_CQ_CTL_CI_2,1460	mmDCORE0_TPC0_QM_CQ_CTL_CI_3,1461	mmDCORE0_TPC0_QM_CQ_CTL_CI_4,1462	mmDCORE0_TPC0_QM_ARC_CQ_CTL_CI,1463	mmDCORE0_TPC0_QM_ARC_CQ_TSIZE,1464	mmDCORE0_TPC0_QM_ARC_CQ_CTL,1465	mmDCORE0_TPC0_QM_CP_SWITCH_WD_SET,1466	mmDCORE0_TPC0_QM_CP_EXT_SWITCH,1467	mmDCORE0_TPC0_QM_CP_PRED_0,1468	mmDCORE0_TPC0_QM_CP_PRED_1,1469	mmDCORE0_TPC0_QM_CP_PRED_2,1470	mmDCORE0_TPC0_QM_CP_PRED_3,1471	mmDCORE0_TPC0_QM_CP_PRED_4,1472	mmDCORE0_TPC0_QM_CP_PRED_UPEN_0,1473	mmDCORE0_TPC0_QM_CP_PRED_UPEN_1,1474	mmDCORE0_TPC0_QM_CP_PRED_UPEN_2,1475	mmDCORE0_TPC0_QM_CP_PRED_UPEN_3,1476	mmDCORE0_TPC0_QM_CP_PRED_UPEN_4,1477	mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_LO_0,1478	mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_LO_1,1479	mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_LO_2,1480	mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_LO_3,1481	mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_LO_4,1482	mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_HI_0,1483	mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_HI_1,1484	mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_HI_2,1485	mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_HI_3,1486	mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_HI_4,1487	mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_LO_0,1488	mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_LO_1,1489	mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_LO_2,1490	mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_LO_3,1491	mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_LO_4,1492	mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_HI_0,1493	mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_HI_1,1494	mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_HI_2,1495	mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_HI_3,1496	mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_HI_4,1497	mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_LO_0,1498	mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_LO_1,1499	mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_LO_2,1500	mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_LO_3,1501	mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_LO_4,1502	mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_HI_0,1503	mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_HI_1,1504	mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_HI_2,1505	mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_HI_3,1506	mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_HI_4,1507	mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_LO_0,1508	mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_LO_1,1509	mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_LO_2,1510	mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_LO_3,1511	mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_LO_4,1512	mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_HI_0,1513	mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_HI_1,1514	mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_HI_2,1515	mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_HI_3,1516	mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_HI_4,1517	mmDCORE0_TPC0_QM_ARC_CQ_IFIFO_MSG_BASE_LO,1518	mmDCORE0_TPC0_QM_ARC_CQ_CTL_MSG_BASE_LO,1519	mmDCORE0_TPC0_QM_CQ_IFIFO_MSG_BASE_LO,1520	mmDCORE0_TPC0_QM_CQ_CTL_MSG_BASE_LO,1521	mmDCORE0_TPC0_CFG_QM_SYNC_OBJECT_MESSAGE,1522	mmDCORE0_TPC0_CFG_QM_SYNC_OBJECT_ADDR,1523	mmDCORE0_TPC0_CFG_QM_KERNEL_BASE_ADDRESS_LOW,1524	mmDCORE0_TPC0_CFG_QM_KERNEL_BASE_ADDRESS_HIGH,1525	mmDCORE0_TPC0_CFG_QM_TID_BASE_DIM_0,1526	mmDCORE0_TPC0_CFG_QM_TID_SIZE_DIM_0,1527	mmDCORE0_TPC0_CFG_QM_TID_BASE_DIM_1,1528	mmDCORE0_TPC0_CFG_QM_TID_SIZE_DIM_1,1529	mmDCORE0_TPC0_CFG_QM_TID_BASE_DIM_2,1530	mmDCORE0_TPC0_CFG_QM_TID_SIZE_DIM_2,1531	mmDCORE0_TPC0_CFG_QM_TID_BASE_DIM_3,1532	mmDCORE0_TPC0_CFG_QM_TID_SIZE_DIM_3,1533	mmDCORE0_TPC0_CFG_QM_TID_BASE_DIM_4,1534	mmDCORE0_TPC0_CFG_QM_TID_SIZE_DIM_4,1535	mmDCORE0_TPC0_CFG_QM_KERNEL_CONFIG,1536	mmDCORE0_TPC0_CFG_QM_KERNEL_ID,1537	mmDCORE0_TPC0_CFG_QM_POWER_LOOP,1538	mmDCORE0_TPC0_CFG_TSB_CFG_MTRR_2_0,1539	mmDCORE0_TPC0_CFG_TSB_CFG_MTRR_2_1,1540	mmDCORE0_TPC0_CFG_TSB_CFG_MTRR_2_2,1541	mmDCORE0_TPC0_CFG_TSB_CFG_MTRR_2_3,1542	mmDCORE0_TPC0_CFG_LUT_FUNC32_BASE2_ADDR_LO,1543	mmDCORE0_TPC0_CFG_LUT_FUNC32_BASE2_ADDR_HI,1544	mmDCORE0_TPC0_CFG_LUT_FUNC64_BASE2_ADDR_LO,1545	mmDCORE0_TPC0_CFG_LUT_FUNC64_BASE2_ADDR_HI,1546	mmDCORE0_TPC0_CFG_LUT_FUNC128_BASE2_ADDR_LO,1547	mmDCORE0_TPC0_CFG_LUT_FUNC128_BASE2_ADDR_HI,1548	mmDCORE0_TPC0_CFG_LUT_FUNC256_BASE2_ADDR_LO,1549	mmDCORE0_TPC0_CFG_LUT_FUNC256_BASE2_ADDR_HI,1550	mmDCORE0_TPC0_CFG_FP8_143_BIAS,1551	mmDCORE0_TPC0_CFG_ROUND_CSR,1552	mmDCORE0_TPC0_CFG_CONV_ROUND_CSR,1553	mmDCORE0_TPC0_CFG_SEMAPHORE,1554	mmDCORE0_TPC0_CFG_LFSR_POLYNOM,1555	mmDCORE0_TPC0_CFG_STATUS,1556	mmDCORE0_TPC0_CFG_TPC_CMD,1557	mmDCORE0_TPC0_CFG_TPC_EXECUTE,1558	mmDCORE0_TPC0_CFG_TPC_DCACHE_L0CD,1559	mmDCORE0_TPC0_CFG_ICACHE_BASE_ADDERESS_LOW,1560	mmDCORE0_TPC0_CFG_ICACHE_BASE_ADDERESS_HIGH,1561	mmDCORE0_TPC0_CFG_RD_RATE_LIMIT,1562	mmDCORE0_TPC0_CFG_WR_RATE_LIMIT,1563	mmDCORE0_TPC0_CFG_LUT_FUNC32_BASE_ADDR_LO,1564	mmDCORE0_TPC0_CFG_LUT_FUNC32_BASE_ADDR_HI,1565	mmDCORE0_TPC0_CFG_LUT_FUNC64_BASE_ADDR_LO,1566	mmDCORE0_TPC0_CFG_LUT_FUNC64_BASE_ADDR_HI,1567	mmDCORE0_TPC0_CFG_LUT_FUNC128_BASE_ADDR_LO,1568	mmDCORE0_TPC0_CFG_LUT_FUNC128_BASE_ADDR_HI,1569	mmDCORE0_TPC0_CFG_LUT_FUNC256_BASE_ADDR_LO,1570	mmDCORE0_TPC0_CFG_LUT_FUNC256_BASE_ADDR_HI,1571	mmDCORE0_TPC0_CFG_KERNEL_KERNEL_CONFIG,1572	mmDCORE0_TPC0_CFG_KERNEL_SRF_0,1573	mmDCORE0_TPC0_CFG_KERNEL_SRF_1,1574	mmDCORE0_TPC0_CFG_KERNEL_SRF_2,1575	mmDCORE0_TPC0_CFG_KERNEL_SRF_3,1576	mmDCORE0_TPC0_CFG_KERNEL_SRF_4,1577	mmDCORE0_TPC0_CFG_KERNEL_SRF_5,1578	mmDCORE0_TPC0_CFG_KERNEL_SRF_6,1579	mmDCORE0_TPC0_CFG_KERNEL_SRF_7,1580	mmDCORE0_TPC0_CFG_KERNEL_SRF_8,1581	mmDCORE0_TPC0_CFG_KERNEL_SRF_9,1582	mmDCORE0_TPC0_CFG_KERNEL_SRF_10,1583	mmDCORE0_TPC0_CFG_KERNEL_SRF_11,1584	mmDCORE0_TPC0_CFG_KERNEL_SRF_12,1585	mmDCORE0_TPC0_CFG_KERNEL_SRF_13,1586	mmDCORE0_TPC0_CFG_KERNEL_SRF_14,1587	mmDCORE0_TPC0_CFG_KERNEL_SRF_15,1588	mmDCORE0_TPC0_CFG_KERNEL_SRF_16,1589	mmDCORE0_TPC0_CFG_KERNEL_SRF_17,1590	mmDCORE0_TPC0_CFG_KERNEL_SRF_18,1591	mmDCORE0_TPC0_CFG_KERNEL_SRF_19,1592	mmDCORE0_TPC0_CFG_KERNEL_SRF_20,1593	mmDCORE0_TPC0_CFG_KERNEL_SRF_21,1594	mmDCORE0_TPC0_CFG_KERNEL_SRF_22,1595	mmDCORE0_TPC0_CFG_KERNEL_SRF_23,1596	mmDCORE0_TPC0_CFG_KERNEL_SRF_24,1597	mmDCORE0_TPC0_CFG_KERNEL_SRF_25,1598	mmDCORE0_TPC0_CFG_KERNEL_SRF_26,1599	mmDCORE0_TPC0_CFG_KERNEL_SRF_27,1600	mmDCORE0_TPC0_CFG_KERNEL_SRF_28,1601	mmDCORE0_TPC0_CFG_KERNEL_SRF_29,1602	mmDCORE0_TPC0_CFG_KERNEL_SRF_30,1603	mmDCORE0_TPC0_CFG_KERNEL_SRF_31,1604	mmDCORE0_TPC0_CFG_TPC_SB_L0CD,1605	mmDCORE0_TPC0_CFG_TPC_COUNT,1606	mmDCORE0_TPC0_CFG_TPC_ID,1607	mmDCORE0_TPC0_CFG_QM_KERNEL_ID_INC,1608	mmDCORE0_TPC0_CFG_QM_TID_BASE_SIZE_HIGH_DIM_0,1609	mmDCORE0_TPC0_CFG_QM_TID_BASE_SIZE_HIGH_DIM_1,1610	mmDCORE0_TPC0_CFG_QM_TID_BASE_SIZE_HIGH_DIM_2,1611	mmDCORE0_TPC0_CFG_QM_TID_BASE_SIZE_HIGH_DIM_3,1612	mmDCORE0_TPC0_CFG_QM_TID_BASE_SIZE_HIGH_DIM_4,1613	mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SPARE_0,1614	mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SPARE_1,1615	mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SPARE_2,1616	mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SPARE_31617};1618 1619static const u32 gaudi2_pb_dcr0_tpc0_ktensor_unsecured_regs[] = {1620	mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW,1621	mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH,1622	mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_PADDING_VALUE,1623	mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG,1624	mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_0_SIZE,1625	mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE,1626	mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_1_SIZE,1627	mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE,1628	mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_2_SIZE,1629	mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE,1630	mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_3_SIZE,1631	mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE,1632	mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_4_SIZE,1633	mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE,1634	mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_PREF_STRIDE,1635	mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_0_SIZE_STRIDE_HIGH,1636	mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_1_SIZE_STRIDE_HIGH,1637	mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_2_SIZE_STRIDE_HIGH,1638	mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_3_SIZE_STRIDE_HIGH,1639	mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_4_SIZE_STRIDE_HIGH,1640};1641 1642static const u32 gaudi2_pb_dcr0_tpc0_qtensor_unsecured_regs[] = {1643	mmDCORE0_TPC0_CFG_QM_TENSOR_0_BASE_ADDR_LOW,1644	mmDCORE0_TPC0_CFG_QM_TENSOR_0_BASE_ADDR_HIGH,1645	mmDCORE0_TPC0_CFG_QM_TENSOR_0_PADDING_VALUE,1646	mmDCORE0_TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG,1647	mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_0_SIZE,1648	mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_0_STRIDE,1649	mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_1_SIZE,1650	mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_1_STRIDE,1651	mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_2_SIZE,1652	mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_2_STRIDE,1653	mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_3_SIZE,1654	mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_3_STRIDE,1655	mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_4_SIZE,1656	mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_4_STRIDE,1657	mmDCORE0_TPC0_CFG_QM_TENSOR_0_PREF_STRIDE,1658	mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_0_SIZE_STRIDE_HIGH,1659	mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_1_SIZE_STRIDE_HIGH,1660	mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_2_SIZE_STRIDE_HIGH,1661	mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_3_SIZE_STRIDE_HIGH,1662	mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_4_SIZE_STRIDE_HIGH,1663};1664 1665static const u32 gaudi2_pb_dcr0_sram0[] = {1666	mmDCORE0_SRAM0_BANK_BASE,1667	mmDCORE0_SRAM0_DBG_CNT_N_HBW_DBG_CNT_BASE,1668	mmDCORE0_SRAM0_RTR_BASE,1669};1670 1671static const u32 gaudi2_pb_dcr0_sm_mstr_if[] = {1672	mmDCORE0_SYNC_MNGR_MSTR_IF_RR_SHRD_HBW_BASE,1673};1674 1675static const u32 gaudi2_pb_dcr0_sm_glbl[] = {1676	mmDCORE0_SYNC_MNGR_GLBL_BASE,1677};1678 1679static const u32 gaudi2_pb_dcr1_sm_glbl[] = {1680	mmDCORE1_SYNC_MNGR_GLBL_BASE,1681};1682 1683static const struct range gaudi2_pb_dcr0_sm_glbl_unsecured_regs[] = {1684	{mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_1, mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_63},1685	{mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_1, mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_63},1686	{mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_1, mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_63},1687	{mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_1, mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_63},1688	{mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_1, mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_63},1689	{mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_1, mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_63},1690	{mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_1, mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_63},1691	{mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_1, mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_63},1692};1693 1694static const struct range gaudi2_pb_dcr_x_sm_glbl_unsecured_regs[] = {1695	{mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_0, mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_63},1696	{mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_0, mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_63},1697	{mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_0, mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_63},1698	{mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_0, mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_63},1699	{mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_0, mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_63},1700	{mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_0, mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_63},1701	{mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_0, mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_63},1702	{mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_0, mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_63},1703};1704 1705static const u32 gaudi2_pb_arc_sched[] = {1706	mmARC_FARM_ARC0_AUX_BASE,1707	mmARC_FARM_ARC0_DUP_ENG_BASE,1708	mmARC_FARM_ARC0_ACP_ENG_BASE,1709};1710 1711static const struct range gaudi2_pb_arc_sched_unsecured_regs[] = {1712	{mmARC_FARM_ARC0_AUX_RUN_HALT_REQ, mmARC_FARM_ARC0_AUX_RUN_HALT_ACK},1713	{mmARC_FARM_ARC0_AUX_CLUSTER_NUM, mmARC_FARM_ARC0_AUX_WAKE_UP_EVENT},1714	{mmARC_FARM_ARC0_AUX_ARC_RST_REQ, mmARC_FARM_ARC0_AUX_CID_OFFSET_7},1715	{mmARC_FARM_ARC0_AUX_SCRATCHPAD_0, mmARC_FARM_ARC0_AUX_INFLIGHT_LBU_RD_CNT},1716	{mmARC_FARM_ARC0_AUX_CBU_EARLY_BRESP_EN, mmARC_FARM_ARC0_AUX_CBU_EARLY_BRESP_EN},1717	{mmARC_FARM_ARC0_AUX_LBU_EARLY_BRESP_EN, mmARC_FARM_ARC0_AUX_LBU_EARLY_BRESP_EN},1718	{mmARC_FARM_ARC0_AUX_DCCM_QUEUE_BASE_ADDR_0, mmARC_FARM_ARC0_AUX_DCCM_QUEUE_ALERT_MSG},1719	{mmARC_FARM_ARC0_AUX_DCCM_Q_PUSH_FIFO_CNT, mmARC_FARM_ARC0_AUX_QMAN_ARC_CQ_SHADOW_CI},1720	{mmARC_FARM_ARC0_AUX_ARC_AXI_ORDERING_WR_IF_CNT, mmARC_FARM_ARC0_AUX_MME_ARC_UPPER_DCCM_EN},1721	{mmARC_FARM_ARC0_DUP_ENG_DUP_TPC_ENG_ADDR_0, mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_63},1722	{mmARC_FARM_ARC0_DUP_ENG_AXUSER_HB_STRONG_ORDER, mmARC_FARM_ARC0_DUP_ENG_AXUSER_LB_OVRD},1723	{mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_0, mmARC_FARM_ARC0_ACP_ENG_ACP_DBG_REG},1724};1725 1726static const u32 gaudi2_pb_xbar_mid[] = {1727	mmXBAR_MID_0_BASE,1728};1729 1730static const u32 gaudi2_pb_xbar_mid_unsecured_regs[] = {1731	mmXBAR_MID_0_UPSCALE,1732	mmXBAR_MID_0_DOWN_CONV,1733	mmXBAR_MID_0_DOWN_CONV_LFSR_EN,1734	mmXBAR_MID_0_DOWN_CONV_LFSR_SET_VLD,1735	mmXBAR_MID_0_DOWN_CONV_LFSR_SET_VALUE,1736	mmXBAR_MID_0_DOWN_CONV_LFSR_CFG_POLY,1737};1738 1739static const u32 gaudi2_pb_xbar_edge[] = {1740	mmXBAR_EDGE_0_BASE,1741};1742 1743static const u32 gaudi2_pb_xbar_edge_unsecured_regs[] = {1744	mmXBAR_EDGE_0_UPSCALE,1745	mmXBAR_EDGE_0_DOWN_CONV,1746	mmXBAR_EDGE_0_DOWN_CONV_LFSR_EN,1747	mmXBAR_EDGE_0_DOWN_CONV_LFSR_SET_VLD,1748	mmXBAR_EDGE_0_DOWN_CONV_LFSR_SET_VALUE,1749	mmXBAR_EDGE_0_DOWN_CONV_LFSR_CFG_POLY,1750};1751 1752static const u32 gaudi2_pb_nic0[] = {1753	mmNIC0_TMR_BASE,1754	mmNIC0_RXB_CORE_BASE,1755	mmNIC0_RXE0_BASE,1756	mmNIC0_RXE1_BASE,1757	mmNIC0_RXE0_AXUSER_AXUSER_CQ0_BASE,1758	mmNIC0_RXE1_AXUSER_AXUSER_CQ0_BASE,1759	mmNIC0_TXS0_BASE,1760	mmNIC0_TXS1_BASE,1761	mmNIC0_TXE0_BASE,1762	mmNIC0_TXE1_BASE,1763	mmNIC0_TXB_BASE,1764	mmNIC0_MSTR_IF_RR_SHRD_HBW_BASE,1765};1766 1767static const u32 gaudi2_pb_nic0_qm_qpc[] = {1768	mmNIC0_QM0_BASE,1769	mmNIC0_QPC0_BASE,1770};1771 1772static const u32 gaudi2_pb_nic0_qm_arc_aux0[] = {1773	mmNIC0_QM_ARC_AUX0_BASE,1774};1775 1776static const struct range gaudi2_pb_nic0_qm_arc_aux0_unsecured_regs[] = {1777	{mmNIC0_QM_ARC_AUX0_RUN_HALT_REQ, mmNIC0_QM_ARC_AUX0_RUN_HALT_ACK},1778	{mmNIC0_QM_ARC_AUX0_CLUSTER_NUM, mmNIC0_QM_ARC_AUX0_WAKE_UP_EVENT},1779	{mmNIC0_QM_ARC_AUX0_ARC_RST_REQ, mmNIC0_QM_ARC_AUX0_CID_OFFSET_7},1780	{mmNIC0_QM_ARC_AUX0_SCRATCHPAD_0, mmNIC0_QM_ARC_AUX0_INFLIGHT_LBU_RD_CNT},1781	{mmNIC0_QM_ARC_AUX0_CBU_EARLY_BRESP_EN, mmNIC0_QM_ARC_AUX0_CBU_EARLY_BRESP_EN},1782	{mmNIC0_QM_ARC_AUX0_LBU_EARLY_BRESP_EN, mmNIC0_QM_ARC_AUX0_LBU_EARLY_BRESP_EN},1783	{mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_BASE_ADDR_0, mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_ALERT_MSG},1784	{mmNIC0_QM_ARC_AUX0_DCCM_Q_PUSH_FIFO_CNT, mmNIC0_QM_ARC_AUX0_QMAN_ARC_CQ_SHADOW_CI},1785	{mmNIC0_QM_ARC_AUX0_ARC_AXI_ORDERING_WR_IF_CNT, mmNIC0_QM_ARC_AUX0_MME_ARC_UPPER_DCCM_EN},1786};1787 1788static const u32 gaudi2_pb_nic0_umr[] = {1789	mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE,1790	mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE + HL_BLOCK_SIZE * 1, /* UMR0_1 */1791	mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE + HL_BLOCK_SIZE * 2, /* UMR0_2 */1792	mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE + HL_BLOCK_SIZE * 3, /* UMR0_3 */1793	mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE + HL_BLOCK_SIZE * 4, /* UMR0_4 */1794	mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE + HL_BLOCK_SIZE * 5, /* UMR0_5 */1795	mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE + HL_BLOCK_SIZE * 6, /* UMR0_6 */1796	mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE + HL_BLOCK_SIZE * 7, /* UMR0_7 */1797	mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE + HL_BLOCK_SIZE * 8, /* UMR0_8 */1798	mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE + HL_BLOCK_SIZE * 9, /* UMR0_9 */1799	mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE + HL_BLOCK_SIZE * 10, /* UMR0_10 */1800	mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE + HL_BLOCK_SIZE * 11, /* UMR0_11 */1801	mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE + HL_BLOCK_SIZE * 12, /* UMR0_12 */1802	mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE + HL_BLOCK_SIZE * 13, /* UMR0_13 */1803	mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE + HL_BLOCK_SIZE * 14, /* UMR0_14 */1804};1805 1806static const struct range gaudi2_pb_nic0_umr_unsecured_regs[] = {1807	{mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32,1808		mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX},1809	{mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32 + HL_BLOCK_SIZE * 1, /* UMR0_1 */1810		mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX + HL_BLOCK_SIZE * 1},1811	{mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32 + HL_BLOCK_SIZE * 2, /* UMR0_2 */1812		mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX + HL_BLOCK_SIZE * 2},1813	{mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32 + HL_BLOCK_SIZE * 3, /* UMR0_3 */1814		mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX + HL_BLOCK_SIZE * 3},1815	{mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32 + HL_BLOCK_SIZE * 4, /* UMR0_4 */1816		mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX + HL_BLOCK_SIZE * 4},1817	{mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32 + HL_BLOCK_SIZE * 5, /* UMR0_5 */1818		mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX + HL_BLOCK_SIZE * 5},1819	{mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32 + HL_BLOCK_SIZE * 6, /* UMR0_6 */1820		mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX + HL_BLOCK_SIZE * 6},1821	{mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32 + HL_BLOCK_SIZE * 7, /* UMR0_7 */1822		mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX + HL_BLOCK_SIZE * 7},1823	{mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32 + HL_BLOCK_SIZE * 8, /* UMR0_8 */1824		mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX + HL_BLOCK_SIZE * 8},1825	{mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32 + HL_BLOCK_SIZE * 9, /* UMR0_9 */1826		mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX + HL_BLOCK_SIZE * 9},1827	{mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32 + HL_BLOCK_SIZE * 10, /* UMR0_10 */1828		mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX + HL_BLOCK_SIZE * 10},1829	{mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32 + HL_BLOCK_SIZE * 11, /* UMR0_11 */1830		mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX + HL_BLOCK_SIZE * 11},1831	{mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32 + HL_BLOCK_SIZE * 12, /* UMR0_12 */1832		mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX + HL_BLOCK_SIZE * 12},1833	{mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32 + HL_BLOCK_SIZE * 13, /* UMR0_13 */1834		mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX + HL_BLOCK_SIZE * 13},1835	{mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32 + HL_BLOCK_SIZE * 14, /* UMR0_14 */1836		mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX + HL_BLOCK_SIZE * 14},1837};1838 1839/*1840 * mmNIC0_QPC0_LINEAR_WQE_QPN and mmNIC0_QPC0_MULTI_STRIDE_WQE_QPN are 32-bit1841 * registers and since the user writes in bulks of 64 bits we need to un-secure1842 * also the following 32 bits (that's why we added also the next 4 bytes to the1843 * table). In the RTL, as part of ECO (2874), writing to the next 4 bytes1844 * triggers a write to the SPECIAL_GLBL_SPARE register, hence it's must be1845 * unsecured as well.1846 */1847#define mmNIC0_QPC0_LINEAR_WQE_RSV (mmNIC0_QPC0_LINEAR_WQE_QPN + 4)1848#define mmNIC0_QPC0_MULTI_STRIDE_WQE_RSV (mmNIC0_QPC0_MULTI_STRIDE_WQE_QPN + 4)1849#define mmNIC0_QPC0_SPECIAL_GLBL_SPARE 0x541FF601850 1851static const u32 gaudi2_pb_nic0_qm_qpc_unsecured_regs[] = {1852	mmNIC0_QPC0_LINEAR_WQE_STATIC_0,1853	mmNIC0_QPC0_LINEAR_WQE_STATIC_1,1854	mmNIC0_QPC0_LINEAR_WQE_STATIC_2,1855	mmNIC0_QPC0_LINEAR_WQE_STATIC_3,1856	mmNIC0_QPC0_LINEAR_WQE_STATIC_4,1857	mmNIC0_QPC0_LINEAR_WQE_STATIC_5,1858	mmNIC0_QPC0_LINEAR_WQE_STATIC_6,1859	mmNIC0_QPC0_LINEAR_WQE_STATIC_7,1860	mmNIC0_QPC0_LINEAR_WQE_STATIC_8,1861	mmNIC0_QPC0_LINEAR_WQE_STATIC_9,1862	mmNIC0_QPC0_LINEAR_WQE_DYNAMIC_0,1863	mmNIC0_QPC0_LINEAR_WQE_DYNAMIC_1,1864	mmNIC0_QPC0_LINEAR_WQE_DYNAMIC_2,1865	mmNIC0_QPC0_LINEAR_WQE_DYNAMIC_3,1866	mmNIC0_QPC0_LINEAR_WQE_DYNAMIC_4,1867	mmNIC0_QPC0_LINEAR_WQE_DYNAMIC_5,1868	mmNIC0_QPC0_LINEAR_WQE_QPN,1869	mmNIC0_QPC0_LINEAR_WQE_RSV,1870	mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_0,1871	mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_1,1872	mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_2,1873	mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_3,1874	mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_4,1875	mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_5,1876	mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_6,1877	mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_7,1878	mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_8,1879	mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_9,1880	mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_10,1881	mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_11,1882	mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_12,1883	mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_13,1884	mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_14,1885	mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_15,1886	mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_16,1887	mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_17,1888	mmNIC0_QPC0_MULTI_STRIDE_WQE_DYNAMIC_0,1889	mmNIC0_QPC0_MULTI_STRIDE_WQE_DYNAMIC_1,1890	mmNIC0_QPC0_MULTI_STRIDE_WQE_DYNAMIC_2,1891	mmNIC0_QPC0_MULTI_STRIDE_WQE_DYNAMIC_3,1892	mmNIC0_QPC0_MULTI_STRIDE_WQE_DYNAMIC_4,1893	mmNIC0_QPC0_MULTI_STRIDE_WQE_DYNAMIC_5,1894	mmNIC0_QPC0_MULTI_STRIDE_WQE_QPN,1895	mmNIC0_QPC0_MULTI_STRIDE_WQE_RSV,1896	mmNIC0_QPC0_QMAN_DOORBELL,1897	mmNIC0_QPC0_QMAN_DOORBELL_QPN,1898	mmNIC0_QPC0_SPECIAL_GLBL_SPARE,1899	mmNIC0_QM0_CQ_CFG0_0,1900	mmNIC0_QM0_CQ_CFG0_1,1901	mmNIC0_QM0_CQ_CFG0_2,1902	mmNIC0_QM0_CQ_CFG0_3,1903	mmNIC0_QM0_CQ_CFG0_4,1904	mmNIC0_QM0_CP_FENCE0_RDATA_0,1905	mmNIC0_QM0_CP_FENCE0_RDATA_1,1906	mmNIC0_QM0_CP_FENCE0_RDATA_2,1907	mmNIC0_QM0_CP_FENCE0_RDATA_3,1908	mmNIC0_QM0_CP_FENCE0_RDATA_4,1909	mmNIC0_QM0_CP_FENCE1_RDATA_0,1910	mmNIC0_QM0_CP_FENCE1_RDATA_1,1911	mmNIC0_QM0_CP_FENCE1_RDATA_2,1912	mmNIC0_QM0_CP_FENCE1_RDATA_3,1913	mmNIC0_QM0_CP_FENCE1_RDATA_4,1914	mmNIC0_QM0_CP_FENCE2_RDATA_0,1915	mmNIC0_QM0_CP_FENCE2_RDATA_1,1916	mmNIC0_QM0_CP_FENCE2_RDATA_2,1917	mmNIC0_QM0_CP_FENCE2_RDATA_3,1918	mmNIC0_QM0_CP_FENCE2_RDATA_4,1919	mmNIC0_QM0_CP_FENCE3_RDATA_0,1920	mmNIC0_QM0_CP_FENCE3_RDATA_1,1921	mmNIC0_QM0_CP_FENCE3_RDATA_2,1922	mmNIC0_QM0_CP_FENCE3_RDATA_3,1923	mmNIC0_QM0_CP_FENCE3_RDATA_4,1924	mmNIC0_QM0_CP_FENCE0_CNT_0,1925	mmNIC0_QM0_CP_FENCE0_CNT_1,1926	mmNIC0_QM0_CP_FENCE0_CNT_2,1927	mmNIC0_QM0_CP_FENCE0_CNT_3,1928	mmNIC0_QM0_CP_FENCE0_CNT_4,1929	mmNIC0_QM0_CP_FENCE1_CNT_0,1930	mmNIC0_QM0_CP_FENCE1_CNT_1,1931	mmNIC0_QM0_CP_FENCE1_CNT_2,1932	mmNIC0_QM0_CP_FENCE1_CNT_3,1933	mmNIC0_QM0_CP_FENCE1_CNT_4,1934	mmNIC0_QM0_CP_FENCE2_CNT_0,1935	mmNIC0_QM0_CP_FENCE2_CNT_1,1936	mmNIC0_QM0_CP_FENCE2_CNT_2,1937	mmNIC0_QM0_CP_FENCE2_CNT_3,1938	mmNIC0_QM0_CP_FENCE2_CNT_4,1939	mmNIC0_QM0_CP_FENCE3_CNT_0,1940	mmNIC0_QM0_CP_FENCE3_CNT_1,1941	mmNIC0_QM0_CP_FENCE3_CNT_2,1942	mmNIC0_QM0_CP_FENCE3_CNT_3,1943	mmNIC0_QM0_CP_FENCE3_CNT_4,1944	mmNIC0_QM0_CQ_PTR_LO_0,1945	mmNIC0_QM0_CQ_PTR_HI_0,1946	mmNIC0_QM0_CQ_TSIZE_0,1947	mmNIC0_QM0_CQ_CTL_0,1948	mmNIC0_QM0_CQ_PTR_LO_1,1949	mmNIC0_QM0_CQ_PTR_HI_1,1950	mmNIC0_QM0_CQ_TSIZE_1,1951	mmNIC0_QM0_CQ_CTL_1,1952	mmNIC0_QM0_CQ_PTR_LO_2,1953	mmNIC0_QM0_CQ_PTR_HI_2,1954	mmNIC0_QM0_CQ_TSIZE_2,1955	mmNIC0_QM0_CQ_CTL_2,1956	mmNIC0_QM0_CQ_PTR_LO_3,1957	mmNIC0_QM0_CQ_PTR_HI_3,1958	mmNIC0_QM0_CQ_TSIZE_3,1959	mmNIC0_QM0_CQ_CTL_3,1960	mmNIC0_QM0_CQ_PTR_LO_4,1961	mmNIC0_QM0_CQ_PTR_HI_4,1962	mmNIC0_QM0_CQ_TSIZE_4,1963	mmNIC0_QM0_CQ_CTL_4,1964	mmNIC0_QM0_QMAN_WR64_BASE_ADDR0_BASE,1965	mmNIC0_QM0_QMAN_WR64_BASE_ADDR0_BASE + 4,1966	mmNIC0_QM0_QMAN_WR64_BASE_ADDR1_BASE,1967	mmNIC0_QM0_QMAN_WR64_BASE_ADDR1_BASE + 4,1968	mmNIC0_QM0_QMAN_WR64_BASE_ADDR2_BASE,1969	mmNIC0_QM0_QMAN_WR64_BASE_ADDR2_BASE + 4,1970	mmNIC0_QM0_QMAN_WR64_BASE_ADDR3_BASE,1971	mmNIC0_QM0_QMAN_WR64_BASE_ADDR3_BASE + 4,1972	mmNIC0_QM0_QMAN_WR64_BASE_ADDR4_BASE,1973	mmNIC0_QM0_QMAN_WR64_BASE_ADDR4_BASE + 4,1974	mmNIC0_QM0_QMAN_WR64_BASE_ADDR5_BASE,1975	mmNIC0_QM0_QMAN_WR64_BASE_ADDR5_BASE + 4,1976	mmNIC0_QM0_QMAN_WR64_BASE_ADDR6_BASE,1977	mmNIC0_QM0_QMAN_WR64_BASE_ADDR6_BASE + 4,1978	mmNIC0_QM0_QMAN_WR64_BASE_ADDR7_BASE,1979	mmNIC0_QM0_QMAN_WR64_BASE_ADDR7_BASE + 4,1980	mmNIC0_QM0_QMAN_WR64_BASE_ADDR8_BASE,1981	mmNIC0_QM0_QMAN_WR64_BASE_ADDR8_BASE + 4,1982	mmNIC0_QM0_QMAN_WR64_BASE_ADDR9_BASE,1983	mmNIC0_QM0_QMAN_WR64_BASE_ADDR9_BASE + 4,1984	mmNIC0_QM0_QMAN_WR64_BASE_ADDR10_BASE,1985	mmNIC0_QM0_QMAN_WR64_BASE_ADDR10_BASE + 4,1986	mmNIC0_QM0_QMAN_WR64_BASE_ADDR11_BASE,1987	mmNIC0_QM0_QMAN_WR64_BASE_ADDR11_BASE + 4,1988	mmNIC0_QM0_QMAN_WR64_BASE_ADDR12_BASE,1989	mmNIC0_QM0_QMAN_WR64_BASE_ADDR12_BASE + 4,1990	mmNIC0_QM0_QMAN_WR64_BASE_ADDR13_BASE,1991	mmNIC0_QM0_QMAN_WR64_BASE_ADDR13_BASE + 4,1992	mmNIC0_QM0_QMAN_WR64_BASE_ADDR14_BASE,1993	mmNIC0_QM0_QMAN_WR64_BASE_ADDR14_BASE + 4,1994	mmNIC0_QM0_QMAN_WR64_BASE_ADDR15_BASE,1995	mmNIC0_QM0_QMAN_WR64_BASE_ADDR15_BASE + 4,1996	mmNIC0_QM0_ARC_CQ_PTR_LO,1997	mmNIC0_QM0_ARC_CQ_PTR_LO_STS,1998	mmNIC0_QM0_ARC_CQ_PTR_HI,1999	mmNIC0_QM0_ARC_CQ_PTR_HI_STS,2000	mmNIC0_QM0_ARB_CFG_0,2001	mmNIC0_QM0_ARB_MST_QUIET_PER,2002	mmNIC0_QM0_ARB_CHOICE_Q_PUSH,2003	mmNIC0_QM0_ARB_WRR_WEIGHT_0,2004	mmNIC0_QM0_ARB_WRR_WEIGHT_1,2005	mmNIC0_QM0_ARB_WRR_WEIGHT_2,2006	mmNIC0_QM0_ARB_WRR_WEIGHT_3,2007	mmNIC0_QM0_ARB_BASE_LO,2008	mmNIC0_QM0_ARB_BASE_HI,2009	mmNIC0_QM0_ARB_MST_SLAVE_EN,2010	mmNIC0_QM0_ARB_MST_SLAVE_EN_1,2011	mmNIC0_QM0_ARB_MST_CRED_INC,2012	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_0,2013	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_1,2014	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_2,2015	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_3,2016	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_4,2017	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_5,2018	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_6,2019	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_7,2020	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_8,2021	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_9,2022	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_10,2023	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_11,2024	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_12,2025	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_13,2026	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_14,2027	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_15,2028	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_16,2029	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_17,2030	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_18,2031	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_19,2032	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_20,2033	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_21,2034	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_22,2035	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_23,2036	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_24,2037	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_25,2038	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_26,2039	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_27,2040	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_28,2041	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_29,2042	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_30,2043	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_31,2044	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_32,2045	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_33,2046	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_34,2047	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_35,2048	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_36,2049	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_37,2050	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_38,2051	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_39,2052	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_40,2053	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_41,2054	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_42,2055	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_43,2056	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_44,2057	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_45,2058	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_46,2059	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_47,2060	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_48,2061	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_49,2062	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_50,2063	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_51,2064	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_52,2065	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_53,2066	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_54,2067	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_55,2068	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_56,2069	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_57,2070	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_58,2071	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_59,2072	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_60,2073	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_61,2074	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_62,2075	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_63,2076	mmNIC0_QM0_ARB_SLV_ID,2077	mmNIC0_QM0_ARB_SLV_MASTER_INC_CRED_OFST,2078	mmNIC0_QM0_ARC_CQ_CFG0,2079	mmNIC0_QM0_CQ_IFIFO_CI_0,2080	mmNIC0_QM0_CQ_IFIFO_CI_1,2081	mmNIC0_QM0_CQ_IFIFO_CI_2,2082	mmNIC0_QM0_CQ_IFIFO_CI_3,2083	mmNIC0_QM0_CQ_IFIFO_CI_4,2084	mmNIC0_QM0_ARC_CQ_IFIFO_CI,2085	mmNIC0_QM0_CQ_CTL_CI_0,2086	mmNIC0_QM0_CQ_CTL_CI_1,2087	mmNIC0_QM0_CQ_CTL_CI_2,2088	mmNIC0_QM0_CQ_CTL_CI_3,2089	mmNIC0_QM0_CQ_CTL_CI_4,2090	mmNIC0_QM0_ARC_CQ_CTL_CI,2091	mmNIC0_QM0_ARC_CQ_TSIZE,2092	mmNIC0_QM0_ARC_CQ_CTL,2093	mmNIC0_QM0_CP_SWITCH_WD_SET,2094	mmNIC0_QM0_CP_EXT_SWITCH,2095	mmNIC0_QM0_CP_PRED_0,2096	mmNIC0_QM0_CP_PRED_1,2097	mmNIC0_QM0_CP_PRED_2,2098	mmNIC0_QM0_CP_PRED_3,2099	mmNIC0_QM0_CP_PRED_4,2100	mmNIC0_QM0_CP_PRED_UPEN_0,2101	mmNIC0_QM0_CP_PRED_UPEN_1,2102	mmNIC0_QM0_CP_PRED_UPEN_2,2103	mmNIC0_QM0_CP_PRED_UPEN_3,2104	mmNIC0_QM0_CP_PRED_UPEN_4,2105	mmNIC0_QM0_CP_MSG_BASE0_ADDR_LO_0,2106	mmNIC0_QM0_CP_MSG_BASE0_ADDR_LO_1,2107	mmNIC0_QM0_CP_MSG_BASE0_ADDR_LO_2,2108	mmNIC0_QM0_CP_MSG_BASE0_ADDR_LO_3,2109	mmNIC0_QM0_CP_MSG_BASE0_ADDR_LO_4,2110	mmNIC0_QM0_CP_MSG_BASE0_ADDR_HI_0,2111	mmNIC0_QM0_CP_MSG_BASE0_ADDR_HI_1,2112	mmNIC0_QM0_CP_MSG_BASE0_ADDR_HI_2,2113	mmNIC0_QM0_CP_MSG_BASE0_ADDR_HI_3,2114	mmNIC0_QM0_CP_MSG_BASE0_ADDR_HI_4,2115	mmNIC0_QM0_CP_MSG_BASE1_ADDR_LO_0,2116	mmNIC0_QM0_CP_MSG_BASE1_ADDR_LO_1,2117	mmNIC0_QM0_CP_MSG_BASE1_ADDR_LO_2,2118	mmNIC0_QM0_CP_MSG_BASE1_ADDR_LO_3,2119	mmNIC0_QM0_CP_MSG_BASE1_ADDR_LO_4,2120	mmNIC0_QM0_CP_MSG_BASE1_ADDR_HI_0,2121	mmNIC0_QM0_CP_MSG_BASE1_ADDR_HI_1,2122	mmNIC0_QM0_CP_MSG_BASE1_ADDR_HI_2,2123	mmNIC0_QM0_CP_MSG_BASE1_ADDR_HI_3,2124	mmNIC0_QM0_CP_MSG_BASE1_ADDR_HI_4,2125	mmNIC0_QM0_CP_MSG_BASE2_ADDR_LO_0,2126	mmNIC0_QM0_CP_MSG_BASE2_ADDR_LO_1,2127	mmNIC0_QM0_CP_MSG_BASE2_ADDR_LO_2,2128	mmNIC0_QM0_CP_MSG_BASE2_ADDR_LO_3,2129	mmNIC0_QM0_CP_MSG_BASE2_ADDR_LO_4,2130	mmNIC0_QM0_CP_MSG_BASE2_ADDR_HI_0,2131	mmNIC0_QM0_CP_MSG_BASE2_ADDR_HI_1,2132	mmNIC0_QM0_CP_MSG_BASE2_ADDR_HI_2,2133	mmNIC0_QM0_CP_MSG_BASE2_ADDR_HI_3,2134	mmNIC0_QM0_CP_MSG_BASE2_ADDR_HI_4,2135	mmNIC0_QM0_CP_MSG_BASE3_ADDR_LO_0,2136	mmNIC0_QM0_CP_MSG_BASE3_ADDR_LO_1,2137	mmNIC0_QM0_CP_MSG_BASE3_ADDR_LO_2,2138	mmNIC0_QM0_CP_MSG_BASE3_ADDR_LO_3,2139	mmNIC0_QM0_CP_MSG_BASE3_ADDR_LO_4,2140	mmNIC0_QM0_CP_MSG_BASE3_ADDR_HI_0,2141	mmNIC0_QM0_CP_MSG_BASE3_ADDR_HI_1,2142	mmNIC0_QM0_CP_MSG_BASE3_ADDR_HI_2,2143	mmNIC0_QM0_CP_MSG_BASE3_ADDR_HI_3,2144	mmNIC0_QM0_CP_MSG_BASE3_ADDR_HI_4,2145	mmNIC0_QM0_ARC_CQ_IFIFO_MSG_BASE_LO,2146	mmNIC0_QM0_ARC_CQ_CTL_MSG_BASE_LO,2147	mmNIC0_QM0_CQ_IFIFO_MSG_BASE_LO,2148	mmNIC0_QM0_CQ_CTL_MSG_BASE_LO2149};2150 2151static const u32 gaudi2_pb_rot0[] = {2152	mmROT0_BASE,2153	mmROT0_MSTR_IF_RR_SHRD_HBW_BASE,2154	mmROT0_QM_BASE,2155};2156 2157static const u32 gaudi2_pb_rot0_arc[] = {2158	mmROT0_QM_ARC_AUX_BASE2159};2160 2161static const struct range gaudi2_pb_rot0_arc_unsecured_regs[] = {2162	{mmROT0_QM_ARC_AUX_RUN_HALT_REQ, mmROT0_QM_ARC_AUX_RUN_HALT_ACK},2163	{mmROT0_QM_ARC_AUX_CLUSTER_NUM, mmROT0_QM_ARC_AUX_WAKE_UP_EVENT},2164	{mmROT0_QM_ARC_AUX_ARC_RST_REQ, mmROT0_QM_ARC_AUX_CID_OFFSET_7},2165	{mmROT0_QM_ARC_AUX_SCRATCHPAD_0, mmROT0_QM_ARC_AUX_INFLIGHT_LBU_RD_CNT},2166	{mmROT0_QM_ARC_AUX_CBU_EARLY_BRESP_EN, mmROT0_QM_ARC_AUX_CBU_EARLY_BRESP_EN},2167	{mmROT0_QM_ARC_AUX_LBU_EARLY_BRESP_EN, mmROT0_QM_ARC_AUX_LBU_EARLY_BRESP_EN},2168	{mmROT0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_0, mmROT0_QM_ARC_AUX_DCCM_QUEUE_ALERT_MSG},2169	{mmROT0_QM_ARC_AUX_DCCM_Q_PUSH_FIFO_CNT, mmROT0_QM_ARC_AUX_QMAN_ARC_CQ_SHADOW_CI},2170	{mmROT0_QM_ARC_AUX_ARC_AXI_ORDERING_WR_IF_CNT, mmROT0_QM_ARC_AUX_MME_ARC_UPPER_DCCM_EN},2171};2172 2173static const u32 gaudi2_pb_rot0_unsecured_regs[] = {2174	mmROT0_QM_CQ_CFG0_0,2175	mmROT0_QM_CQ_CFG0_1,2176	mmROT0_QM_CQ_CFG0_2,2177	mmROT0_QM_CQ_CFG0_3,2178	mmROT0_QM_CQ_CFG0_4,2179	mmROT0_QM_CP_FENCE0_RDATA_0,2180	mmROT0_QM_CP_FENCE0_RDATA_1,2181	mmROT0_QM_CP_FENCE0_RDATA_2,2182	mmROT0_QM_CP_FENCE0_RDATA_3,2183	mmROT0_QM_CP_FENCE0_RDATA_4,2184	mmROT0_QM_CP_FENCE1_RDATA_0,2185	mmROT0_QM_CP_FENCE1_RDATA_1,2186	mmROT0_QM_CP_FENCE1_RDATA_2,2187	mmROT0_QM_CP_FENCE1_RDATA_3,2188	mmROT0_QM_CP_FENCE1_RDATA_4,2189	mmROT0_QM_CP_FENCE2_RDATA_0,2190	mmROT0_QM_CP_FENCE2_RDATA_1,2191	mmROT0_QM_CP_FENCE2_RDATA_2,2192	mmROT0_QM_CP_FENCE2_RDATA_3,2193	mmROT0_QM_CP_FENCE2_RDATA_4,2194	mmROT0_QM_CP_FENCE3_RDATA_0,2195	mmROT0_QM_CP_FENCE3_RDATA_1,2196	mmROT0_QM_CP_FENCE3_RDATA_2,2197	mmROT0_QM_CP_FENCE3_RDATA_3,2198	mmROT0_QM_CP_FENCE3_RDATA_4,2199	mmROT0_QM_CP_FENCE0_CNT_0,2200	mmROT0_QM_CP_FENCE0_CNT_1,2201	mmROT0_QM_CP_FENCE0_CNT_2,2202	mmROT0_QM_CP_FENCE0_CNT_3,2203	mmROT0_QM_CP_FENCE0_CNT_4,2204	mmROT0_QM_CP_FENCE1_CNT_0,2205	mmROT0_QM_CP_FENCE1_CNT_1,2206	mmROT0_QM_CP_FENCE1_CNT_2,2207	mmROT0_QM_CP_FENCE1_CNT_3,2208	mmROT0_QM_CP_FENCE1_CNT_4,2209	mmROT0_QM_CP_FENCE2_CNT_0,2210	mmROT0_QM_CP_FENCE2_CNT_1,2211	mmROT0_QM_CP_FENCE2_CNT_2,2212	mmROT0_QM_CP_FENCE2_CNT_3,2213	mmROT0_QM_CP_FENCE2_CNT_4,2214	mmROT0_QM_CP_FENCE3_CNT_0,2215	mmROT0_QM_CP_FENCE3_CNT_1,2216	mmROT0_QM_CP_FENCE3_CNT_2,2217	mmROT0_QM_CP_FENCE3_CNT_3,2218	mmROT0_QM_CP_FENCE3_CNT_4,2219	mmROT0_QM_CQ_PTR_LO_0,2220	mmROT0_QM_CQ_PTR_HI_0,2221	mmROT0_QM_CQ_TSIZE_0,2222	mmROT0_QM_CQ_CTL_0,2223	mmROT0_QM_CQ_PTR_LO_1,2224	mmROT0_QM_CQ_PTR_HI_1,2225	mmROT0_QM_CQ_TSIZE_1,2226	mmROT0_QM_CQ_CTL_1,2227	mmROT0_QM_CQ_PTR_LO_2,2228	mmROT0_QM_CQ_PTR_HI_2,2229	mmROT0_QM_CQ_TSIZE_2,2230	mmROT0_QM_CQ_CTL_2,2231	mmROT0_QM_CQ_PTR_LO_3,2232	mmROT0_QM_CQ_PTR_HI_3,2233	mmROT0_QM_CQ_TSIZE_3,2234	mmROT0_QM_CQ_CTL_3,2235	mmROT0_QM_CQ_PTR_LO_4,2236	mmROT0_QM_CQ_PTR_HI_4,2237	mmROT0_QM_CQ_TSIZE_4,2238	mmROT0_QM_CQ_CTL_4,2239	mmROT0_QM_QMAN_WR64_BASE_ADDR0_BASE,2240	mmROT0_QM_QMAN_WR64_BASE_ADDR0_BASE + 4,2241	mmROT0_QM_QMAN_WR64_BASE_ADDR1_BASE,2242	mmROT0_QM_QMAN_WR64_BASE_ADDR1_BASE + 4,2243	mmROT0_QM_QMAN_WR64_BASE_ADDR2_BASE,2244	mmROT0_QM_QMAN_WR64_BASE_ADDR2_BASE + 4,2245	mmROT0_QM_QMAN_WR64_BASE_ADDR3_BASE,2246	mmROT0_QM_QMAN_WR64_BASE_ADDR3_BASE + 4,2247	mmROT0_QM_QMAN_WR64_BASE_ADDR4_BASE,2248	mmROT0_QM_QMAN_WR64_BASE_ADDR4_BASE + 4,2249	mmROT0_QM_QMAN_WR64_BASE_ADDR5_BASE,2250	mmROT0_QM_QMAN_WR64_BASE_ADDR5_BASE + 4,2251	mmROT0_QM_QMAN_WR64_BASE_ADDR6_BASE,2252	mmROT0_QM_QMAN_WR64_BASE_ADDR6_BASE + 4,2253	mmROT0_QM_QMAN_WR64_BASE_ADDR7_BASE,2254	mmROT0_QM_QMAN_WR64_BASE_ADDR7_BASE + 4,2255	mmROT0_QM_QMAN_WR64_BASE_ADDR8_BASE,2256	mmROT0_QM_QMAN_WR64_BASE_ADDR8_BASE + 4,2257	mmROT0_QM_QMAN_WR64_BASE_ADDR9_BASE,2258	mmROT0_QM_QMAN_WR64_BASE_ADDR9_BASE + 4,2259	mmROT0_QM_QMAN_WR64_BASE_ADDR10_BASE,2260	mmROT0_QM_QMAN_WR64_BASE_ADDR10_BASE + 4,2261	mmROT0_QM_QMAN_WR64_BASE_ADDR11_BASE,2262	mmROT0_QM_QMAN_WR64_BASE_ADDR11_BASE + 4,2263	mmROT0_QM_QMAN_WR64_BASE_ADDR12_BASE,2264	mmROT0_QM_QMAN_WR64_BASE_ADDR12_BASE + 4,2265	mmROT0_QM_QMAN_WR64_BASE_ADDR13_BASE,2266	mmROT0_QM_QMAN_WR64_BASE_ADDR13_BASE + 4,2267	mmROT0_QM_QMAN_WR64_BASE_ADDR14_BASE,2268	mmROT0_QM_QMAN_WR64_BASE_ADDR14_BASE + 4,2269	mmROT0_QM_QMAN_WR64_BASE_ADDR15_BASE,2270	mmROT0_QM_QMAN_WR64_BASE_ADDR15_BASE + 4,2271	mmROT0_QM_ARC_CQ_PTR_LO,2272	mmROT0_QM_ARC_CQ_PTR_LO_STS,2273	mmROT0_QM_ARC_CQ_PTR_HI,2274	mmROT0_QM_ARC_CQ_PTR_HI_STS,2275	mmROT0_QM_ARB_CFG_0,2276	mmROT0_QM_ARB_MST_QUIET_PER,2277	mmROT0_QM_ARB_CHOICE_Q_PUSH,2278	mmROT0_QM_ARB_WRR_WEIGHT_0,2279	mmROT0_QM_ARB_WRR_WEIGHT_1,2280	mmROT0_QM_ARB_WRR_WEIGHT_2,2281	mmROT0_QM_ARB_WRR_WEIGHT_3,2282	mmROT0_QM_ARB_BASE_LO,2283	mmROT0_QM_ARB_BASE_HI,2284	mmROT0_QM_ARB_MST_SLAVE_EN,2285	mmROT0_QM_ARB_MST_SLAVE_EN_1,2286	mmROT0_QM_ARB_MST_CRED_INC,2287	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_0,2288	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_1,2289	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_2,2290	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_3,2291	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_4,2292	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_5,2293	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_6,2294	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_7,2295	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_8,2296	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_9,2297	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_10,2298	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_11,2299	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_12,2300	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_13,2301	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_14,2302	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_15,2303	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_16,2304	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_17,2305	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_18,2306	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_19,2307	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_20,2308	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_21,2309	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_22,2310	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_23,2311	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_24,2312	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_25,2313	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_26,2314	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_27,2315	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_28,2316	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_29,2317	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_30,2318	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_31,2319	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_32,2320	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_33,2321	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_34,2322	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_35,2323	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_36,2324	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_37,2325	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_38,2326	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_39,2327	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_40,2328	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_41,2329	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_42,2330	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_43,2331	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_44,2332	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_45,2333	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_46,2334	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_47,2335	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_48,2336	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_49,2337	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_50,2338	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_51,2339	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_52,2340	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_53,2341	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_54,2342	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_55,2343	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_56,2344	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_57,2345	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_58,2346	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_59,2347	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_60,2348	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_61,2349	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_62,2350	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_63,2351	mmROT0_QM_ARB_SLV_ID,2352	mmROT0_QM_ARB_SLV_MASTER_INC_CRED_OFST,2353	mmROT0_QM_ARC_CQ_CFG0,2354	mmROT0_QM_CQ_IFIFO_CI_0,2355	mmROT0_QM_CQ_IFIFO_CI_1,2356	mmROT0_QM_CQ_IFIFO_CI_2,2357	mmROT0_QM_CQ_IFIFO_CI_3,2358	mmROT0_QM_CQ_IFIFO_CI_4,2359	mmROT0_QM_ARC_CQ_IFIFO_CI,2360	mmROT0_QM_CQ_CTL_CI_0,2361	mmROT0_QM_CQ_CTL_CI_1,2362	mmROT0_QM_CQ_CTL_CI_2,2363	mmROT0_QM_CQ_CTL_CI_3,2364	mmROT0_QM_CQ_CTL_CI_4,2365	mmROT0_QM_ARC_CQ_CTL_CI,2366	mmROT0_QM_ARC_CQ_TSIZE,2367	mmROT0_QM_ARC_CQ_CTL,2368	mmROT0_QM_CP_SWITCH_WD_SET,2369	mmROT0_QM_CP_EXT_SWITCH,2370	mmROT0_QM_CP_PRED_0,2371	mmROT0_QM_CP_PRED_1,2372	mmROT0_QM_CP_PRED_2,2373	mmROT0_QM_CP_PRED_3,2374	mmROT0_QM_CP_PRED_4,2375	mmROT0_QM_CP_PRED_UPEN_0,2376	mmROT0_QM_CP_PRED_UPEN_1,2377	mmROT0_QM_CP_PRED_UPEN_2,2378	mmROT0_QM_CP_PRED_UPEN_3,2379	mmROT0_QM_CP_PRED_UPEN_4,2380	mmROT0_QM_CP_MSG_BASE0_ADDR_LO_0,2381	mmROT0_QM_CP_MSG_BASE0_ADDR_LO_1,2382	mmROT0_QM_CP_MSG_BASE0_ADDR_LO_2,2383	mmROT0_QM_CP_MSG_BASE0_ADDR_LO_3,2384	mmROT0_QM_CP_MSG_BASE0_ADDR_LO_4,2385	mmROT0_QM_CP_MSG_BASE0_ADDR_HI_0,2386	mmROT0_QM_CP_MSG_BASE0_ADDR_HI_1,2387	mmROT0_QM_CP_MSG_BASE0_ADDR_HI_2,2388	mmROT0_QM_CP_MSG_BASE0_ADDR_HI_3,2389	mmROT0_QM_CP_MSG_BASE0_ADDR_HI_4,2390	mmROT0_QM_CP_MSG_BASE1_ADDR_LO_0,2391	mmROT0_QM_CP_MSG_BASE1_ADDR_LO_1,2392	mmROT0_QM_CP_MSG_BASE1_ADDR_LO_2,2393	mmROT0_QM_CP_MSG_BASE1_ADDR_LO_3,2394	mmROT0_QM_CP_MSG_BASE1_ADDR_LO_4,2395	mmROT0_QM_CP_MSG_BASE1_ADDR_HI_0,2396	mmROT0_QM_CP_MSG_BASE1_ADDR_HI_1,2397	mmROT0_QM_CP_MSG_BASE1_ADDR_HI_2,2398	mmROT0_QM_CP_MSG_BASE1_ADDR_HI_3,2399	mmROT0_QM_CP_MSG_BASE1_ADDR_HI_4,2400	mmROT0_QM_CP_MSG_BASE2_ADDR_LO_0,2401	mmROT0_QM_CP_MSG_BASE2_ADDR_LO_1,2402	mmROT0_QM_CP_MSG_BASE2_ADDR_LO_2,2403	mmROT0_QM_CP_MSG_BASE2_ADDR_LO_3,2404	mmROT0_QM_CP_MSG_BASE2_ADDR_LO_4,2405	mmROT0_QM_CP_MSG_BASE2_ADDR_HI_0,2406	mmROT0_QM_CP_MSG_BASE2_ADDR_HI_1,2407	mmROT0_QM_CP_MSG_BASE2_ADDR_HI_2,2408	mmROT0_QM_CP_MSG_BASE2_ADDR_HI_3,2409	mmROT0_QM_CP_MSG_BASE2_ADDR_HI_4,2410	mmROT0_QM_CP_MSG_BASE3_ADDR_LO_0,2411	mmROT0_QM_CP_MSG_BASE3_ADDR_LO_1,2412	mmROT0_QM_CP_MSG_BASE3_ADDR_LO_2,2413	mmROT0_QM_CP_MSG_BASE3_ADDR_LO_3,2414	mmROT0_QM_CP_MSG_BASE3_ADDR_LO_4,2415	mmROT0_QM_CP_MSG_BASE3_ADDR_HI_0,2416	mmROT0_QM_CP_MSG_BASE3_ADDR_HI_1,2417	mmROT0_QM_CP_MSG_BASE3_ADDR_HI_2,2418	mmROT0_QM_CP_MSG_BASE3_ADDR_HI_3,2419	mmROT0_QM_CP_MSG_BASE3_ADDR_HI_4,2420	mmROT0_QM_ARC_CQ_IFIFO_MSG_BASE_LO,2421	mmROT0_QM_ARC_CQ_CTL_MSG_BASE_LO,2422	mmROT0_QM_CQ_IFIFO_MSG_BASE_LO,2423	mmROT0_QM_CQ_CTL_MSG_BASE_LO,2424	mmROT0_DESC_CONTEXT_ID,2425	mmROT0_DESC_IN_IMG_START_ADDR_L,2426	mmROT0_DESC_IN_IMG_START_ADDR_H,2427	mmROT0_DESC_OUT_IMG_START_ADDR_L,2428	mmROT0_DESC_OUT_IMG_START_ADDR_H,2429	mmROT0_DESC_CFG,2430	mmROT0_DESC_IM_READ_SLOPE,2431	mmROT0_DESC_SIN_D,2432	mmROT0_DESC_COS_D,2433	mmROT0_DESC_IN_IMG,2434	mmROT0_DESC_IN_STRIDE,2435	mmROT0_DESC_IN_STRIPE,2436	mmROT0_DESC_IN_CENTER,2437	mmROT0_DESC_OUT_IMG,2438	mmROT0_DESC_OUT_STRIDE,2439	mmROT0_DESC_OUT_STRIPE,2440	mmROT0_DESC_OUT_CENTER,2441	mmROT0_DESC_BACKGROUND,2442	mmROT0_DESC_CPL_MSG_EN,2443	mmROT0_DESC_IDLE_STATE,2444	mmROT0_DESC_CPL_MSG_ADDR,2445	mmROT0_DESC_CPL_MSG_DATA,2446	mmROT0_DESC_X_I_START_OFFSET,2447	mmROT0_DESC_X_I_START_OFFSET_FLIP,2448	mmROT0_DESC_X_I_FIRST,2449	mmROT0_DESC_Y_I_FIRST,2450	mmROT0_DESC_Y_I,2451	mmROT0_DESC_OUT_STRIPE_SIZE,2452	mmROT0_DESC_RSB_CFG_0,2453	mmROT0_DESC_RSB_PAD_VAL,2454	mmROT0_DESC_OWM_CFG,2455	mmROT0_DESC_CTRL_CFG,2456	mmROT0_DESC_PIXEL_PAD,2457	mmROT0_DESC_PREC_SHIFT,2458	mmROT0_DESC_MAX_VAL,2459	mmROT0_DESC_A0_M11,2460	mmROT0_DESC_A1_M12,2461	mmROT0_DESC_A2,2462	mmROT0_DESC_B0_M21,2463	mmROT0_DESC_B1_M22,2464	mmROT0_DESC_B2,2465	mmROT0_DESC_C0,2466	mmROT0_DESC_C1,2467	mmROT0_DESC_C2,2468	mmROT0_DESC_D0,2469	mmROT0_DESC_D1,2470	mmROT0_DESC_D2,2471	mmROT0_DESC_INV_PROC_SIZE_M_1,2472	mmROT0_DESC_MESH_IMG_START_ADDR_L,2473	mmROT0_DESC_MESH_IMG_START_ADDR_H,2474	mmROT0_DESC_MESH_IMG,2475	mmROT0_DESC_MESH_STRIDE,2476	mmROT0_DESC_MESH_STRIPE,2477	mmROT0_DESC_MESH_CTRL,2478	mmROT0_DESC_MESH_GH,2479	mmROT0_DESC_MESH_GV,2480	mmROT0_DESC_MRSB_CFG_0,2481	mmROT0_DESC_MRSB_PAD_VAL,2482	mmROT0_DESC_BUF_CFG,2483	mmROT0_DESC_CID_OFFSET,2484	mmROT0_DESC_PUSH_DESC2485};2486 2487static const u32 gaudi2_pb_psoc_global_conf[] = {2488	mmPSOC_GLOBAL_CONF_BASE2489};2490 2491static const u32 gaudi2_pb_psoc[] = {2492	mmPSOC_EFUSE_BASE,2493	mmPSOC_BTL_BASE,2494	mmPSOC_CS_TRACE_BASE,2495	mmPSOC_DFT_EFUSE_BASE,2496	mmPSOC_PID_BASE,2497	mmPSOC_ARC0_CFG_BASE,2498	mmPSOC_ARC0_MSTR_IF_RR_SHRD_HBW_BASE,2499	mmPSOC_ARC0_AUX_BASE,2500	mmPSOC_ARC1_CFG_BASE,2501	mmPSOC_ARC1_MSTR_IF_RR_SHRD_HBW_BASE,2502	mmPSOC_ARC1_AUX_BASE,2503	mmJT_MSTR_IF_RR_SHRD_HBW_BASE,2504	mmSMI_MSTR_IF_RR_SHRD_HBW_BASE,2505	mmI2C_S_MSTR_IF_RR_SHRD_HBW_BASE,2506	mmPSOC_SVID0_BASE,2507	mmPSOC_SVID1_BASE,2508	mmPSOC_SVID2_BASE,2509	mmPSOC_AVS0_BASE,2510	mmPSOC_AVS1_BASE,2511	mmPSOC_AVS2_BASE,2512	mmPSOC_PWM0_BASE,2513	mmPSOC_PWM1_BASE,2514	mmPSOC_MSTR_IF_RR_SHRD_HBW_BASE,2515};2516 2517static const u32 gaudi2_pb_pmmu[] = {2518	mmPMMU_HBW_MMU_BASE,2519	mmPMMU_HBW_STLB_BASE,2520	mmPMMU_HBW_MSTR_IF_RR_SHRD_HBW_BASE,2521	mmPMMU_PIF_BASE,2522};2523 2524static const u32 gaudi2_pb_psoc_pll[] = {2525	mmPSOC_MME_PLL_CTRL_BASE,2526	mmPSOC_CPU_PLL_CTRL_BASE,2527	mmPSOC_VID_PLL_CTRL_BASE2528};2529 2530static const u32 gaudi2_pb_pmmu_pll[] = {2531	mmPMMU_MME_PLL_CTRL_BASE,2532	mmPMMU_VID_PLL_CTRL_BASE2533};2534 2535static const u32 gaudi2_pb_xbar_pll[] = {2536	mmDCORE0_XBAR_DMA_PLL_CTRL_BASE,2537	mmDCORE0_XBAR_MMU_PLL_CTRL_BASE,2538	mmDCORE0_XBAR_IF_PLL_CTRL_BASE,2539	mmDCORE0_XBAR_MESH_PLL_CTRL_BASE,2540	mmDCORE1_XBAR_DMA_PLL_CTRL_BASE,2541	mmDCORE1_XBAR_MMU_PLL_CTRL_BASE,2542	mmDCORE1_XBAR_IF_PLL_CTRL_BASE,2543	mmDCORE1_XBAR_MESH_PLL_CTRL_BASE,2544	mmDCORE1_XBAR_HBM_PLL_CTRL_BASE,2545	mmDCORE2_XBAR_DMA_PLL_CTRL_BASE,2546	mmDCORE2_XBAR_MMU_PLL_CTRL_BASE,2547	mmDCORE2_XBAR_IF_PLL_CTRL_BASE,2548	mmDCORE2_XBAR_BANK_PLL_CTRL_BASE,2549	mmDCORE2_XBAR_HBM_PLL_CTRL_BASE,2550	mmDCORE3_XBAR_DMA_PLL_CTRL_BASE,2551	mmDCORE3_XBAR_MMU_PLL_CTRL_BASE,2552	mmDCORE3_XBAR_IF_PLL_CTRL_BASE,2553	mmDCORE3_XBAR_BANK_PLL_CTRL_BASE2554};2555 2556static const u32 gaudi2_pb_xft_pll[] = {2557	mmDCORE0_HBM_PLL_CTRL_BASE,2558	mmDCORE0_TPC_PLL_CTRL_BASE,2559	mmDCORE0_PCI_PLL_CTRL_BASE,2560	mmDCORE1_HBM_PLL_CTRL_BASE,2561	mmDCORE1_TPC_PLL_CTRL_BASE,2562	mmDCORE1_NIC_PLL_CTRL_BASE,2563	mmDCORE2_HBM_PLL_CTRL_BASE,2564	mmDCORE2_TPC_PLL_CTRL_BASE,2565	mmDCORE3_HBM_PLL_CTRL_BASE,2566	mmDCORE3_TPC_PLL_CTRL_BASE,2567	mmDCORE3_NIC_PLL_CTRL_BASE,2568};2569 2570static const u32 gaudi2_pb_pcie[] = {2571	mmPCIE_ELBI_RR_MSTR_IF_RR_SHRD_HBW_BASE,2572	mmPCIE_LBW_RR_MSTR_IF_RR_SHRD_HBW_BASE,2573	mmPCIE_MSTR_RR_MSTR_IF_RR_SHRD_HBW_BASE,2574	mmPCIE_WRAP_BASE,2575};2576 2577static const u32 gaudi2_pb_pcie_unsecured_regs[] = {2578	mmPCIE_WRAP_SPECIAL_GLBL_SPARE_0,2579};2580 2581static const u32 gaudi2_pb_thermal_sensor0[] = {2582	mmDCORE0_XFT_BASE,2583	mmDCORE0_TSTDVS_BASE,2584};2585 2586static const u32 gaudi2_pb_hbm[] = {2587	mmHBM0_MC0_BASE,2588	mmHBM0_MC1_BASE,2589};2590 2591static const u32 gaudi2_pb_mme_qm_arc_acp_eng[] = {2592	mmDCORE0_MME_QM_ARC_ACP_ENG_BASE,2593};2594 2595static const struct range gaudi2_pb_mme_qm_arc_acp_eng_unsecured_regs[] = {2596	{mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_0, mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_DBG_REG},2597};2598 2599struct gaudi2_tpc_pb_data {2600	struct hl_block_glbl_sec *glbl_sec;2601	u32 block_array_size;2602};2603 2604static void gaudi2_config_tpcs_glbl_sec(struct hl_device *hdev, int dcore, int inst, u32 offset,2605						struct iterate_module_ctx *ctx)2606{2607	struct gaudi2_tpc_pb_data *pb_data = ctx->data;2608 2609	hl_config_glbl_sec(hdev, gaudi2_pb_dcr0_tpc0, pb_data->glbl_sec,2610					offset, pb_data->block_array_size);2611}2612 2613static int gaudi2_init_pb_tpc(struct hl_device *hdev)2614{2615	u32 stride, kernel_tensor_stride, qm_tensor_stride, block_array_size;2616	struct gaudi2_tpc_pb_data tpc_pb_data;2617	struct hl_block_glbl_sec *glbl_sec;2618	struct iterate_module_ctx tpc_iter;2619	int i;2620 2621	block_array_size = ARRAY_SIZE(gaudi2_pb_dcr0_tpc0);2622 2623	glbl_sec = kcalloc(block_array_size, sizeof(struct hl_block_glbl_sec), GFP_KERNEL);2624	if (!glbl_sec)2625		return -ENOMEM;2626 2627	kernel_tensor_stride = mmDCORE0_TPC0_CFG_KERNEL_TENSOR_1_BASE -2628				mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_BASE;2629	qm_tensor_stride = mmDCORE0_TPC0_CFG_QM_TENSOR_1_BASE - mmDCORE0_TPC0_CFG_QM_TENSOR_0_BASE;2630 2631	hl_secure_block(hdev, glbl_sec, block_array_size);2632	hl_unsecure_registers(hdev, gaudi2_pb_dcr0_tpc0_unsecured_regs,2633			ARRAY_SIZE(gaudi2_pb_dcr0_tpc0_unsecured_regs),2634			0, gaudi2_pb_dcr0_tpc0, glbl_sec,2635			block_array_size);2636 2637	/* Unsecure all TPC kernel tensors */2638	for (i = 0 ; i < TPC_NUM_OF_KERNEL_TENSORS ; i++)2639		hl_unsecure_registers(hdev,2640			gaudi2_pb_dcr0_tpc0_ktensor_unsecured_regs,2641			ARRAY_SIZE(gaudi2_pb_dcr0_tpc0_ktensor_unsecured_regs),2642			i * kernel_tensor_stride, gaudi2_pb_dcr0_tpc0,2643			glbl_sec, block_array_size);2644 2645	/* Unsecure all TPC QM tensors */2646	for (i = 0 ; i < TPC_NUM_OF_QM_TENSORS ; i++)2647		hl_unsecure_registers(hdev,2648			gaudi2_pb_dcr0_tpc0_qtensor_unsecured_regs,2649			ARRAY_SIZE(gaudi2_pb_dcr0_tpc0_qtensor_unsecured_regs),2650			i * qm_tensor_stride,2651			gaudi2_pb_dcr0_tpc0, glbl_sec, block_array_size);2652 2653	/* unsecure all 32 TPC QM SRF regs */2654	stride = mmDCORE0_TPC0_CFG_QM_SRF_1 - mmDCORE0_TPC0_CFG_QM_SRF_0;2655	for (i = 0 ; i < 32 ; i++)2656		hl_unsecure_register(hdev, mmDCORE0_TPC0_CFG_QM_SRF_0,2657				i * stride, gaudi2_pb_dcr0_tpc0, glbl_sec,2658				block_array_size);2659 2660	/* unsecure the 4 TPC LOCK VALUE regs */2661	stride = mmDCORE0_TPC0_CFG_TPC_LOCK_VALUE_1 - mmDCORE0_TPC0_CFG_TPC_LOCK_VALUE_0;2662	for (i = 0 ; i < 4 ; i++)2663		hl_unsecure_register(hdev, mmDCORE0_TPC0_CFG_TPC_LOCK_VALUE_0,2664				i * stride, gaudi2_pb_dcr0_tpc0, glbl_sec,2665				block_array_size);2666 2667	/* prepare data for TPC iterator */2668	tpc_pb_data.glbl_sec = glbl_sec;2669	tpc_pb_data.block_array_size = block_array_size;2670	tpc_iter.fn = &gaudi2_config_tpcs_glbl_sec;2671	tpc_iter.data = &tpc_pb_data;2672	gaudi2_iterate_tpcs(hdev, &tpc_iter);2673 2674	kfree(glbl_sec);2675 2676	return 0;2677}2678 2679struct gaudi2_tpc_arc_pb_data {2680	u32 unsecured_regs_arr_size;2681	u32 arc_regs_arr_size;2682};2683 2684static void gaudi2_config_tpcs_pb_ranges(struct hl_device *hdev, int dcore, int inst, u32 offset,2685						struct iterate_module_ctx *ctx)2686{2687	struct gaudi2_tpc_arc_pb_data *pb_data = ctx->data;2688 2689	ctx->rc = hl_init_pb_ranges(hdev, HL_PB_SHARED, HL_PB_NA, 1,2690					offset, gaudi2_pb_dcr0_tpc0_arc,2691					pb_data->arc_regs_arr_size,2692					gaudi2_pb_dcr0_tpc0_arc_unsecured_regs,2693					pb_data->unsecured_regs_arr_size);2694}2695 2696static int gaudi2_init_pb_tpc_arc(struct hl_device *hdev)2697{2698	struct gaudi2_tpc_arc_pb_data tpc_arc_pb_data;2699	struct iterate_module_ctx tpc_iter;2700 2701	tpc_arc_pb_data.arc_regs_arr_size = ARRAY_SIZE(gaudi2_pb_dcr0_tpc0_arc);2702	tpc_arc_pb_data.unsecured_regs_arr_size =2703			ARRAY_SIZE(gaudi2_pb_dcr0_tpc0_arc_unsecured_regs);2704 2705	tpc_iter.fn = &gaudi2_config_tpcs_pb_ranges;2706	tpc_iter.data = &tpc_arc_pb_data;2707	gaudi2_iterate_tpcs(hdev, &tpc_iter);2708 2709	return tpc_iter.rc;2710}2711 2712static int gaudi2_init_pb_sm_objs(struct hl_device *hdev)2713{2714	int i, j, glbl_sec_array_len = gaudi2_pb_dcr0_sm_objs.glbl_sec_length;2715	u32 sec_entry, *sec_array, array_base, first_sob, first_mon;2716 2717	array_base = gaudi2_pb_dcr0_sm_objs.mm_block_base_addr +2718				gaudi2_pb_dcr0_sm_objs.glbl_sec_offset;2719 2720	sec_array = kcalloc(glbl_sec_array_len, sizeof(u32), GFP_KERNEL);2721	if (!sec_array)2722		return -ENOMEM;2723 2724	first_sob = GAUDI2_RESERVED_SOB_NUMBER;2725	first_mon = GAUDI2_RESERVED_MON_NUMBER;2726 2727	/* 8192 SOB_OBJs skipping first GAUDI2_MAX_PENDING_CS of them */2728	for (j = i = first_sob ; i < DCORE_NUM_OF_SOB ; i++, j++)2729		UNSET_GLBL_SEC_BIT(sec_array, j);2730 2731	/* 2048 MON_PAY ADDR_L skipping first GAUDI2_MAX_PENDING_CS of them */2732	for (i = first_mon, j += i ; i < DCORE_NUM_OF_MONITORS ; i++, j++)2733		UNSET_GLBL_SEC_BIT(sec_array, j);2734 2735	/* 2048 MON_PAY ADDR_H skipping first GAUDI2_MAX_PENDING_CS of them */2736	for (i = first_mon, j += i ; i < DCORE_NUM_OF_MONITORS ; i++, j++)2737		UNSET_GLBL_SEC_BIT(sec_array, j);2738 2739	/* 2048 MON_PAY DATA skipping first GAUDI2_MAX_PENDING_CS of them */2740	for (i = first_mon, j += i ; i < DCORE_NUM_OF_MONITORS ; i++, j++)2741		UNSET_GLBL_SEC_BIT(sec_array, j);2742 2743	/* 2048 MON_ARM skipping first GAUDI2_MAX_PENDING_CS of them */2744	for (i = first_mon, j += i ; i < DCORE_NUM_OF_MONITORS ; i++, j++)2745		UNSET_GLBL_SEC_BIT(sec_array, j);2746 2747	/* 2048 MON_CONFIG skipping first GAUDI2_MAX_PENDING_CS of them */2748	for (i = first_mon, j += i ; i < DCORE_NUM_OF_MONITORS ; i++, j++)2749		UNSET_GLBL_SEC_BIT(sec_array, j);2750 2751	/* 2048 MON_STATUS skipping first GAUDI2_MAX_PENDING_CS of them */2752	for (i = first_mon, j += i ; i < DCORE_NUM_OF_MONITORS ; i++, j++)2753		UNSET_GLBL_SEC_BIT(sec_array, j);2754 2755	/* Unsecure selected Dcore0 registers */2756	for (i = 0 ; i < glbl_sec_array_len ; i++) {2757		sec_entry = array_base + i * sizeof(u32);2758		WREG32(sec_entry, sec_array[i]);2759	}2760 2761	/* Unsecure Dcore1 - Dcore3 registers */2762	memset(sec_array, -1, glbl_sec_array_len * sizeof(u32));2763 2764	for (i = 1 ; i < NUM_OF_DCORES ; i++) {2765		for (j = 0 ; j < glbl_sec_array_len ; j++) {2766			sec_entry = DCORE_OFFSET * i + array_base + j * sizeof(u32);2767			WREG32(sec_entry, sec_array[j]);2768		}2769	}2770 2771	kfree(sec_array);2772 2773	return 0;2774}2775 2776static void gaudi2_write_lbw_range_register(struct hl_device *hdev, u64 base, void *data)2777{2778	u32 reg_min_offset, reg_max_offset, write_min, write_max;2779	struct rr_config *rr_cfg = (struct rr_config *) data;2780 2781	switch (rr_cfg->type) {2782	case RR_TYPE_SHORT:2783		reg_min_offset = RR_LBW_SEC_RANGE_MIN_SHORT_0_OFFSET;2784		reg_max_offset = RR_LBW_SEC_RANGE_MAX_SHORT_0_OFFSET;2785		break;2786 2787	case RR_TYPE_LONG:2788		reg_min_offset = RR_LBW_SEC_RANGE_MIN_0_OFFSET;2789		reg_max_offset = RR_LBW_SEC_RANGE_MAX_0_OFFSET;2790		break;2791 2792	case RR_TYPE_SHORT_PRIV:2793		reg_min_offset = RR_LBW_PRIV_RANGE_MIN_SHORT_0_OFFSET;2794		reg_max_offset = RR_LBW_PRIV_RANGE_MAX_SHORT_0_OFFSET;2795		break;2796 2797	case RR_TYPE_LONG_PRIV:2798		reg_min_offset = RR_LBW_PRIV_RANGE_MIN_0_OFFSET;2799		reg_max_offset = RR_LBW_PRIV_RANGE_MAX_0_OFFSET;2800		break;2801 2802	default:2803		dev_err(hdev->dev, "Invalid LBW RR type %u\n", rr_cfg->type);2804		return;2805	}2806 2807	reg_min_offset += rr_cfg->index * sizeof(u32);2808	reg_max_offset += rr_cfg->index * sizeof(u32);2809 2810	if (rr_cfg->type == RR_TYPE_SHORT || rr_cfg->type == RR_TYPE_SHORT_PRIV) {2811		write_min = FIELD_GET(RR_LBW_SHORT_MASK, lower_32_bits(rr_cfg->min));2812		write_max = FIELD_GET(RR_LBW_SHORT_MASK, lower_32_bits(rr_cfg->max));2813 2814	} else {2815		write_min = FIELD_GET(RR_LBW_LONG_MASK, lower_32_bits(rr_cfg->min));2816		write_max = FIELD_GET(RR_LBW_LONG_MASK, lower_32_bits(rr_cfg->max));2817	}2818 2819	/* Configure LBW RR:2820	 * Both RR types start blocking from base address 0x1000007FF80000002821	 * SHORT RRs address bits [26:12]2822	 * LONG RRs address bits [26:0]2823	 */2824	WREG32(base + reg_min_offset, write_min);2825	WREG32(base + reg_max_offset, write_max);2826}2827 2828void gaudi2_write_rr_to_all_lbw_rtrs(struct hl_device *hdev, u8 rr_type, u32 rr_index, u64 min_val,2829					u64 max_val)2830{2831	struct dup_block_ctx block_ctx;2832	struct rr_config rr_cfg;2833 2834	if ((rr_type == RR_TYPE_SHORT || rr_type == RR_TYPE_SHORT_PRIV) &&2835								rr_index >= NUM_SHORT_LBW_RR) {2836 2837		dev_err(hdev->dev, "invalid short LBW %s range register index: %u",2838			rr_type == RR_TYPE_SHORT ? "secure" : "privileged", rr_index);2839		return;2840	}2841 2842	if ((rr_type == RR_TYPE_LONG || rr_type == RR_TYPE_LONG_PRIV) &&2843								rr_index >= NUM_LONG_LBW_RR) {2844 2845		dev_err(hdev->dev, "invalid long LBW %s range register index: %u",2846			rr_type == RR_TYPE_LONG ? "secure" : "privileged", rr_index);2847		return;2848	}2849 2850	rr_cfg.type = rr_type;2851	rr_cfg.index = rr_index;2852	rr_cfg.min = min_val;2853	rr_cfg.max = max_val;2854 2855	block_ctx.instance_cfg_fn = &gaudi2_write_lbw_range_register;2856	block_ctx.data = &rr_cfg;2857 2858	/* SFT */2859	block_ctx.base = mmSFT0_LBW_RTR_IF_MSTR_IF_RR_SHRD_LBW_BASE;2860	block_ctx.blocks = NUM_OF_SFT;2861	block_ctx.block_off = SFT_OFFSET;2862	block_ctx.instances = SFT_NUM_OF_LBW_RTR;2863	block_ctx.instance_off = SFT_LBW_RTR_OFFSET;2864	gaudi2_init_blocks(hdev, &block_ctx);2865 2866	/* SIF */2867	block_ctx.base = mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_BASE;2868	block_ctx.blocks = NUM_OF_DCORES;2869	block_ctx.block_off = DCORE_OFFSET;2870	block_ctx.instances = NUM_OF_RTR_PER_DCORE;2871	block_ctx.instance_off = DCORE_RTR_OFFSET;2872	gaudi2_init_blocks(hdev, &block_ctx);2873 2874	block_ctx.blocks = 1;2875	block_ctx.block_off = 0;2876	block_ctx.instances = 1;2877	block_ctx.instance_off = 0;2878 2879	/* PCIE ELBI */2880	block_ctx.base = mmPCIE_ELBI_RR_MSTR_IF_RR_SHRD_LBW_BASE;2881	gaudi2_init_blocks(hdev, &block_ctx);2882 2883	/* PCIE MSTR */2884	block_ctx.base = mmPCIE_MSTR_RR_MSTR_IF_RR_SHRD_LBW_BASE;2885	gaudi2_init_blocks(hdev, &block_ctx);2886 2887	/* PCIE LBW */2888	block_ctx.base = mmPCIE_LBW_RR_MSTR_IF_RR_SHRD_LBW_BASE;2889	gaudi2_init_blocks(hdev, &block_ctx);2890}2891 2892static void gaudi2_init_lbw_range_registers_secure(struct hl_device *hdev)2893{2894	int i;2895 2896	/* Up to 14 14bit-address regs.2897	 *2898	 * - range 0: NIC0_CFG2899	 * - range 1: NIC1_CFG2900	 * - range 2: NIC2_CFG2901	 * - range 3: NIC3_CFG2902	 * - range 4: NIC4_CFG2903	 * - range 5: NIC5_CFG2904	 * - range 6: NIC6_CFG2905	 * - range 7: NIC7_CFG2906	 * - range 8: NIC8_CFG2907	 * - range 9: NIC9_CFG2908	 * - range 10: NIC10_CFG2909	 * - range 11: NIC11_CFG + *_DBG (not including TPC_DBG)2910	 *2911	 * If F/W security is not enabled:2912	 * - ranges 12,13: PSOC_CFG (excluding PSOC_TIMESTAMP, PSOC_EFUSE and PSOC_GLOBAL_CONF)2913	 */2914	u64 lbw_range_min_short[] = {2915		mmNIC0_TX_AXUSER_BASE,2916		mmNIC1_TX_AXUSER_BASE,2917		mmNIC2_TX_AXUSER_BASE,2918		mmNIC3_TX_AXUSER_BASE,2919		mmNIC4_TX_AXUSER_BASE,2920		mmNIC5_TX_AXUSER_BASE,2921		mmNIC6_TX_AXUSER_BASE,2922		mmNIC7_TX_AXUSER_BASE,2923		mmNIC8_TX_AXUSER_BASE,2924		mmNIC9_TX_AXUSER_BASE,2925		mmNIC10_TX_AXUSER_BASE,2926		mmNIC11_TX_AXUSER_BASE,2927		mmPSOC_I2C_M0_BASE,2928		mmPSOC_GPIO0_BASE2929	};2930	u64 lbw_range_max_short[] = {2931		mmNIC0_MAC_CH3_MAC_PCS_BASE + HL_BLOCK_SIZE,2932		mmNIC1_MAC_CH3_MAC_PCS_BASE + HL_BLOCK_SIZE,2933		mmNIC2_MAC_CH3_MAC_PCS_BASE + HL_BLOCK_SIZE,2934		mmNIC3_MAC_CH3_MAC_PCS_BASE + HL_BLOCK_SIZE,2935		mmNIC4_MAC_CH3_MAC_PCS_BASE + HL_BLOCK_SIZE,2936		mmNIC5_MAC_CH3_MAC_PCS_BASE + HL_BLOCK_SIZE,2937		mmNIC6_MAC_CH3_MAC_PCS_BASE + HL_BLOCK_SIZE,2938		mmNIC7_MAC_CH3_MAC_PCS_BASE + HL_BLOCK_SIZE,2939		mmNIC8_MAC_CH3_MAC_PCS_BASE + HL_BLOCK_SIZE,2940		mmNIC9_MAC_CH3_MAC_PCS_BASE + HL_BLOCK_SIZE,2941		mmNIC10_MAC_CH3_MAC_PCS_BASE + HL_BLOCK_SIZE,2942		mmNIC11_DBG_FUNNEL_NCH_BASE + HL_BLOCK_SIZE,2943		mmPSOC_WDOG_BASE + HL_BLOCK_SIZE,2944		mmSVID2_AC_BASE + HL_BLOCK_SIZE2945	};2946 2947	/* Up to 4 26bit-address regs.2948	 *2949	 * - range 0: TPC_DBG2950	 * - range 1: PCIE_DBI.MSIX_DOORBELL_OFF2951	 * - range 2/3: used in soft reset to block access to several blocks and are cleared here2952	 */2953	u64 lbw_range_min_long[] = {2954		mmDCORE0_TPC0_ROM_TABLE_BASE,2955		mmPCIE_DBI_MSIX_DOORBELL_OFF,2956		0x0,2957		0x02958	};2959	u64 lbw_range_max_long[] = {2960		mmDCORE3_TPC5_EML_CS_BASE + HL_BLOCK_SIZE,2961		mmPCIE_DBI_MSIX_DOORBELL_OFF + 0x4,2962		0x0,2963		0x02964	};2965 2966	/* write short range registers to all lbw rtrs */2967	for (i = 0 ; i < ARRAY_SIZE(lbw_range_min_short) ; i++) {2968		if ((lbw_range_min_short[i] == mmPSOC_I2C_M0_BASE ||2969				lbw_range_min_short[i] == mmPSOC_EFUSE_BASE) &&2970				hdev->asic_prop.fw_security_enabled)2971			continue;2972 2973		gaudi2_write_rr_to_all_lbw_rtrs(hdev, RR_TYPE_SHORT, i,2974				lbw_range_min_short[i], lbw_range_max_short[i]);2975	}2976 2977	/* write long range registers to all lbw rtrs */2978	for (i = 0 ; i < ARRAY_SIZE(lbw_range_min_long) ; i++) {2979		gaudi2_write_rr_to_all_lbw_rtrs(hdev, RR_TYPE_LONG, i,2980				lbw_range_min_long[i], lbw_range_max_long[i]);2981	}2982}2983 2984static void gaudi2_init_lbw_range_registers(struct hl_device *hdev)2985{2986	gaudi2_init_lbw_range_registers_secure(hdev);2987}2988 2989static void gaudi2_write_hbw_range_register(struct hl_device *hdev, u64 base, void *data)2990{2991	u32 min_lo_reg_offset, min_hi_reg_offset, max_lo_reg_offset, max_hi_reg_offset;2992	struct rr_config *rr_cfg = (struct rr_config *) data;2993	u64 val_min, val_max;2994 2995	switch (rr_cfg->type) {2996	case RR_TYPE_SHORT:2997		min_lo_reg_offset = RR_SHRD_HBW_SEC_RANGE_MIN_SHORT_LO_0_OFFSET;2998		min_hi_reg_offset = RR_SHRD_HBW_SEC_RANGE_MIN_SHORT_HI_0_OFFSET;2999		max_lo_reg_offset = RR_SHRD_HBW_SEC_RANGE_MAX_SHORT_LO_0_OFFSET;3000		max_hi_reg_offset = RR_SHRD_HBW_SEC_RANGE_MAX_SHORT_HI_0_OFFSET;3001		break;3002 3003	case RR_TYPE_LONG:3004		min_lo_reg_offset = RR_SHRD_HBW_SEC_RANGE_MIN_LO_0_OFFSET;3005		min_hi_reg_offset = RR_SHRD_HBW_SEC_RANGE_MIN_HI_0_OFFSET;3006		max_lo_reg_offset = RR_SHRD_HBW_SEC_RANGE_MAX_LO_0_OFFSET;3007		max_hi_reg_offset = RR_SHRD_HBW_SEC_RANGE_MAX_HI_0_OFFSET;3008		break;3009 3010	case RR_TYPE_SHORT_PRIV:3011		min_lo_reg_offset = RR_SHRD_HBW_PRIV_RANGE_MIN_SHORT_LO_0_OFFSET;3012		min_hi_reg_offset = RR_SHRD_HBW_PRIV_RANGE_MIN_SHORT_HI_0_OFFSET;3013		max_lo_reg_offset = RR_SHRD_HBW_PRIV_RANGE_MAX_SHORT_LO_0_OFFSET;3014		max_hi_reg_offset = RR_SHRD_HBW_PRIV_RANGE_MAX_SHORT_HI_0_OFFSET;3015		break;3016 3017	case RR_TYPE_LONG_PRIV:3018		min_lo_reg_offset = RR_SHRD_HBW_PRIV_RANGE_MIN_LO_0_OFFSET;3019		min_hi_reg_offset = RR_SHRD_HBW_PRIV_RANGE_MIN_HI_0_OFFSET;3020		max_lo_reg_offset = RR_SHRD_HBW_PRIV_RANGE_MAX_LO_0_OFFSET;3021		max_hi_reg_offset = RR_SHRD_HBW_PRIV_RANGE_MAX_HI_0_OFFSET;3022		break;3023 3024	default:3025		dev_err(hdev->dev, "Invalid HBW RR type %u\n", rr_cfg->type);3026		return;3027	}3028 3029	min_lo_reg_offset += rr_cfg->index * sizeof(u32);3030	min_hi_reg_offset += rr_cfg->index * sizeof(u32);3031	max_lo_reg_offset += rr_cfg->index * sizeof(u32);3032	max_hi_reg_offset += rr_cfg->index * sizeof(u32);3033 3034	if (rr_cfg->type == RR_TYPE_SHORT || rr_cfg->type == RR_TYPE_SHORT_PRIV) {3035		val_min = FIELD_GET(RR_HBW_SHORT_HI_MASK, rr_cfg->min) |3036				FIELD_GET(RR_HBW_SHORT_LO_MASK, rr_cfg->min);3037		val_max = FIELD_GET(RR_HBW_SHORT_HI_MASK, rr_cfg->max) |3038				FIELD_GET(RR_HBW_SHORT_LO_MASK, rr_cfg->max);3039	} else {3040		val_min = FIELD_GET(RR_HBW_LONG_HI_MASK, rr_cfg->min) |3041				FIELD_GET(RR_HBW_LONG_LO_MASK, rr_cfg->min);3042		val_max = FIELD_GET(RR_HBW_LONG_HI_MASK, rr_cfg->max) |3043				FIELD_GET(RR_HBW_LONG_LO_MASK, rr_cfg->max);3044	}3045 3046	/* Configure HBW RR:3047	 * SHORT RRs (0x1000_<36bits>000) - HI: address bits [47:44], LO: address bits [43:12]3048	 * LONG  RRs (0x<52bits>000)      - HI: address bits [63:44], LO: address bits [43:12]3049	 */3050	WREG32(base + min_lo_reg_offset, lower_32_bits(val_min));3051	WREG32(base + min_hi_reg_offset, upper_32_bits(val_min));3052	WREG32(base + max_lo_reg_offset, lower_32_bits(val_max));3053	WREG32(base + max_hi_reg_offset, upper_32_bits(val_max));3054}3055 3056static void gaudi2_write_hbw_rr_to_all_mstr_if(struct hl_device *hdev, u8 rr_type, u32 rr_index,3057						u64 min_val, u64 max_val)3058{3059	struct dup_block_ctx block_ctx;3060	struct rr_config rr_cfg;3061 3062	if ((rr_type == RR_TYPE_SHORT || rr_type == RR_TYPE_SHORT_PRIV) &&3063								rr_index >= NUM_SHORT_HBW_RR) {3064 3065		dev_err(hdev->dev, "invalid short HBW %s range register index: %u",3066			rr_type == RR_TYPE_SHORT ? "secure" : "privileged", rr_index);3067		return;3068	}3069 3070	if ((rr_type == RR_TYPE_LONG || rr_type == RR_TYPE_LONG_PRIV) &&3071								rr_index >= NUM_LONG_HBW_RR) {3072 3073		dev_err(hdev->dev, "invalid long HBW %s range register index: %u",3074			rr_type == RR_TYPE_LONG ? "secure" : "privileged", rr_index);3075		return;3076	}3077 3078	rr_cfg.type = rr_type;3079	rr_cfg.index = rr_index;3080	rr_cfg.min = min_val;3081	rr_cfg.max = max_val;3082 3083	block_ctx.instance_cfg_fn = &gaudi2_write_hbw_range_register;3084	block_ctx.data = &rr_cfg;3085 3086	/* SFT */3087	block_ctx.base = mmSFT0_HBW_RTR_IF0_MSTR_IF_RR_SHRD_HBW_BASE;3088	block_ctx.blocks = NUM_OF_SFT;3089	block_ctx.block_off = SFT_OFFSET;3090	block_ctx.instances = SFT_NUM_OF_HBW_RTR;3091	block_ctx.instance_off = SFT_IF_RTR_OFFSET;3092	gaudi2_init_blocks(hdev, &block_ctx);3093 3094	/* SIF */3095	block_ctx.base = mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE;3096	block_ctx.blocks = NUM_OF_DCORES;3097	block_ctx.block_off = DCORE_OFFSET;3098	block_ctx.instances = NUM_OF_RTR_PER_DCORE;3099	block_ctx.instance_off = DCORE_RTR_OFFSET;3100	gaudi2_init_blocks(hdev, &block_ctx);3101 3102	/* PCIE MSTR */3103	block_ctx.base = mmPCIE_MSTR_RR_MSTR_IF_RR_SHRD_HBW_BASE;3104	block_ctx.blocks = 1;3105	block_ctx.block_off = 0;3106	block_ctx.instances = 1;3107	block_ctx.instance_off = 0;3108	gaudi2_init_blocks(hdev, &block_ctx);3109}3110 3111static void gaudi2_init_hbw_range_registers(struct hl_device *hdev)3112{3113	int i;3114 3115	/* Up to 6 short RR (0x1000_<36bits>000) and 4 long RR (0x<52bits>000).3116	 *3117	 * - short range 0:3118	 *	SPI Flash, ARC0/1 ICCM/DCCM, Secure Boot ROM, PSOC_FW/Scratchpad/PCIE_FW SRAM3119	 */3120	u64 hbw_range_min_short[] = {3121		SPI_FLASH_BASE_ADDR3122	};3123	u64 hbw_range_max_short[] = {3124		PCIE_FW_SRAM_ADDR + PCIE_FW_SRAM_SIZE3125	};3126 3127	for (i = 0 ; i < ARRAY_SIZE(hbw_range_min_short) ; i++) {3128		gaudi2_write_hbw_rr_to_all_mstr_if(hdev, RR_TYPE_SHORT, i, hbw_range_min_short[i],3129							hbw_range_max_short[i]);3130	}3131}3132 3133static void gaudi2_write_mmu_range_register(struct hl_device *hdev, u64 base,3134						struct rr_config *rr_cfg)3135{3136	u32 min_lo_reg_offset, min_hi_reg_offset, max_lo_reg_offset, max_hi_reg_offset;3137 3138	switch (rr_cfg->type) {3139	case RR_TYPE_LONG:3140		min_lo_reg_offset = MMU_RR_SEC_MIN_31_0_0_OFFSET;3141		min_hi_reg_offset = MMU_RR_SEC_MIN_63_32_0_OFFSET;3142		max_lo_reg_offset = MMU_RR_SEC_MAX_31_0_0_OFFSET;3143		max_hi_reg_offset = MMU_RR_SEC_MAX_63_32_0_OFFSET;3144		break;3145 3146	case RR_TYPE_LONG_PRIV:3147		min_lo_reg_offset = MMU_RR_PRIV_MIN_31_0_0_OFFSET;3148		min_hi_reg_offset = MMU_RR_PRIV_MIN_63_32_0_OFFSET;3149		max_lo_reg_offset = MMU_RR_PRIV_MAX_31_0_0_OFFSET;3150		max_hi_reg_offset = MMU_RR_PRIV_MAX_63_32_0_OFFSET;3151		break;3152 3153	default:3154		dev_err(hdev->dev, "Invalid MMU RR type %u\n", rr_cfg->type);3155		return;3156	}3157 3158	min_lo_reg_offset += rr_cfg->index * sizeof(u32);3159	min_hi_reg_offset += rr_cfg->index * sizeof(u32);3160	max_lo_reg_offset += rr_cfg->index * sizeof(u32);3161	max_hi_reg_offset += rr_cfg->index * sizeof(u32);3162 3163	/* Configure MMU RR (address bits [63:0]) */3164	WREG32(base + min_lo_reg_offset, lower_32_bits(rr_cfg->min));3165	WREG32(base + min_hi_reg_offset, upper_32_bits(rr_cfg->min));3166	WREG32(base + max_lo_reg_offset, lower_32_bits(rr_cfg->max));3167	WREG32(base + max_hi_reg_offset, upper_32_bits(rr_cfg->max));3168}3169 3170static void gaudi2_init_mmu_range_registers(struct hl_device *hdev)3171{3172	u32 dcore_id, hmmu_id, hmmu_base;3173	struct rr_config rr_cfg;3174 3175	/* Up to 8 ranges [63:0].3176	 *3177	 * - range 0: Reserved HBM area for F/W and driver3178	 */3179 3180	/* The RRs are located after the HMMU so need to use the scrambled addresses */3181	rr_cfg.min = hdev->asic_funcs->scramble_addr(hdev, DRAM_PHYS_BASE);3182	rr_cfg.max = hdev->asic_funcs->scramble_addr(hdev, hdev->asic_prop.dram_user_base_address);3183	rr_cfg.index = 0;3184	rr_cfg.type = RR_TYPE_LONG;3185 3186	for (dcore_id = 0 ; dcore_id < NUM_OF_DCORES ; dcore_id++) {3187		for (hmmu_id = 0 ; hmmu_id < NUM_OF_HMMU_PER_DCORE; hmmu_id++) {3188			if (!gaudi2_is_hmmu_enabled(hdev, dcore_id, hmmu_id))3189				continue;3190 3191			hmmu_base = mmDCORE0_HMMU0_MMU_BASE + dcore_id * DCORE_OFFSET +3192					hmmu_id * DCORE_HMMU_OFFSET;3193 3194			gaudi2_write_mmu_range_register(hdev, hmmu_base, &rr_cfg);3195		}3196	}3197}3198 3199/**3200 * gaudi2_init_range_registers -3201 * Initialize range registers of all initiators3202 *3203 * @hdev: pointer to hl_device structure3204 */3205static void gaudi2_init_range_registers(struct hl_device *hdev)3206{3207	gaudi2_init_lbw_range_registers(hdev);3208	gaudi2_init_hbw_range_registers(hdev);3209	gaudi2_init_mmu_range_registers(hdev);3210}3211 3212/**3213 * gaudi2_init_protection_bits -3214 * Initialize protection bits of specific registers3215 *3216 * @hdev: pointer to hl_device structure3217 *3218 * All protection bits are 1 by default, means not protected. Need to set to 03219 * each bit that belongs to a protected register.3220 *3221 */3222static int gaudi2_init_protection_bits(struct hl_device *hdev)3223{3224	u32 *user_regs_array = NULL, user_regs_array_size = 0, engine_core_intr_reg;3225	struct asic_fixed_properties *prop = &hdev->asic_prop;3226	u32 instance_offset;3227	int rc = 0;3228	u8 i;3229 3230	/* SFT */3231	instance_offset = mmSFT1_HBW_RTR_IF0_RTR_CTRL_BASE - mmSFT0_HBW_RTR_IF0_RTR_CTRL_BASE;3232	rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA, 4, instance_offset,3233			gaudi2_pb_sft0, ARRAY_SIZE(gaudi2_pb_sft0),3234			NULL, HL_PB_NA);3235 3236	/* HIF */3237	instance_offset = mmDCORE0_HIF1_BASE - mmDCORE0_HIF0_BASE;3238	rc |= hl_init_pb_with_mask(hdev, NUM_OF_DCORES, DCORE_OFFSET,3239			NUM_OF_HIF_PER_DCORE, instance_offset,3240			gaudi2_pb_dcr0_hif, ARRAY_SIZE(gaudi2_pb_dcr0_hif),3241			NULL, HL_PB_NA, prop->hmmu_hif_enabled_mask);3242 3243	/* RTR */3244	instance_offset = mmDCORE0_RTR1_CTRL_BASE - mmDCORE0_RTR0_CTRL_BASE;3245	rc |= hl_init_pb(hdev, NUM_OF_DCORES, DCORE_OFFSET, 8, instance_offset,3246			gaudi2_pb_dcr0_rtr0, ARRAY_SIZE(gaudi2_pb_dcr0_rtr0),3247			NULL, HL_PB_NA);3248 3249	/* HMMU */3250	rc |= hl_init_pb_with_mask(hdev, NUM_OF_DCORES, DCORE_OFFSET,3251			NUM_OF_HMMU_PER_DCORE, DCORE_HMMU_OFFSET,3252			gaudi2_pb_dcr0_hmmu0, ARRAY_SIZE(gaudi2_pb_dcr0_hmmu0),3253			NULL, HL_PB_NA, prop->hmmu_hif_enabled_mask);3254 3255	/* CPU.3256	 * Except for CPU_IF, skip when security is enabled in F/W, because the blocks are protected3257	 * by privileged RR.3258	 */3259	rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA,3260			HL_PB_SINGLE_INSTANCE, HL_PB_NA,3261			gaudi2_pb_cpu_if, ARRAY_SIZE(gaudi2_pb_cpu_if),3262			NULL, HL_PB_NA);3263 3264	if (!hdev->asic_prop.fw_security_enabled)3265		rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA,3266				HL_PB_SINGLE_INSTANCE, HL_PB_NA,3267				gaudi2_pb_cpu, ARRAY_SIZE(gaudi2_pb_cpu),3268				NULL, HL_PB_NA);3269 3270	/* KDMA */3271	rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA,3272			HL_PB_SINGLE_INSTANCE, HL_PB_NA,3273			gaudi2_pb_kdma, ARRAY_SIZE(gaudi2_pb_kdma),3274			NULL, HL_PB_NA);3275 3276	/* PDMA */3277	instance_offset = mmPDMA1_CORE_BASE - mmPDMA0_CORE_BASE;3278	rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA, 2, instance_offset,3279			gaudi2_pb_pdma0, ARRAY_SIZE(gaudi2_pb_pdma0),3280			gaudi2_pb_pdma0_unsecured_regs,3281			ARRAY_SIZE(gaudi2_pb_pdma0_unsecured_regs));3282 3283	/* ARC PDMA */3284	rc |= hl_init_pb_ranges(hdev, HL_PB_SHARED, HL_PB_NA, 2,3285			instance_offset, gaudi2_pb_pdma0_arc,3286			ARRAY_SIZE(gaudi2_pb_pdma0_arc),3287			gaudi2_pb_pdma0_arc_unsecured_regs,3288			ARRAY_SIZE(gaudi2_pb_pdma0_arc_unsecured_regs));3289 3290	/* EDMA */3291	instance_offset = mmDCORE0_EDMA1_CORE_BASE - mmDCORE0_EDMA0_CORE_BASE;3292	rc |= hl_init_pb_with_mask(hdev, NUM_OF_DCORES, DCORE_OFFSET, 2,3293			instance_offset, gaudi2_pb_dcr0_edma0,3294			ARRAY_SIZE(gaudi2_pb_dcr0_edma0),3295			gaudi2_pb_dcr0_edma0_unsecured_regs,3296			ARRAY_SIZE(gaudi2_pb_dcr0_edma0_unsecured_regs),3297			prop->edma_enabled_mask);3298 3299	/* ARC EDMA */3300	rc |= hl_init_pb_ranges_with_mask(hdev, NUM_OF_DCORES, DCORE_OFFSET, 2,3301			instance_offset, gaudi2_pb_dcr0_edma0_arc,3302			ARRAY_SIZE(gaudi2_pb_dcr0_edma0_arc),3303			gaudi2_pb_dcr0_edma0_arc_unsecured_regs,3304			ARRAY_SIZE(gaudi2_pb_dcr0_edma0_arc_unsecured_regs),3305			prop->edma_enabled_mask);3306 3307	/* MME */3308	instance_offset = mmDCORE0_MME_SBTE1_BASE - mmDCORE0_MME_SBTE0_BASE;3309 3310	for (i = 0 ; i < NUM_OF_DCORES * NUM_OF_MME_PER_DCORE ; i++) {3311		/* MME SBTE */3312		rc |= hl_init_pb_single_dcore(hdev, (DCORE_OFFSET * i), 5,3313				instance_offset, gaudi2_pb_dcr0_mme_sbte,3314				ARRAY_SIZE(gaudi2_pb_dcr0_mme_sbte), NULL,3315				HL_PB_NA);3316 3317		/* MME */3318		rc |= hl_init_pb_single_dcore(hdev, (DCORE_OFFSET * i),3319				HL_PB_SINGLE_INSTANCE, HL_PB_NA,3320				gaudi2_pb_dcr0_mme_eng,3321				ARRAY_SIZE(gaudi2_pb_dcr0_mme_eng),3322				gaudi2_pb_dcr0_mme_eng_unsecured_regs,3323				ARRAY_SIZE(gaudi2_pb_dcr0_mme_eng_unsecured_regs));3324	}3325 3326	/*3327	 * we have special iteration for case in which we would like to3328	 * configure stubbed MME's ARC/QMAN3329	 */3330	for (i = 0 ; i < NUM_OF_DCORES * NUM_OF_MME_PER_DCORE ; i++) {3331		/* MME QM */3332		rc |= hl_init_pb_single_dcore(hdev, (DCORE_OFFSET * i),3333				HL_PB_SINGLE_INSTANCE, HL_PB_NA,3334				gaudi2_pb_dcr0_mme_qm,3335				ARRAY_SIZE(gaudi2_pb_dcr0_mme_qm),3336				gaudi2_pb_dcr0_mme_qm_unsecured_regs,3337				ARRAY_SIZE(gaudi2_pb_dcr0_mme_qm_unsecured_regs));3338 3339		/* ARC MME */3340		rc |= hl_init_pb_ranges_single_dcore(hdev, (DCORE_OFFSET * i),3341			HL_PB_SINGLE_INSTANCE, HL_PB_NA,3342			gaudi2_pb_dcr0_mme_arc,3343			ARRAY_SIZE(gaudi2_pb_dcr0_mme_arc),3344			gaudi2_pb_dcr0_mme_arc_unsecured_regs,3345			ARRAY_SIZE(gaudi2_pb_dcr0_mme_arc_unsecured_regs));3346	}3347 3348	/* MME QM ARC ACP ENG */3349	rc |= hl_init_pb_ranges_with_mask(hdev, NUM_OF_DCORES, DCORE_OFFSET,3350			HL_PB_SINGLE_INSTANCE, HL_PB_NA,3351			gaudi2_pb_mme_qm_arc_acp_eng,3352			ARRAY_SIZE(gaudi2_pb_mme_qm_arc_acp_eng),3353			gaudi2_pb_mme_qm_arc_acp_eng_unsecured_regs,3354			ARRAY_SIZE(gaudi2_pb_mme_qm_arc_acp_eng_unsecured_regs),3355			(BIT(NUM_OF_DCORES * NUM_OF_MME_PER_DCORE) - 1));3356 3357	/* TPC */3358	rc |= gaudi2_init_pb_tpc(hdev);3359	rc |= gaudi2_init_pb_tpc_arc(hdev);3360 3361	/* SRAM */3362	instance_offset = mmDCORE0_SRAM1_BANK_BASE - mmDCORE0_SRAM0_BANK_BASE;3363	rc |= hl_init_pb(hdev, NUM_OF_DCORES, DCORE_OFFSET, 8, instance_offset,3364			gaudi2_pb_dcr0_sram0, ARRAY_SIZE(gaudi2_pb_dcr0_sram0),3365			NULL, HL_PB_NA);3366 3367	/* Sync Manager MSTR IF */3368	rc |= hl_init_pb(hdev, NUM_OF_DCORES, DCORE_OFFSET,3369			HL_PB_SINGLE_INSTANCE, HL_PB_NA,3370			gaudi2_pb_dcr0_sm_mstr_if,3371			ARRAY_SIZE(gaudi2_pb_dcr0_sm_mstr_if),3372			NULL, HL_PB_NA);3373 3374	/* Sync Manager GLBL */3375 3376	/* Secure Dcore0 CQ0 registers */3377	rc |= hl_init_pb_ranges(hdev, HL_PB_SHARED, HL_PB_NA,3378			HL_PB_SINGLE_INSTANCE, HL_PB_NA,3379			gaudi2_pb_dcr0_sm_glbl,3380			ARRAY_SIZE(gaudi2_pb_dcr0_sm_glbl),3381			gaudi2_pb_dcr0_sm_glbl_unsecured_regs,3382			ARRAY_SIZE(gaudi2_pb_dcr0_sm_glbl_unsecured_regs));3383 3384	/* Unsecure all other CQ registers */3385	rc |= hl_init_pb_ranges(hdev, NUM_OF_DCORES - 1, DCORE_OFFSET,3386			HL_PB_SINGLE_INSTANCE, HL_PB_NA,3387			gaudi2_pb_dcr1_sm_glbl,3388			ARRAY_SIZE(gaudi2_pb_dcr1_sm_glbl),3389			gaudi2_pb_dcr_x_sm_glbl_unsecured_regs,3390			ARRAY_SIZE(gaudi2_pb_dcr_x_sm_glbl_unsecured_regs));3391 3392	/* PSOC.3393	 * Except for PSOC_GLOBAL_CONF, skip when security is enabled in F/W, because the blocks are3394	 * protected by privileged RR.3395	 * For PSOC_GLOBAL_CONF, need to un-secure the scratchpad register which is used for engine3396	 * cores to raise events towards F/W.3397	 */3398	engine_core_intr_reg = (u32) (hdev->asic_prop.engine_core_interrupt_reg_addr - CFG_BASE);3399	if (engine_core_intr_reg >= mmPSOC_GLOBAL_CONF_SCRATCHPAD_0 &&3400			engine_core_intr_reg <= mmPSOC_GLOBAL_CONF_SCRATCHPAD_31) {3401		user_regs_array = &engine_core_intr_reg;3402		user_regs_array_size = 1;3403	} else {3404		dev_err(hdev->dev,3405			"Engine cores register for interrupts (%#x) is not a PSOC scratchpad register\n",3406			engine_core_intr_reg);3407	}3408 3409	rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA,3410			HL_PB_SINGLE_INSTANCE, HL_PB_NA,3411			gaudi2_pb_psoc_global_conf, ARRAY_SIZE(gaudi2_pb_psoc_global_conf),3412			user_regs_array, user_regs_array_size);3413 3414	if (!hdev->asic_prop.fw_security_enabled)3415		rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA,3416				HL_PB_SINGLE_INSTANCE, HL_PB_NA,3417				gaudi2_pb_psoc, ARRAY_SIZE(gaudi2_pb_psoc),3418				NULL, HL_PB_NA);3419 3420	/* PMMU */3421	rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA,3422			HL_PB_SINGLE_INSTANCE, HL_PB_NA,3423			gaudi2_pb_pmmu, ARRAY_SIZE(gaudi2_pb_pmmu),3424			NULL, HL_PB_NA);3425 3426	/* PLL.3427	 * Skip PSOC/XFT PLL when security is enabled in F/W, because these blocks are protected by3428	 * privileged RR.3429	 */3430	rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA,3431			HL_PB_SINGLE_INSTANCE, HL_PB_NA,3432			gaudi2_pb_pmmu_pll, ARRAY_SIZE(gaudi2_pb_pmmu_pll),3433			NULL, HL_PB_NA);3434	rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA,3435			HL_PB_SINGLE_INSTANCE, HL_PB_NA,3436			gaudi2_pb_xbar_pll, ARRAY_SIZE(gaudi2_pb_xbar_pll),3437			NULL, HL_PB_NA);3438 3439	if (!hdev->asic_prop.fw_security_enabled) {3440		rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA,3441				HL_PB_SINGLE_INSTANCE, HL_PB_NA,3442				gaudi2_pb_psoc_pll, ARRAY_SIZE(gaudi2_pb_psoc_pll),3443				NULL, HL_PB_NA);3444		rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA,3445				HL_PB_SINGLE_INSTANCE, HL_PB_NA,3446				gaudi2_pb_xft_pll, ARRAY_SIZE(gaudi2_pb_xft_pll),3447				NULL, HL_PB_NA);3448	}3449 3450	/* PCIE */3451	rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA,3452			HL_PB_SINGLE_INSTANCE, HL_PB_NA,3453			gaudi2_pb_pcie, ARRAY_SIZE(gaudi2_pb_pcie),3454			gaudi2_pb_pcie_unsecured_regs,3455			ARRAY_SIZE(gaudi2_pb_pcie_unsecured_regs));3456 3457	/* Thermal Sensor.3458	 * Skip when security is enabled in F/W, because the blocks are protected by privileged RR.3459	 */3460	if (!hdev->asic_prop.fw_security_enabled) {3461		instance_offset = mmDCORE1_XFT_BASE - mmDCORE0_XFT_BASE;3462		rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA, 4, instance_offset,3463				gaudi2_pb_thermal_sensor0,3464				ARRAY_SIZE(gaudi2_pb_thermal_sensor0), NULL, HL_PB_NA);3465	}3466 3467	/* Scheduler ARCs */3468	instance_offset = mmARC_FARM_ARC1_AUX_BASE - mmARC_FARM_ARC0_AUX_BASE;3469	rc |= hl_init_pb_ranges(hdev, HL_PB_SHARED, HL_PB_NA,3470			NUM_OF_ARC_FARMS_ARC,3471			instance_offset, gaudi2_pb_arc_sched,3472			ARRAY_SIZE(gaudi2_pb_arc_sched),3473			gaudi2_pb_arc_sched_unsecured_regs,3474			ARRAY_SIZE(gaudi2_pb_arc_sched_unsecured_regs));3475 3476	/* XBAR MIDs */3477	instance_offset = mmXBAR_MID_1_BASE - mmXBAR_MID_0_BASE;3478	rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA, NUM_OF_XBAR,3479			instance_offset, gaudi2_pb_xbar_mid,3480			ARRAY_SIZE(gaudi2_pb_xbar_mid),3481			gaudi2_pb_xbar_mid_unsecured_regs,3482			ARRAY_SIZE(gaudi2_pb_xbar_mid_unsecured_regs));3483 3484	/* XBAR EDGEs */3485	instance_offset = mmXBAR_EDGE_1_BASE - mmXBAR_EDGE_0_BASE;3486	rc |= hl_init_pb_with_mask(hdev, HL_PB_SHARED, HL_PB_NA, NUM_OF_XBAR,3487			instance_offset, gaudi2_pb_xbar_edge,3488			ARRAY_SIZE(gaudi2_pb_xbar_edge),3489			gaudi2_pb_xbar_edge_unsecured_regs,3490			ARRAY_SIZE(gaudi2_pb_xbar_edge_unsecured_regs),3491			prop->xbar_edge_enabled_mask);3492 3493	/* NIC */3494	rc |= hl_init_pb_with_mask(hdev, NIC_NUMBER_OF_MACROS, NIC_OFFSET,3495			HL_PB_SINGLE_INSTANCE, HL_PB_NA,3496			gaudi2_pb_nic0, ARRAY_SIZE(gaudi2_pb_nic0),3497			NULL, HL_PB_NA, hdev->nic_ports_mask);3498 3499	/* NIC QM and QPC */3500	rc |= hl_init_pb_with_mask(hdev, NIC_NUMBER_OF_MACROS, NIC_OFFSET,3501			NIC_NUMBER_OF_QM_PER_MACRO, NIC_QM_OFFSET,3502			gaudi2_pb_nic0_qm_qpc, ARRAY_SIZE(gaudi2_pb_nic0_qm_qpc),3503			gaudi2_pb_nic0_qm_qpc_unsecured_regs,3504			ARRAY_SIZE(gaudi2_pb_nic0_qm_qpc_unsecured_regs),3505			hdev->nic_ports_mask);3506 3507	/* NIC QM ARC */3508	rc |= hl_init_pb_ranges_with_mask(hdev, NIC_NUMBER_OF_MACROS,3509			NIC_OFFSET, NIC_NUMBER_OF_QM_PER_MACRO, NIC_QM_OFFSET,3510			gaudi2_pb_nic0_qm_arc_aux0,3511			ARRAY_SIZE(gaudi2_pb_nic0_qm_arc_aux0),3512			gaudi2_pb_nic0_qm_arc_aux0_unsecured_regs,3513			ARRAY_SIZE(gaudi2_pb_nic0_qm_arc_aux0_unsecured_regs),3514			hdev->nic_ports_mask);3515 3516	/* NIC UMR */3517	rc |= hl_init_pb_ranges_with_mask(hdev, NIC_NUMBER_OF_MACROS,3518			NIC_OFFSET, NIC_NUMBER_OF_QM_PER_MACRO, NIC_QM_OFFSET,3519			gaudi2_pb_nic0_umr,3520			ARRAY_SIZE(gaudi2_pb_nic0_umr),3521			gaudi2_pb_nic0_umr_unsecured_regs,3522			ARRAY_SIZE(gaudi2_pb_nic0_umr_unsecured_regs),3523			hdev->nic_ports_mask);3524 3525	/* Rotators */3526	instance_offset = mmROT1_BASE - mmROT0_BASE;3527	rc |= hl_init_pb_with_mask(hdev, HL_PB_SHARED, HL_PB_NA, NUM_OF_ROT,3528			instance_offset, gaudi2_pb_rot0,3529			ARRAY_SIZE(gaudi2_pb_rot0),3530			gaudi2_pb_rot0_unsecured_regs,3531			ARRAY_SIZE(gaudi2_pb_rot0_unsecured_regs),3532			(BIT(NUM_OF_ROT) - 1));3533 3534	/* Rotators ARCS */3535	rc |= hl_init_pb_ranges_with_mask(hdev, HL_PB_SHARED,3536			HL_PB_NA, NUM_OF_ROT, instance_offset,3537			gaudi2_pb_rot0_arc, ARRAY_SIZE(gaudi2_pb_rot0_arc),3538			gaudi2_pb_rot0_arc_unsecured_regs,3539			ARRAY_SIZE(gaudi2_pb_rot0_arc_unsecured_regs),3540			(BIT(NUM_OF_ROT) - 1));3541 3542	rc |= gaudi2_init_pb_sm_objs(hdev);3543 3544	return rc;3545}3546 3547/**3548 * gaudi2_init_security - Initialize security model3549 *3550 * @hdev: pointer to hl_device structure3551 *3552 * Initialize the security model of the device3553 * That includes range registers and protection bit per register.3554 */3555int gaudi2_init_security(struct hl_device *hdev)3556{3557	int rc;3558 3559	rc = gaudi2_init_protection_bits(hdev);3560	if (rc)3561		return rc;3562 3563	gaudi2_init_range_registers(hdev);3564 3565	return 0;3566}3567 3568struct gaudi2_ack_pb_tpc_data {3569	u32 tpc_regs_array_size;3570	u32 arc_tpc_regs_array_size;3571};3572 3573static void gaudi2_ack_pb_tpc_config(struct hl_device *hdev, int dcore, int inst, u32 offset,3574					struct iterate_module_ctx *ctx)3575{3576	struct gaudi2_ack_pb_tpc_data *pb_data = ctx->data;3577 3578	hl_ack_pb_single_dcore(hdev, offset, HL_PB_SINGLE_INSTANCE, HL_PB_NA,3579				gaudi2_pb_dcr0_tpc0, pb_data->tpc_regs_array_size);3580 3581	hl_ack_pb_single_dcore(hdev, offset, HL_PB_SINGLE_INSTANCE, HL_PB_NA,3582				gaudi2_pb_dcr0_tpc0_arc, pb_data->arc_tpc_regs_array_size);3583}3584 3585static void gaudi2_ack_pb_tpc(struct hl_device *hdev)3586{3587	struct iterate_module_ctx tpc_iter = {3588		.fn = &gaudi2_ack_pb_tpc_config,3589	};3590	struct gaudi2_ack_pb_tpc_data data;3591 3592	data.tpc_regs_array_size = ARRAY_SIZE(gaudi2_pb_dcr0_tpc0);3593	data.arc_tpc_regs_array_size = ARRAY_SIZE(gaudi2_pb_dcr0_tpc0_arc);3594	tpc_iter.data = &data;3595 3596	gaudi2_iterate_tpcs(hdev, &tpc_iter);3597}3598 3599/**3600 * gaudi2_ack_protection_bits_errors - scan all blocks having protection bits3601 * and for every protection error found, display the appropriate error message3602 * and clear the error.3603 *3604 * @hdev: pointer to hl_device structure3605 *3606 * All protection bits are 1 by default, means not protected. Need to set to 03607 * each bit that belongs to a protected register.3608 *3609 */3610void gaudi2_ack_protection_bits_errors(struct hl_device *hdev)3611{3612	struct asic_fixed_properties *prop = &hdev->asic_prop;3613	u32 instance_offset;3614	u8 i;3615 3616	/* SFT */3617	instance_offset = mmSFT1_HBW_RTR_IF0_RTR_CTRL_BASE - mmSFT0_HBW_RTR_IF0_RTR_CTRL_BASE;3618	hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, 4, instance_offset,3619			gaudi2_pb_sft0, ARRAY_SIZE(gaudi2_pb_sft0));3620 3621	/* HIF */3622	instance_offset = mmDCORE0_HIF1_BASE - mmDCORE0_HIF0_BASE;3623	hl_ack_pb_with_mask(hdev, NUM_OF_DCORES, DCORE_OFFSET,3624			NUM_OF_HIF_PER_DCORE, instance_offset,3625			gaudi2_pb_dcr0_hif, ARRAY_SIZE(gaudi2_pb_dcr0_hif),3626			prop->hmmu_hif_enabled_mask);3627 3628	/* RTR */3629	instance_offset = mmDCORE0_RTR1_CTRL_BASE - mmDCORE0_RTR0_CTRL_BASE;3630	hl_ack_pb(hdev, NUM_OF_DCORES, DCORE_OFFSET, 8, instance_offset,3631			gaudi2_pb_dcr0_rtr0, ARRAY_SIZE(gaudi2_pb_dcr0_rtr0));3632 3633	/* HMMU */3634	hl_ack_pb_with_mask(hdev, NUM_OF_DCORES, DCORE_OFFSET,3635			NUM_OF_HMMU_PER_DCORE, DCORE_HMMU_OFFSET,3636			gaudi2_pb_dcr0_hmmu0, ARRAY_SIZE(gaudi2_pb_dcr0_hmmu0),3637			prop->hmmu_hif_enabled_mask);3638 3639	/* CPU.3640	 * Except for CPU_IF, skip when security is enabled in F/W, because the blocks are protected3641	 * by privileged RR.3642	 */3643	hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, HL_PB_SINGLE_INSTANCE, HL_PB_NA,3644			gaudi2_pb_cpu_if, ARRAY_SIZE(gaudi2_pb_cpu_if));3645	if (!hdev->asic_prop.fw_security_enabled)3646		hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, HL_PB_SINGLE_INSTANCE, HL_PB_NA,3647				gaudi2_pb_cpu, ARRAY_SIZE(gaudi2_pb_cpu));3648 3649	/* KDMA */3650	hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, HL_PB_SINGLE_INSTANCE, HL_PB_NA,3651			gaudi2_pb_kdma, ARRAY_SIZE(gaudi2_pb_kdma));3652 3653	/* PDMA */3654	instance_offset = mmPDMA1_CORE_BASE - mmPDMA0_CORE_BASE;3655	hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, 2, instance_offset,3656			gaudi2_pb_pdma0, ARRAY_SIZE(gaudi2_pb_pdma0));3657 3658	/* ARC PDMA */3659	hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, 2, instance_offset,3660			gaudi2_pb_pdma0_arc, ARRAY_SIZE(gaudi2_pb_pdma0_arc));3661 3662	/* EDMA */3663	instance_offset = mmDCORE0_EDMA1_CORE_BASE - mmDCORE0_EDMA0_CORE_BASE;3664	hl_ack_pb_with_mask(hdev, NUM_OF_DCORES, DCORE_OFFSET, 2,3665			instance_offset, gaudi2_pb_dcr0_edma0,3666			ARRAY_SIZE(gaudi2_pb_dcr0_edma0),3667			prop->edma_enabled_mask);3668 3669	/* ARC EDMA */3670	hl_ack_pb_with_mask(hdev, NUM_OF_DCORES, DCORE_OFFSET, 2,3671			instance_offset, gaudi2_pb_dcr0_edma0_arc,3672			ARRAY_SIZE(gaudi2_pb_dcr0_edma0_arc),3673			prop->edma_enabled_mask);3674 3675	/* MME */3676	instance_offset = mmDCORE0_MME_SBTE1_BASE - mmDCORE0_MME_SBTE0_BASE;3677 3678	for (i = 0 ; i < NUM_OF_DCORES * NUM_OF_MME_PER_DCORE ; i++) {3679		/* MME SBTE */3680		hl_ack_pb_single_dcore(hdev, (DCORE_OFFSET * i), 5,3681				instance_offset, gaudi2_pb_dcr0_mme_sbte,3682				ARRAY_SIZE(gaudi2_pb_dcr0_mme_sbte));3683 3684		/* MME */3685		hl_ack_pb_single_dcore(hdev, (DCORE_OFFSET * i),3686				HL_PB_SINGLE_INSTANCE, HL_PB_NA,3687				gaudi2_pb_dcr0_mme_eng,3688				ARRAY_SIZE(gaudi2_pb_dcr0_mme_eng));3689	}3690 3691	/*3692	 * we have special iteration for case in which we would like to3693	 * configure stubbed MME's ARC/QMAN3694	 */3695	for (i = 0 ; i < NUM_OF_DCORES * NUM_OF_MME_PER_DCORE ; i++) {3696		/* MME QM */3697		hl_ack_pb_single_dcore(hdev, (DCORE_OFFSET * i),3698				HL_PB_SINGLE_INSTANCE, HL_PB_NA,3699				gaudi2_pb_dcr0_mme_qm,3700				ARRAY_SIZE(gaudi2_pb_dcr0_mme_qm));3701 3702		/* ARC MME */3703		hl_ack_pb_single_dcore(hdev, (DCORE_OFFSET * i),3704				HL_PB_SINGLE_INSTANCE, HL_PB_NA,3705				gaudi2_pb_dcr0_mme_arc,3706				ARRAY_SIZE(gaudi2_pb_dcr0_mme_arc));3707	}3708 3709	/* MME QM ARC ACP ENG */3710	hl_ack_pb_with_mask(hdev, NUM_OF_DCORES, DCORE_OFFSET,3711			HL_PB_SINGLE_INSTANCE, HL_PB_NA,3712			gaudi2_pb_mme_qm_arc_acp_eng,3713			ARRAY_SIZE(gaudi2_pb_mme_qm_arc_acp_eng),3714			(BIT(NUM_OF_DCORES * NUM_OF_MME_PER_DCORE) - 1));3715 3716	/* TPC */3717	gaudi2_ack_pb_tpc(hdev);3718 3719	/* SRAM */3720	instance_offset = mmDCORE0_SRAM1_BANK_BASE - mmDCORE0_SRAM0_BANK_BASE;3721	hl_ack_pb(hdev, NUM_OF_DCORES, DCORE_OFFSET, 8, instance_offset,3722			gaudi2_pb_dcr0_sram0, ARRAY_SIZE(gaudi2_pb_dcr0_sram0));3723 3724	/* Sync Manager MSTR IF */3725	hl_ack_pb(hdev, NUM_OF_DCORES, DCORE_OFFSET, HL_PB_SINGLE_INSTANCE, HL_PB_NA,3726			gaudi2_pb_dcr0_sm_mstr_if, ARRAY_SIZE(gaudi2_pb_dcr0_sm_mstr_if));3727 3728	/* Sync Manager */3729	hl_ack_pb(hdev, NUM_OF_DCORES, DCORE_OFFSET, HL_PB_SINGLE_INSTANCE, HL_PB_NA,3730			gaudi2_pb_dcr0_sm_glbl, ARRAY_SIZE(gaudi2_pb_dcr0_sm_glbl));3731 3732	hl_ack_pb(hdev, NUM_OF_DCORES, DCORE_OFFSET, HL_PB_SINGLE_INSTANCE, HL_PB_NA,3733			gaudi2_pb_dcr0_sm_mstr_if, ARRAY_SIZE(gaudi2_pb_dcr0_sm_mstr_if));3734 3735	/* PSOC.3736	 * Except for PSOC_GLOBAL_CONF, skip when security is enabled in F/W, because the blocks are3737	 * protected by privileged RR.3738	 */3739	hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, HL_PB_SINGLE_INSTANCE, HL_PB_NA,3740			gaudi2_pb_psoc_global_conf, ARRAY_SIZE(gaudi2_pb_psoc_global_conf));3741	if (!hdev->asic_prop.fw_security_enabled)3742		hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, HL_PB_SINGLE_INSTANCE, HL_PB_NA,3743				gaudi2_pb_psoc, ARRAY_SIZE(gaudi2_pb_psoc));3744 3745	/* PMMU */3746	hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, HL_PB_SINGLE_INSTANCE, HL_PB_NA,3747			gaudi2_pb_pmmu, ARRAY_SIZE(gaudi2_pb_pmmu));3748 3749	/* PLL.3750	 * Skip PSOC/XFT PLL when security is enabled in F/W, because these blocks are protected by3751	 * privileged RR.3752	 */3753	hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, HL_PB_SINGLE_INSTANCE, HL_PB_NA,3754			gaudi2_pb_pmmu_pll, ARRAY_SIZE(gaudi2_pb_pmmu_pll));3755	hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, HL_PB_SINGLE_INSTANCE, HL_PB_NA,3756			gaudi2_pb_xbar_pll, ARRAY_SIZE(gaudi2_pb_xbar_pll));3757	if (!hdev->asic_prop.fw_security_enabled) {3758		hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, HL_PB_SINGLE_INSTANCE, HL_PB_NA,3759				gaudi2_pb_psoc_pll, ARRAY_SIZE(gaudi2_pb_psoc_pll));3760		hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, HL_PB_SINGLE_INSTANCE, HL_PB_NA,3761				gaudi2_pb_xft_pll, ARRAY_SIZE(gaudi2_pb_xft_pll));3762	}3763 3764	/* PCIE */3765	hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, HL_PB_SINGLE_INSTANCE, HL_PB_NA,3766			gaudi2_pb_pcie, ARRAY_SIZE(gaudi2_pb_pcie));3767 3768	/* Thermal Sensor.3769	 * Skip when security is enabled in F/W, because the blocks are protected by privileged RR.3770	 */3771	if (!hdev->asic_prop.fw_security_enabled) {3772		instance_offset = mmDCORE1_XFT_BASE - mmDCORE0_XFT_BASE;3773		hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, 4, instance_offset,3774				gaudi2_pb_thermal_sensor0, ARRAY_SIZE(gaudi2_pb_thermal_sensor0));3775	}3776 3777	/* HBM */3778	instance_offset = mmHBM1_MC0_BASE - mmHBM0_MC0_BASE;3779	hl_ack_pb_with_mask(hdev, HL_PB_SHARED, HL_PB_NA, GAUDI2_HBM_NUM,3780			instance_offset, gaudi2_pb_hbm,3781			ARRAY_SIZE(gaudi2_pb_hbm), prop->dram_enabled_mask);3782 3783	/* Scheduler ARCs */3784	instance_offset = mmARC_FARM_ARC1_AUX_BASE - mmARC_FARM_ARC0_AUX_BASE;3785	hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, NUM_OF_ARC_FARMS_ARC,3786			instance_offset, gaudi2_pb_arc_sched,3787			ARRAY_SIZE(gaudi2_pb_arc_sched));3788 3789	/* XBAR MIDs */3790	instance_offset = mmXBAR_MID_1_BASE - mmXBAR_MID_0_BASE;3791	hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, NUM_OF_XBAR,3792			instance_offset, gaudi2_pb_xbar_mid,3793			ARRAY_SIZE(gaudi2_pb_xbar_mid));3794 3795	/* XBAR EDGEs */3796	instance_offset = mmXBAR_EDGE_1_BASE - mmXBAR_EDGE_0_BASE;3797	hl_ack_pb_with_mask(hdev, HL_PB_SHARED, HL_PB_NA, NUM_OF_XBAR,3798			instance_offset, gaudi2_pb_xbar_edge,3799			ARRAY_SIZE(gaudi2_pb_xbar_edge), prop->xbar_edge_enabled_mask);3800 3801	/* NIC */3802	hl_ack_pb_with_mask(hdev, NIC_NUMBER_OF_MACROS, NIC_OFFSET, HL_PB_SINGLE_INSTANCE, HL_PB_NA,3803			gaudi2_pb_nic0, ARRAY_SIZE(gaudi2_pb_nic0), hdev->nic_ports_mask);3804 3805	/* NIC QM and QPC */3806	hl_ack_pb_with_mask(hdev, NIC_NUMBER_OF_MACROS, NIC_OFFSET, NIC_NUMBER_OF_QM_PER_MACRO,3807			NIC_QM_OFFSET, gaudi2_pb_nic0_qm_qpc, ARRAY_SIZE(gaudi2_pb_nic0_qm_qpc),3808			hdev->nic_ports_mask);3809 3810	/* NIC QM ARC */3811	hl_ack_pb_with_mask(hdev, NIC_NUMBER_OF_MACROS, NIC_OFFSET, NIC_NUMBER_OF_QM_PER_MACRO,3812			NIC_QM_OFFSET, gaudi2_pb_nic0_qm_arc_aux0,3813			ARRAY_SIZE(gaudi2_pb_nic0_qm_arc_aux0), hdev->nic_ports_mask);3814 3815	/* NIC UMR */3816	hl_ack_pb_with_mask(hdev, NIC_NUMBER_OF_MACROS, NIC_OFFSET, NIC_NUMBER_OF_QM_PER_MACRO,3817			NIC_QM_OFFSET, gaudi2_pb_nic0_umr, ARRAY_SIZE(gaudi2_pb_nic0_umr),3818			hdev->nic_ports_mask);3819 3820	/* Rotators */3821	instance_offset = mmROT1_BASE - mmROT0_BASE;3822	hl_ack_pb_with_mask(hdev, HL_PB_SHARED, HL_PB_NA, NUM_OF_ROT, instance_offset,3823			gaudi2_pb_rot0, ARRAY_SIZE(gaudi2_pb_rot0), (BIT(NUM_OF_ROT) - 1));3824 3825	/* Rotators ARCS */3826	hl_ack_pb_with_mask(hdev, HL_PB_SHARED, HL_PB_NA, NUM_OF_ROT, instance_offset,3827			gaudi2_pb_rot0_arc, ARRAY_SIZE(gaudi2_pb_rot0_arc), (BIT(NUM_OF_ROT) - 1));3828}3829 3830/*3831 * Print PB security errors3832 */3833 3834void gaudi2_pb_print_security_errors(struct hl_device *hdev, u32 block_addr, u32 cause,3835					u32 offended_addr)3836{3837	int i = 0;3838	const char *error_format =3839		"Security error at block 0x%x, offending address 0x%x\n"3840		"Cause 0x%x: %s %s %s %s %s %s %s %s\n";3841	char *mcause[8] = {"Unknown", "", "", "", "", "", "", "" };3842 3843	if (!cause)3844		return;3845 3846	if (cause & SPECIAL_GLBL_ERR_CAUSE_APB_PRIV_RD)3847		mcause[i++] = "APB_PRIV_RD";3848 3849	if (cause & SPECIAL_GLBL_ERR_CAUSE_APB_SEC_RD)3850		mcause[i++] = "APB_SEC_RD";3851 3852	if (cause & SPECIAL_GLBL_ERR_CAUSE_APB_UNMAPPED_RD)3853		mcause[i++] = "APB_UNMAPPED_RD";3854 3855	if (cause & SPECIAL_GLBL_ERR_CAUSE_APB_PRIV_WR)3856		mcause[i++] = "APB_PRIV_WR";3857 3858	if (cause & SPECIAL_GLBL_ERR_CAUSE_APB_SEC_WR)3859		mcause[i++] = "APB_SEC_WR";3860 3861	if (cause & SPECIAL_GLBL_ERR_CAUSE_APB_UNMAPPED_WR)3862		mcause[i++] = "APB_UNMAPPED_WR";3863 3864	if (cause & SPECIAL_GLBL_ERR_CAUSE_EXT_SEC_WR)3865		mcause[i++] = "EXT_SEC_WR";3866 3867	if (cause & SPECIAL_GLBL_ERR_CAUSE_EXT_UNMAPPED_WR)3868		mcause[i++] = "APB_EXT_UNMAPPED_WR";3869 3870	dev_err_ratelimited(hdev->dev, error_format, block_addr, offended_addr,3871			cause, mcause[0], mcause[1], mcause[2], mcause[3],3872			mcause[4], mcause[5], mcause[6], mcause[7]);3873}3874