714 lines · c
1// SPDX-License-Identifier: GPL-2.02 3/*4 * Copyright 2016-2019 HabanaLabs, Ltd.5 * All Rights Reserved.6 */7 8#include "goyaP.h"9#include "../include/goya/goya_coresight.h"10#include "../include/goya/asic_reg/goya_regs.h"11#include "../include/goya/asic_reg/goya_masks.h"12 13#include <uapi/drm/habanalabs_accel.h>14 15#define GOYA_PLDM_CORESIGHT_TIMEOUT_USEC (CORESIGHT_TIMEOUT_USEC * 100)16 17#define SPMU_SECTION_SIZE DMA_CH_0_CS_SPMU_MAX_OFFSET18#define SPMU_EVENT_TYPES_OFFSET 0x40019#define SPMU_MAX_COUNTERS 620 21static u64 debug_stm_regs[GOYA_STM_LAST + 1] = {22 [GOYA_STM_CPU] = mmCPU_STM_BASE,23 [GOYA_STM_DMA_CH_0_CS] = mmDMA_CH_0_CS_STM_BASE,24 [GOYA_STM_DMA_CH_1_CS] = mmDMA_CH_1_CS_STM_BASE,25 [GOYA_STM_DMA_CH_2_CS] = mmDMA_CH_2_CS_STM_BASE,26 [GOYA_STM_DMA_CH_3_CS] = mmDMA_CH_3_CS_STM_BASE,27 [GOYA_STM_DMA_CH_4_CS] = mmDMA_CH_4_CS_STM_BASE,28 [GOYA_STM_DMA_MACRO_CS] = mmDMA_MACRO_CS_STM_BASE,29 [GOYA_STM_MME1_SBA] = mmMME1_SBA_STM_BASE,30 [GOYA_STM_MME3_SBB] = mmMME3_SBB_STM_BASE,31 [GOYA_STM_MME4_WACS2] = mmMME4_WACS2_STM_BASE,32 [GOYA_STM_MME4_WACS] = mmMME4_WACS_STM_BASE,33 [GOYA_STM_MMU_CS] = mmMMU_CS_STM_BASE,34 [GOYA_STM_PCIE] = mmPCIE_STM_BASE,35 [GOYA_STM_PSOC] = mmPSOC_STM_BASE,36 [GOYA_STM_TPC0_EML] = mmTPC0_EML_STM_BASE,37 [GOYA_STM_TPC1_EML] = mmTPC1_EML_STM_BASE,38 [GOYA_STM_TPC2_EML] = mmTPC2_EML_STM_BASE,39 [GOYA_STM_TPC3_EML] = mmTPC3_EML_STM_BASE,40 [GOYA_STM_TPC4_EML] = mmTPC4_EML_STM_BASE,41 [GOYA_STM_TPC5_EML] = mmTPC5_EML_STM_BASE,42 [GOYA_STM_TPC6_EML] = mmTPC6_EML_STM_BASE,43 [GOYA_STM_TPC7_EML] = mmTPC7_EML_STM_BASE44};45 46static u64 debug_etf_regs[GOYA_ETF_LAST + 1] = {47 [GOYA_ETF_CPU_0] = mmCPU_ETF_0_BASE,48 [GOYA_ETF_CPU_1] = mmCPU_ETF_1_BASE,49 [GOYA_ETF_CPU_TRACE] = mmCPU_ETF_TRACE_BASE,50 [GOYA_ETF_DMA_CH_0_CS] = mmDMA_CH_0_CS_ETF_BASE,51 [GOYA_ETF_DMA_CH_1_CS] = mmDMA_CH_1_CS_ETF_BASE,52 [GOYA_ETF_DMA_CH_2_CS] = mmDMA_CH_2_CS_ETF_BASE,53 [GOYA_ETF_DMA_CH_3_CS] = mmDMA_CH_3_CS_ETF_BASE,54 [GOYA_ETF_DMA_CH_4_CS] = mmDMA_CH_4_CS_ETF_BASE,55 [GOYA_ETF_DMA_MACRO_CS] = mmDMA_MACRO_CS_ETF_BASE,56 [GOYA_ETF_MME1_SBA] = mmMME1_SBA_ETF_BASE,57 [GOYA_ETF_MME3_SBB] = mmMME3_SBB_ETF_BASE,58 [GOYA_ETF_MME4_WACS2] = mmMME4_WACS2_ETF_BASE,59 [GOYA_ETF_MME4_WACS] = mmMME4_WACS_ETF_BASE,60 [GOYA_ETF_MMU_CS] = mmMMU_CS_ETF_BASE,61 [GOYA_ETF_PCIE] = mmPCIE_ETF_BASE,62 [GOYA_ETF_PSOC] = mmPSOC_ETF_BASE,63 [GOYA_ETF_TPC0_EML] = mmTPC0_EML_ETF_BASE,64 [GOYA_ETF_TPC1_EML] = mmTPC1_EML_ETF_BASE,65 [GOYA_ETF_TPC2_EML] = mmTPC2_EML_ETF_BASE,66 [GOYA_ETF_TPC3_EML] = mmTPC3_EML_ETF_BASE,67 [GOYA_ETF_TPC4_EML] = mmTPC4_EML_ETF_BASE,68 [GOYA_ETF_TPC5_EML] = mmTPC5_EML_ETF_BASE,69 [GOYA_ETF_TPC6_EML] = mmTPC6_EML_ETF_BASE,70 [GOYA_ETF_TPC7_EML] = mmTPC7_EML_ETF_BASE71};72 73static u64 debug_funnel_regs[GOYA_FUNNEL_LAST + 1] = {74 [GOYA_FUNNEL_CPU] = mmCPU_FUNNEL_BASE,75 [GOYA_FUNNEL_DMA_CH_6_1] = mmDMA_CH_FUNNEL_6_1_BASE,76 [GOYA_FUNNEL_DMA_MACRO_3_1] = mmDMA_MACRO_FUNNEL_3_1_BASE,77 [GOYA_FUNNEL_MME0_RTR] = mmMME0_RTR_FUNNEL_BASE,78 [GOYA_FUNNEL_MME1_RTR] = mmMME1_RTR_FUNNEL_BASE,79 [GOYA_FUNNEL_MME2_RTR] = mmMME2_RTR_FUNNEL_BASE,80 [GOYA_FUNNEL_MME3_RTR] = mmMME3_RTR_FUNNEL_BASE,81 [GOYA_FUNNEL_MME4_RTR] = mmMME4_RTR_FUNNEL_BASE,82 [GOYA_FUNNEL_MME5_RTR] = mmMME5_RTR_FUNNEL_BASE,83 [GOYA_FUNNEL_PCIE] = mmPCIE_FUNNEL_BASE,84 [GOYA_FUNNEL_PSOC] = mmPSOC_FUNNEL_BASE,85 [GOYA_FUNNEL_TPC0_EML] = mmTPC0_EML_FUNNEL_BASE,86 [GOYA_FUNNEL_TPC1_EML] = mmTPC1_EML_FUNNEL_BASE,87 [GOYA_FUNNEL_TPC1_RTR] = mmTPC1_RTR_FUNNEL_BASE,88 [GOYA_FUNNEL_TPC2_EML] = mmTPC2_EML_FUNNEL_BASE,89 [GOYA_FUNNEL_TPC2_RTR] = mmTPC2_RTR_FUNNEL_BASE,90 [GOYA_FUNNEL_TPC3_EML] = mmTPC3_EML_FUNNEL_BASE,91 [GOYA_FUNNEL_TPC3_RTR] = mmTPC3_RTR_FUNNEL_BASE,92 [GOYA_FUNNEL_TPC4_EML] = mmTPC4_EML_FUNNEL_BASE,93 [GOYA_FUNNEL_TPC4_RTR] = mmTPC4_RTR_FUNNEL_BASE,94 [GOYA_FUNNEL_TPC5_EML] = mmTPC5_EML_FUNNEL_BASE,95 [GOYA_FUNNEL_TPC5_RTR] = mmTPC5_RTR_FUNNEL_BASE,96 [GOYA_FUNNEL_TPC6_EML] = mmTPC6_EML_FUNNEL_BASE,97 [GOYA_FUNNEL_TPC6_RTR] = mmTPC6_RTR_FUNNEL_BASE,98 [GOYA_FUNNEL_TPC7_EML] = mmTPC7_EML_FUNNEL_BASE99};100 101static u64 debug_bmon_regs[GOYA_BMON_LAST + 1] = {102 [GOYA_BMON_CPU_RD] = mmCPU_RD_BMON_BASE,103 [GOYA_BMON_CPU_WR] = mmCPU_WR_BMON_BASE,104 [GOYA_BMON_DMA_CH_0_0] = mmDMA_CH_0_BMON_0_BASE,105 [GOYA_BMON_DMA_CH_0_1] = mmDMA_CH_0_BMON_1_BASE,106 [GOYA_BMON_DMA_CH_1_0] = mmDMA_CH_1_BMON_0_BASE,107 [GOYA_BMON_DMA_CH_1_1] = mmDMA_CH_1_BMON_1_BASE,108 [GOYA_BMON_DMA_CH_2_0] = mmDMA_CH_2_BMON_0_BASE,109 [GOYA_BMON_DMA_CH_2_1] = mmDMA_CH_2_BMON_1_BASE,110 [GOYA_BMON_DMA_CH_3_0] = mmDMA_CH_3_BMON_0_BASE,111 [GOYA_BMON_DMA_CH_3_1] = mmDMA_CH_3_BMON_1_BASE,112 [GOYA_BMON_DMA_CH_4_0] = mmDMA_CH_4_BMON_0_BASE,113 [GOYA_BMON_DMA_CH_4_1] = mmDMA_CH_4_BMON_1_BASE,114 [GOYA_BMON_DMA_MACRO_0] = mmDMA_MACRO_BMON_0_BASE,115 [GOYA_BMON_DMA_MACRO_1] = mmDMA_MACRO_BMON_1_BASE,116 [GOYA_BMON_DMA_MACRO_2] = mmDMA_MACRO_BMON_2_BASE,117 [GOYA_BMON_DMA_MACRO_3] = mmDMA_MACRO_BMON_3_BASE,118 [GOYA_BMON_DMA_MACRO_4] = mmDMA_MACRO_BMON_4_BASE,119 [GOYA_BMON_DMA_MACRO_5] = mmDMA_MACRO_BMON_5_BASE,120 [GOYA_BMON_DMA_MACRO_6] = mmDMA_MACRO_BMON_6_BASE,121 [GOYA_BMON_DMA_MACRO_7] = mmDMA_MACRO_BMON_7_BASE,122 [GOYA_BMON_MME1_SBA_0] = mmMME1_SBA_BMON0_BASE,123 [GOYA_BMON_MME1_SBA_1] = mmMME1_SBA_BMON1_BASE,124 [GOYA_BMON_MME3_SBB_0] = mmMME3_SBB_BMON0_BASE,125 [GOYA_BMON_MME3_SBB_1] = mmMME3_SBB_BMON1_BASE,126 [GOYA_BMON_MME4_WACS2_0] = mmMME4_WACS2_BMON0_BASE,127 [GOYA_BMON_MME4_WACS2_1] = mmMME4_WACS2_BMON1_BASE,128 [GOYA_BMON_MME4_WACS2_2] = mmMME4_WACS2_BMON2_BASE,129 [GOYA_BMON_MME4_WACS_0] = mmMME4_WACS_BMON0_BASE,130 [GOYA_BMON_MME4_WACS_1] = mmMME4_WACS_BMON1_BASE,131 [GOYA_BMON_MME4_WACS_2] = mmMME4_WACS_BMON2_BASE,132 [GOYA_BMON_MME4_WACS_3] = mmMME4_WACS_BMON3_BASE,133 [GOYA_BMON_MME4_WACS_4] = mmMME4_WACS_BMON4_BASE,134 [GOYA_BMON_MME4_WACS_5] = mmMME4_WACS_BMON5_BASE,135 [GOYA_BMON_MME4_WACS_6] = mmMME4_WACS_BMON6_BASE,136 [GOYA_BMON_MMU_0] = mmMMU_BMON_0_BASE,137 [GOYA_BMON_MMU_1] = mmMMU_BMON_1_BASE,138 [GOYA_BMON_PCIE_MSTR_RD] = mmPCIE_BMON_MSTR_RD_BASE,139 [GOYA_BMON_PCIE_MSTR_WR] = mmPCIE_BMON_MSTR_WR_BASE,140 [GOYA_BMON_PCIE_SLV_RD] = mmPCIE_BMON_SLV_RD_BASE,141 [GOYA_BMON_PCIE_SLV_WR] = mmPCIE_BMON_SLV_WR_BASE,142 [GOYA_BMON_TPC0_EML_0] = mmTPC0_EML_BUSMON_0_BASE,143 [GOYA_BMON_TPC0_EML_1] = mmTPC0_EML_BUSMON_1_BASE,144 [GOYA_BMON_TPC0_EML_2] = mmTPC0_EML_BUSMON_2_BASE,145 [GOYA_BMON_TPC0_EML_3] = mmTPC0_EML_BUSMON_3_BASE,146 [GOYA_BMON_TPC1_EML_0] = mmTPC1_EML_BUSMON_0_BASE,147 [GOYA_BMON_TPC1_EML_1] = mmTPC1_EML_BUSMON_1_BASE,148 [GOYA_BMON_TPC1_EML_2] = mmTPC1_EML_BUSMON_2_BASE,149 [GOYA_BMON_TPC1_EML_3] = mmTPC1_EML_BUSMON_3_BASE,150 [GOYA_BMON_TPC2_EML_0] = mmTPC2_EML_BUSMON_0_BASE,151 [GOYA_BMON_TPC2_EML_1] = mmTPC2_EML_BUSMON_1_BASE,152 [GOYA_BMON_TPC2_EML_2] = mmTPC2_EML_BUSMON_2_BASE,153 [GOYA_BMON_TPC2_EML_3] = mmTPC2_EML_BUSMON_3_BASE,154 [GOYA_BMON_TPC3_EML_0] = mmTPC3_EML_BUSMON_0_BASE,155 [GOYA_BMON_TPC3_EML_1] = mmTPC3_EML_BUSMON_1_BASE,156 [GOYA_BMON_TPC3_EML_2] = mmTPC3_EML_BUSMON_2_BASE,157 [GOYA_BMON_TPC3_EML_3] = mmTPC3_EML_BUSMON_3_BASE,158 [GOYA_BMON_TPC4_EML_0] = mmTPC4_EML_BUSMON_0_BASE,159 [GOYA_BMON_TPC4_EML_1] = mmTPC4_EML_BUSMON_1_BASE,160 [GOYA_BMON_TPC4_EML_2] = mmTPC4_EML_BUSMON_2_BASE,161 [GOYA_BMON_TPC4_EML_3] = mmTPC4_EML_BUSMON_3_BASE,162 [GOYA_BMON_TPC5_EML_0] = mmTPC5_EML_BUSMON_0_BASE,163 [GOYA_BMON_TPC5_EML_1] = mmTPC5_EML_BUSMON_1_BASE,164 [GOYA_BMON_TPC5_EML_2] = mmTPC5_EML_BUSMON_2_BASE,165 [GOYA_BMON_TPC5_EML_3] = mmTPC5_EML_BUSMON_3_BASE,166 [GOYA_BMON_TPC6_EML_0] = mmTPC6_EML_BUSMON_0_BASE,167 [GOYA_BMON_TPC6_EML_1] = mmTPC6_EML_BUSMON_1_BASE,168 [GOYA_BMON_TPC6_EML_2] = mmTPC6_EML_BUSMON_2_BASE,169 [GOYA_BMON_TPC6_EML_3] = mmTPC6_EML_BUSMON_3_BASE,170 [GOYA_BMON_TPC7_EML_0] = mmTPC7_EML_BUSMON_0_BASE,171 [GOYA_BMON_TPC7_EML_1] = mmTPC7_EML_BUSMON_1_BASE,172 [GOYA_BMON_TPC7_EML_2] = mmTPC7_EML_BUSMON_2_BASE,173 [GOYA_BMON_TPC7_EML_3] = mmTPC7_EML_BUSMON_3_BASE174};175 176static u64 debug_spmu_regs[GOYA_SPMU_LAST + 1] = {177 [GOYA_SPMU_DMA_CH_0_CS] = mmDMA_CH_0_CS_SPMU_BASE,178 [GOYA_SPMU_DMA_CH_1_CS] = mmDMA_CH_1_CS_SPMU_BASE,179 [GOYA_SPMU_DMA_CH_2_CS] = mmDMA_CH_2_CS_SPMU_BASE,180 [GOYA_SPMU_DMA_CH_3_CS] = mmDMA_CH_3_CS_SPMU_BASE,181 [GOYA_SPMU_DMA_CH_4_CS] = mmDMA_CH_4_CS_SPMU_BASE,182 [GOYA_SPMU_DMA_MACRO_CS] = mmDMA_MACRO_CS_SPMU_BASE,183 [GOYA_SPMU_MME1_SBA] = mmMME1_SBA_SPMU_BASE,184 [GOYA_SPMU_MME3_SBB] = mmMME3_SBB_SPMU_BASE,185 [GOYA_SPMU_MME4_WACS2] = mmMME4_WACS2_SPMU_BASE,186 [GOYA_SPMU_MME4_WACS] = mmMME4_WACS_SPMU_BASE,187 [GOYA_SPMU_MMU_CS] = mmMMU_CS_SPMU_BASE,188 [GOYA_SPMU_PCIE] = mmPCIE_SPMU_BASE,189 [GOYA_SPMU_TPC0_EML] = mmTPC0_EML_SPMU_BASE,190 [GOYA_SPMU_TPC1_EML] = mmTPC1_EML_SPMU_BASE,191 [GOYA_SPMU_TPC2_EML] = mmTPC2_EML_SPMU_BASE,192 [GOYA_SPMU_TPC3_EML] = mmTPC3_EML_SPMU_BASE,193 [GOYA_SPMU_TPC4_EML] = mmTPC4_EML_SPMU_BASE,194 [GOYA_SPMU_TPC5_EML] = mmTPC5_EML_SPMU_BASE,195 [GOYA_SPMU_TPC6_EML] = mmTPC6_EML_SPMU_BASE,196 [GOYA_SPMU_TPC7_EML] = mmTPC7_EML_SPMU_BASE197};198 199static int goya_coresight_timeout(struct hl_device *hdev, u64 addr,200 int position, bool up)201{202 int rc;203 u32 val, timeout_usec;204 205 if (hdev->pldm)206 timeout_usec = GOYA_PLDM_CORESIGHT_TIMEOUT_USEC;207 else208 timeout_usec = CORESIGHT_TIMEOUT_USEC;209 210 rc = hl_poll_timeout(211 hdev,212 addr,213 val,214 up ? val & BIT(position) : !(val & BIT(position)),215 1000,216 timeout_usec);217 218 if (rc) {219 dev_err(hdev->dev,220 "Timeout while waiting for coresight, addr: 0x%llx, position: %d, up: %d\n",221 addr, position, up);222 return -EFAULT;223 }224 225 return 0;226}227 228static int goya_config_stm(struct hl_device *hdev,229 struct hl_debug_params *params)230{231 struct hl_debug_params_stm *input;232 u64 base_reg;233 u32 frequency;234 int rc;235 236 if (params->reg_idx >= ARRAY_SIZE(debug_stm_regs)) {237 dev_err(hdev->dev, "Invalid register index in STM\n");238 return -EINVAL;239 }240 241 base_reg = debug_stm_regs[params->reg_idx] - CFG_BASE;242 243 WREG32(base_reg + 0xFB0, CORESIGHT_UNLOCK);244 245 if (params->enable) {246 input = params->input;247 248 if (!input)249 return -EINVAL;250 251 WREG32(base_reg + 0xE80, 0x80004);252 WREG32(base_reg + 0xD64, 7);253 WREG32(base_reg + 0xD60, 0);254 WREG32(base_reg + 0xD00, lower_32_bits(input->he_mask));255 WREG32(base_reg + 0xD20, lower_32_bits(input->sp_mask));256 WREG32(base_reg + 0xD60, 1);257 WREG32(base_reg + 0xD00, upper_32_bits(input->he_mask));258 WREG32(base_reg + 0xD20, upper_32_bits(input->sp_mask));259 WREG32(base_reg + 0xE70, 0x10);260 WREG32(base_reg + 0xE60, 0);261 WREG32(base_reg + 0xE64, 0x420000);262 WREG32(base_reg + 0xE00, 0xFFFFFFFF);263 WREG32(base_reg + 0xE20, 0xFFFFFFFF);264 WREG32(base_reg + 0xEF4, input->id);265 WREG32(base_reg + 0xDF4, 0x80);266 frequency = hdev->asic_prop.psoc_timestamp_frequency;267 if (frequency == 0)268 frequency = input->frequency;269 WREG32(base_reg + 0xE8C, frequency);270 WREG32(base_reg + 0xE90, 0x7FF);271 WREG32(base_reg + 0xE80, 0x27 | (input->id << 16));272 } else {273 WREG32(base_reg + 0xE80, 4);274 WREG32(base_reg + 0xD64, 0);275 WREG32(base_reg + 0xD60, 1);276 WREG32(base_reg + 0xD00, 0);277 WREG32(base_reg + 0xD20, 0);278 WREG32(base_reg + 0xD60, 0);279 WREG32(base_reg + 0xE20, 0);280 WREG32(base_reg + 0xE00, 0);281 WREG32(base_reg + 0xDF4, 0x80);282 WREG32(base_reg + 0xE70, 0);283 WREG32(base_reg + 0xE60, 0);284 WREG32(base_reg + 0xE64, 0);285 WREG32(base_reg + 0xE8C, 0);286 287 rc = goya_coresight_timeout(hdev, base_reg + 0xE80, 23, false);288 if (rc) {289 dev_err(hdev->dev,290 "Failed to disable STM on timeout, error %d\n",291 rc);292 return rc;293 }294 295 WREG32(base_reg + 0xE80, 4);296 }297 298 return 0;299}300 301static int goya_config_etf(struct hl_device *hdev,302 struct hl_debug_params *params)303{304 struct hl_debug_params_etf *input;305 u64 base_reg;306 u32 val;307 int rc;308 309 if (params->reg_idx >= ARRAY_SIZE(debug_etf_regs)) {310 dev_err(hdev->dev, "Invalid register index in ETF\n");311 return -EINVAL;312 }313 314 base_reg = debug_etf_regs[params->reg_idx] - CFG_BASE;315 316 WREG32(base_reg + 0xFB0, CORESIGHT_UNLOCK);317 318 val = RREG32(base_reg + 0x20);319 320 if ((!params->enable && val == 0x0) || (params->enable && val != 0x0))321 return 0;322 323 val = RREG32(base_reg + 0x304);324 val |= 0x1000;325 WREG32(base_reg + 0x304, val);326 val |= 0x40;327 WREG32(base_reg + 0x304, val);328 329 rc = goya_coresight_timeout(hdev, base_reg + 0x304, 6, false);330 if (rc) {331 dev_err(hdev->dev,332 "Failed to %s ETF on timeout, error %d\n",333 params->enable ? "enable" : "disable", rc);334 return rc;335 }336 337 rc = goya_coresight_timeout(hdev, base_reg + 0xC, 2, true);338 if (rc) {339 dev_err(hdev->dev,340 "Failed to %s ETF on timeout, error %d\n",341 params->enable ? "enable" : "disable", rc);342 return rc;343 }344 345 WREG32(base_reg + 0x20, 0);346 347 if (params->enable) {348 input = params->input;349 350 if (!input)351 return -EINVAL;352 353 WREG32(base_reg + 0x34, 0x3FFC);354 WREG32(base_reg + 0x28, input->sink_mode);355 WREG32(base_reg + 0x304, 0x4001);356 WREG32(base_reg + 0x308, 0xA);357 WREG32(base_reg + 0x20, 1);358 } else {359 WREG32(base_reg + 0x34, 0);360 WREG32(base_reg + 0x28, 0);361 WREG32(base_reg + 0x304, 0);362 }363 364 return 0;365}366 367static int goya_etr_validate_address(struct hl_device *hdev, u64 addr,368 u64 size)369{370 struct asic_fixed_properties *prop = &hdev->asic_prop;371 u64 range_start, range_end;372 373 if (addr > (addr + size)) {374 dev_err(hdev->dev,375 "ETR buffer size %llu overflow\n", size);376 return false;377 }378 379 range_start = prop->dmmu.start_addr;380 range_end = prop->dmmu.end_addr;381 382 return hl_mem_area_inside_range(addr, size, range_start, range_end);383}384 385static int goya_config_etr(struct hl_device *hdev,386 struct hl_debug_params *params)387{388 struct hl_debug_params_etr *input;389 u32 val;390 int rc;391 392 WREG32(mmPSOC_ETR_LAR, CORESIGHT_UNLOCK);393 394 val = RREG32(mmPSOC_ETR_CTL);395 396 if ((!params->enable && val == 0x0) || (params->enable && val != 0x0))397 return 0;398 399 val = RREG32(mmPSOC_ETR_FFCR);400 val |= 0x1000;401 WREG32(mmPSOC_ETR_FFCR, val);402 val |= 0x40;403 WREG32(mmPSOC_ETR_FFCR, val);404 405 rc = goya_coresight_timeout(hdev, mmPSOC_ETR_FFCR, 6, false);406 if (rc) {407 dev_err(hdev->dev, "Failed to %s ETR on timeout, error %d\n",408 params->enable ? "enable" : "disable", rc);409 return rc;410 }411 412 rc = goya_coresight_timeout(hdev, mmPSOC_ETR_STS, 2, true);413 if (rc) {414 dev_err(hdev->dev, "Failed to %s ETR on timeout, error %d\n",415 params->enable ? "enable" : "disable", rc);416 return rc;417 }418 419 WREG32(mmPSOC_ETR_CTL, 0);420 421 if (params->enable) {422 input = params->input;423 424 if (!input)425 return -EINVAL;426 427 if (input->buffer_size == 0) {428 dev_err(hdev->dev,429 "ETR buffer size should be bigger than 0\n");430 return -EINVAL;431 }432 433 if (!goya_etr_validate_address(hdev,434 input->buffer_address, input->buffer_size)) {435 dev_err(hdev->dev, "buffer address is not valid\n");436 return -EINVAL;437 }438 439 WREG32(mmPSOC_ETR_BUFWM, 0x3FFC);440 WREG32(mmPSOC_ETR_RSZ, input->buffer_size);441 WREG32(mmPSOC_ETR_MODE, input->sink_mode);442 if (!hdev->asic_prop.fw_security_enabled) {443 /* make ETR not privileged */444 val = FIELD_PREP(PSOC_ETR_AXICTL_PROTCTRLBIT0_MASK, 0);445 /* make ETR non-secured (inverted logic) */446 val |= FIELD_PREP(PSOC_ETR_AXICTL_PROTCTRLBIT1_MASK, 1);447 /* burst size 8 */448 val |= FIELD_PREP(PSOC_ETR_AXICTL_WRBURSTLEN_MASK, 7);449 WREG32(mmPSOC_ETR_AXICTL, val);450 }451 WREG32(mmPSOC_ETR_DBALO,452 lower_32_bits(input->buffer_address));453 WREG32(mmPSOC_ETR_DBAHI,454 upper_32_bits(input->buffer_address));455 WREG32(mmPSOC_ETR_FFCR, 3);456 WREG32(mmPSOC_ETR_PSCR, 0xA);457 WREG32(mmPSOC_ETR_CTL, 1);458 } else {459 WREG32(mmPSOC_ETR_BUFWM, 0);460 WREG32(mmPSOC_ETR_RSZ, 0x400);461 WREG32(mmPSOC_ETR_DBALO, 0);462 WREG32(mmPSOC_ETR_DBAHI, 0);463 WREG32(mmPSOC_ETR_PSCR, 0);464 WREG32(mmPSOC_ETR_MODE, 0);465 WREG32(mmPSOC_ETR_FFCR, 0);466 467 if (params->output_size >= sizeof(u64)) {468 u32 rwp, rwphi;469 470 /*471 * The trace buffer address is 40 bits wide. The end of472 * the buffer is set in the RWP register (lower 32473 * bits), and in the RWPHI register (upper 8 bits).474 */475 rwp = RREG32(mmPSOC_ETR_RWP);476 rwphi = RREG32(mmPSOC_ETR_RWPHI) & 0xff;477 *(u64 *) params->output = ((u64) rwphi << 32) | rwp;478 }479 }480 481 return 0;482}483 484static int goya_config_funnel(struct hl_device *hdev,485 struct hl_debug_params *params)486{487 u64 base_reg;488 489 if (params->reg_idx >= ARRAY_SIZE(debug_funnel_regs)) {490 dev_err(hdev->dev, "Invalid register index in FUNNEL\n");491 return -EINVAL;492 }493 494 base_reg = debug_funnel_regs[params->reg_idx] - CFG_BASE;495 496 WREG32(base_reg + 0xFB0, CORESIGHT_UNLOCK);497 498 WREG32(base_reg, params->enable ? 0x33F : 0);499 500 return 0;501}502 503static int goya_config_bmon(struct hl_device *hdev,504 struct hl_debug_params *params)505{506 struct hl_debug_params_bmon *input;507 u64 base_reg;508 u32 pcie_base = 0;509 510 if (params->reg_idx >= ARRAY_SIZE(debug_bmon_regs)) {511 dev_err(hdev->dev, "Invalid register index in BMON\n");512 return -EINVAL;513 }514 515 base_reg = debug_bmon_regs[params->reg_idx] - CFG_BASE;516 517 WREG32(base_reg + 0x104, 1);518 519 if (params->enable) {520 input = params->input;521 522 if (!input)523 return -EINVAL;524 525 WREG32(base_reg + 0x200, lower_32_bits(input->start_addr0));526 WREG32(base_reg + 0x204, upper_32_bits(input->start_addr0));527 WREG32(base_reg + 0x208, lower_32_bits(input->addr_mask0));528 WREG32(base_reg + 0x20C, upper_32_bits(input->addr_mask0));529 WREG32(base_reg + 0x240, lower_32_bits(input->start_addr1));530 WREG32(base_reg + 0x244, upper_32_bits(input->start_addr1));531 WREG32(base_reg + 0x248, lower_32_bits(input->addr_mask1));532 WREG32(base_reg + 0x24C, upper_32_bits(input->addr_mask1));533 WREG32(base_reg + 0x224, 0);534 WREG32(base_reg + 0x234, 0);535 WREG32(base_reg + 0x30C, input->bw_win);536 WREG32(base_reg + 0x308, input->win_capture);537 538 /* PCIE IF BMON bug WA */539 if (params->reg_idx != GOYA_BMON_PCIE_MSTR_RD &&540 params->reg_idx != GOYA_BMON_PCIE_MSTR_WR &&541 params->reg_idx != GOYA_BMON_PCIE_SLV_RD &&542 params->reg_idx != GOYA_BMON_PCIE_SLV_WR)543 pcie_base = 0xA000000;544 545 WREG32(base_reg + 0x700, pcie_base | 0xB00 | (input->id << 12));546 WREG32(base_reg + 0x708, pcie_base | 0xA00 | (input->id << 12));547 WREG32(base_reg + 0x70C, pcie_base | 0xC00 | (input->id << 12));548 549 WREG32(base_reg + 0x100, 0x11);550 WREG32(base_reg + 0x304, 0x1);551 } else {552 WREG32(base_reg + 0x200, 0);553 WREG32(base_reg + 0x204, 0);554 WREG32(base_reg + 0x208, 0xFFFFFFFF);555 WREG32(base_reg + 0x20C, 0xFFFFFFFF);556 WREG32(base_reg + 0x240, 0);557 WREG32(base_reg + 0x244, 0);558 WREG32(base_reg + 0x248, 0xFFFFFFFF);559 WREG32(base_reg + 0x24C, 0xFFFFFFFF);560 WREG32(base_reg + 0x224, 0xFFFFFFFF);561 WREG32(base_reg + 0x234, 0x1070F);562 WREG32(base_reg + 0x30C, 0);563 WREG32(base_reg + 0x308, 0xFFFF);564 WREG32(base_reg + 0x700, 0xA000B00);565 WREG32(base_reg + 0x708, 0xA000A00);566 WREG32(base_reg + 0x70C, 0xA000C00);567 WREG32(base_reg + 0x100, 1);568 WREG32(base_reg + 0x304, 0);569 WREG32(base_reg + 0x104, 0);570 }571 572 return 0;573}574 575static int goya_config_spmu(struct hl_device *hdev,576 struct hl_debug_params *params)577{578 u64 base_reg;579 u64 *output;580 u32 output_arr_len;581 u32 events_num;582 u32 overflow_idx;583 u32 cycle_cnt_idx;584 int i;585 586 if (params->reg_idx >= ARRAY_SIZE(debug_spmu_regs)) {587 dev_err(hdev->dev, "Invalid register index in SPMU\n");588 return -EINVAL;589 }590 591 base_reg = debug_spmu_regs[params->reg_idx] - CFG_BASE;592 593 if (params->enable) {594 struct hl_debug_params_spmu *input = params->input;595 596 if (!input)597 return -EINVAL;598 599 if (input->event_types_num < 3) {600 dev_err(hdev->dev,601 "not enough event types values for SPMU enable\n");602 return -EINVAL;603 }604 605 if (input->event_types_num > SPMU_MAX_COUNTERS) {606 dev_err(hdev->dev,607 "too many event types values for SPMU enable\n");608 return -EINVAL;609 }610 611 WREG32(base_reg + 0xE04, 0x41013046);612 WREG32(base_reg + 0xE04, 0x41013040);613 614 for (i = 0 ; i < input->event_types_num ; i++)615 WREG32(base_reg + SPMU_EVENT_TYPES_OFFSET + i * 4,616 input->event_types[i]);617 618 WREG32(base_reg + 0xE04, 0x41013041);619 WREG32(base_reg + 0xC00, 0x8000003F);620 } else {621 output = params->output;622 output_arr_len = params->output_size / 8;623 events_num = output_arr_len - 2;624 overflow_idx = output_arr_len - 2;625 cycle_cnt_idx = output_arr_len - 1;626 627 if (!output)628 return -EINVAL;629 630 if (output_arr_len < 3) {631 dev_err(hdev->dev,632 "not enough values for SPMU disable\n");633 return -EINVAL;634 }635 636 if (events_num > SPMU_MAX_COUNTERS) {637 dev_err(hdev->dev,638 "too many events values for SPMU disable\n");639 return -EINVAL;640 }641 642 WREG32(base_reg + 0xE04, 0x41013040);643 644 for (i = 0 ; i < events_num ; i++)645 output[i] = RREG32(base_reg + i * 8);646 647 output[overflow_idx] = RREG32(base_reg + 0xCC0);648 649 output[cycle_cnt_idx] = RREG32(base_reg + 0xFC);650 output[cycle_cnt_idx] <<= 32;651 output[cycle_cnt_idx] |= RREG32(base_reg + 0xF8);652 653 WREG32(base_reg + 0xCC0, 0);654 }655 656 return 0;657}658 659int goya_debug_coresight(struct hl_device *hdev, struct hl_ctx *ctx, void *data)660{661 struct hl_debug_params *params = data;662 int rc = 0;663 664 switch (params->op) {665 case HL_DEBUG_OP_STM:666 rc = goya_config_stm(hdev, params);667 break;668 case HL_DEBUG_OP_ETF:669 rc = goya_config_etf(hdev, params);670 break;671 case HL_DEBUG_OP_ETR:672 rc = goya_config_etr(hdev, params);673 break;674 case HL_DEBUG_OP_FUNNEL:675 rc = goya_config_funnel(hdev, params);676 break;677 case HL_DEBUG_OP_BMON:678 rc = goya_config_bmon(hdev, params);679 break;680 case HL_DEBUG_OP_SPMU:681 rc = goya_config_spmu(hdev, params);682 break;683 case HL_DEBUG_OP_TIMESTAMP:684 /* Do nothing as this opcode is deprecated */685 break;686 687 default:688 dev_err(hdev->dev, "Unknown coresight id %d\n", params->op);689 return -EINVAL;690 }691 692 /* Perform read from the device to flush all configuration */693 RREG32(mmPCIE_DBI_DEVICE_ID_VENDOR_ID_REG);694 695 return rc;696}697 698void goya_halt_coresight(struct hl_device *hdev, struct hl_ctx *ctx)699{700 struct hl_debug_params params = {};701 int i, rc;702 703 for (i = GOYA_ETF_FIRST ; i <= GOYA_ETF_LAST ; i++) {704 params.reg_idx = i;705 rc = goya_config_etf(hdev, ¶ms);706 if (rc)707 dev_err(hdev->dev, "halt ETF failed, %d/%d\n", rc, i);708 }709 710 rc = goya_config_etr(hdev, ¶ms);711 if (rc)712 dev_err(hdev->dev, "halt ETR failed, %d\n", rc);713}714