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1/* SPDX-License-Identifier: GPL-2.02 *3 * Copyright 2016-2020 HabanaLabs, Ltd.4 * All Rights Reserved.5 *6 */7 8#ifndef GAUDI_MASKS_H_9#define GAUDI_MASKS_H_10 11#include "asic_reg/gaudi_regs.h"12 13/* Useful masks for bits in various registers */14#define PCI_DMA_QMAN_ENABLE (\15 (FIELD_PREP(DMA0_QM_GLBL_CFG0_PQF_EN_MASK, 0xF)) | \16 (FIELD_PREP(DMA0_QM_GLBL_CFG0_CQF_EN_MASK, 0xF)) | \17 (FIELD_PREP(DMA0_QM_GLBL_CFG0_CP_EN_MASK, 0xF)))18 19#define QMAN_EXTERNAL_MAKE_TRUSTED (\20 (FIELD_PREP(DMA0_QM_GLBL_PROT_PQF_MASK, 0xF)) | \21 (FIELD_PREP(DMA0_QM_GLBL_PROT_CQF_MASK, 0xF)) | \22 (FIELD_PREP(DMA0_QM_GLBL_PROT_CP_MASK, 0xF)) | \23 (FIELD_PREP(DMA0_QM_GLBL_PROT_ERR_MASK, 0x1)))24 25#define QMAN_INTERNAL_MAKE_TRUSTED (\26 (FIELD_PREP(DMA0_QM_GLBL_PROT_PQF_MASK, 0xF)) | \27 (FIELD_PREP(DMA0_QM_GLBL_PROT_ERR_MASK, 0x1)))28 29#define HBM_DMA_QMAN_ENABLE (\30 (FIELD_PREP(DMA0_QM_GLBL_CFG0_PQF_EN_MASK, 0xF)) | \31 (FIELD_PREP(DMA0_QM_GLBL_CFG0_CQF_EN_MASK, 0x1F)) | \32 (FIELD_PREP(DMA0_QM_GLBL_CFG0_CP_EN_MASK, 0x1F)))33 34#define QMAN_MME_ENABLE (\35 (FIELD_PREP(MME0_QM_GLBL_CFG0_PQF_EN_MASK, 0xF)) | \36 (FIELD_PREP(MME0_QM_GLBL_CFG0_CQF_EN_MASK, 0x1F)) | \37 (FIELD_PREP(MME0_QM_GLBL_CFG0_CP_EN_MASK, 0x1F)))38 39#define QMAN_TPC_ENABLE (\40 (FIELD_PREP(TPC0_QM_GLBL_CFG0_PQF_EN_MASK, 0xF)) | \41 (FIELD_PREP(TPC0_QM_GLBL_CFG0_CQF_EN_MASK, 0x1F)) | \42 (FIELD_PREP(TPC0_QM_GLBL_CFG0_CP_EN_MASK, 0x1F)))43 44#define NIC_QMAN_ENABLE (\45 (FIELD_PREP(NIC0_QM0_GLBL_CFG0_PQF_EN_MASK, 0xF)) | \46 (FIELD_PREP(NIC0_QM0_GLBL_CFG0_CQF_EN_MASK, 0xF)) | \47 (FIELD_PREP(NIC0_QM0_GLBL_CFG0_CP_EN_MASK, 0xF)))48 49#define QMAN_UPPER_CP_CGM_PWR_GATE_EN (\50 (FIELD_PREP(DMA0_QM_CGM_CFG_IDLE_TH_MASK, 0x20)) | \51 (FIELD_PREP(DMA0_QM_CGM_CFG_G2F_TH_MASK, 0xA)) | \52 (FIELD_PREP(DMA0_QM_CGM_CFG_CP_IDLE_MASK_MASK, 0x10)) | \53 (FIELD_PREP(DMA0_QM_CGM_CFG_EN_MASK, 0x1)))54 55#define QMAN_COMMON_CP_CGM_PWR_GATE_EN (\56 (FIELD_PREP(DMA0_QM_CGM_CFG_IDLE_TH_MASK, 0x20)) | \57 (FIELD_PREP(DMA0_QM_CGM_CFG_G2F_TH_MASK, 0xA)) | \58 (FIELD_PREP(DMA0_QM_CGM_CFG_CP_IDLE_MASK_MASK, 0xF)) | \59 (FIELD_PREP(DMA0_QM_CGM_CFG_EN_MASK, 0x1)))60 61#define PCI_DMA_QMAN_GLBL_ERR_CFG_MSG_EN_MASK (\62 (FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_MASK, 0xF)) | \63 (FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_MASK, 0xF)) | \64 (FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_MASK, 0xF)))65 66#define PCI_DMA_QMAN_GLBL_ERR_CFG_STOP_ON_ERR_EN_MASK (\67 (FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_MASK, 0xF)) | \68 (FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_MASK, 0xF)) | \69 (FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_MASK, 0xF)) | \70 (FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_ARB_STOP_ON_ERR_MASK, 0x1)))71 72#define HBM_DMA_QMAN_GLBL_ERR_CFG_MSG_EN_MASK (\73 (FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_MASK, 0xF)) | \74 (FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_MASK, 0x1F)) | \75 (FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_MASK, 0x1F)))76 77#define HBM_DMA_QMAN_GLBL_ERR_CFG_STOP_ON_ERR_EN_MASK (\78 (FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_MASK, 0xF)) | \79 (FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_MASK, 0x1F)) | \80 (FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_MASK, 0x1F)) | \81 (FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_ARB_STOP_ON_ERR_MASK, 0x1)))82 83#define TPC_QMAN_GLBL_ERR_CFG_MSG_EN_MASK (\84 (FIELD_PREP(TPC0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_MASK, 0xF)) | \85 (FIELD_PREP(TPC0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_MASK, 0x1F)) | \86 (FIELD_PREP(TPC0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_MASK, 0x1F)))87 88#define TPC_QMAN_GLBL_ERR_CFG_STOP_ON_ERR_EN_MASK (\89 (FIELD_PREP(TPC0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_MASK, 0xF)) | \90 (FIELD_PREP(TPC0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_MASK, 0x1F)) | \91 (FIELD_PREP(TPC0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_MASK, 0x1F)) | \92 (FIELD_PREP(TPC0_QM_GLBL_ERR_CFG_ARB_STOP_ON_ERR_MASK, 0x1)))93 94#define MME_QMAN_GLBL_ERR_CFG_MSG_EN_MASK (\95 (FIELD_PREP(MME0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_MASK, 0xF)) | \96 (FIELD_PREP(MME0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_MASK, 0x1F)) | \97 (FIELD_PREP(MME0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_MASK, 0x1F)))98 99#define MME_QMAN_GLBL_ERR_CFG_STOP_ON_ERR_EN_MASK (\100 (FIELD_PREP(MME0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_MASK, 0xF)) | \101 (FIELD_PREP(MME0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_MASK, 0x1F)) | \102 (FIELD_PREP(MME0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_MASK, 0x1F)) | \103 (FIELD_PREP(MME0_QM_GLBL_ERR_CFG_ARB_STOP_ON_ERR_MASK, 0x1)))104 105#define NIC_QMAN_GLBL_ERR_CFG_MSG_EN_MASK (\106 (FIELD_PREP(NIC0_QM0_GLBL_ERR_CFG_PQF_ERR_MSG_EN_MASK, 0xF)) | \107 (FIELD_PREP(NIC0_QM0_GLBL_ERR_CFG_CQF_ERR_MSG_EN_MASK, 0xF)) | \108 (FIELD_PREP(NIC0_QM0_GLBL_ERR_CFG_CP_ERR_MSG_EN_MASK, 0xF)))109 110#define NIC_QMAN_GLBL_ERR_CFG_STOP_ON_ERR_EN_MASK (\111 (FIELD_PREP(NIC0_QM0_GLBL_ERR_CFG_PQF_STOP_ON_ERR_MASK, 0xF)) | \112 (FIELD_PREP(NIC0_QM0_GLBL_ERR_CFG_CQF_STOP_ON_ERR_MASK, 0xF)) | \113 (FIELD_PREP(NIC0_QM0_GLBL_ERR_CFG_CP_STOP_ON_ERR_MASK, 0xF)) | \114 (FIELD_PREP(NIC0_QM0_GLBL_ERR_CFG_ARB_STOP_ON_ERR_MASK, 0x1)))115 116#define QMAN_CGM1_PWR_GATE_EN (FIELD_PREP(DMA0_QM_CGM_CFG1_MASK_TH_MASK, 0xA))117 118/* RESET registers configuration */119#define CFG_RST_L_PSOC_MASK BIT_MASK(0)120#define CFG_RST_L_PCIE_MASK BIT_MASK(1)121#define CFG_RST_L_PCIE_IF_MASK BIT_MASK(2)122#define CFG_RST_L_HBM_S_PLL_MASK BIT_MASK(3)123#define CFG_RST_L_TPC_S_PLL_MASK BIT_MASK(4)124#define CFG_RST_L_MME_S_PLL_MASK BIT_MASK(5)125#define CFG_RST_L_CPU_PLL_MASK BIT_MASK(6)126#define CFG_RST_L_PCIE_PLL_MASK BIT_MASK(7)127#define CFG_RST_L_NIC_S_PLL_MASK BIT_MASK(8)128#define CFG_RST_L_HBM_N_PLL_MASK BIT_MASK(9)129#define CFG_RST_L_TPC_N_PLL_MASK BIT_MASK(10)130#define CFG_RST_L_MME_N_PLL_MASK BIT_MASK(11)131#define CFG_RST_L_NIC_N_PLL_MASK BIT_MASK(12)132#define CFG_RST_L_DMA_W_PLL_MASK BIT_MASK(13)133#define CFG_RST_L_SIF_W_PLL_MASK BIT_MASK(14)134#define CFG_RST_L_MESH_W_PLL_MASK BIT_MASK(15)135#define CFG_RST_L_SRAM_W_PLL_MASK BIT_MASK(16)136#define CFG_RST_L_DMA_E_PLL_MASK BIT_MASK(17)137#define CFG_RST_L_SIF_E_PLL_MASK BIT_MASK(18)138#define CFG_RST_L_MESH_E_PLL_MASK BIT_MASK(19)139#define CFG_RST_L_SRAM_E_PLL_MASK BIT_MASK(20)140 141#define CFG_RST_L_IF_1_MASK BIT_MASK(21)142#define CFG_RST_L_IF_0_MASK BIT_MASK(22)143#define CFG_RST_L_IF_2_MASK BIT_MASK(23)144#define CFG_RST_L_IF_3_MASK BIT_MASK(24)145#define CFG_RST_L_IF_MASK GENMASK(24, 21)146 147#define CFG_RST_L_TPC_0_MASK BIT_MASK(25)148#define CFG_RST_L_TPC_1_MASK BIT_MASK(26)149#define CFG_RST_L_TPC_2_MASK BIT_MASK(27)150#define CFG_RST_L_TPC_3_MASK BIT_MASK(28)151#define CFG_RST_L_TPC_4_MASK BIT_MASK(29)152#define CFG_RST_L_TPC_5_MASK BIT_MASK(30)153#define CFG_RST_L_TPC_6_MASK BIT_MASK(31)154#define CFG_RST_L_TPC_MASK GENMASK(31, 25)155 156#define CFG_RST_H_TPC_7_MASK BIT_MASK(0)157 158#define CFG_RST_H_MME_0_MASK BIT_MASK(1)159#define CFG_RST_H_MME_1_MASK BIT_MASK(2)160#define CFG_RST_H_MME_2_MASK BIT_MASK(3)161#define CFG_RST_H_MME_3_MASK BIT_MASK(4)162#define CFG_RST_H_MME_MASK GENMASK(4, 1)163 164#define CFG_RST_H_HBM_0_MASK BIT_MASK(5)165#define CFG_RST_H_HBM_1_MASK BIT_MASK(6)166#define CFG_RST_H_HBM_2_MASK BIT_MASK(7)167#define CFG_RST_H_HBM_3_MASK BIT_MASK(8)168#define CFG_RST_H_HBM_MASK GENMASK(8, 5)169 170#define CFG_RST_H_NIC_0_MASK BIT_MASK(9)171#define CFG_RST_H_NIC_1_MASK BIT_MASK(10)172#define CFG_RST_H_NIC_2_MASK BIT_MASK(11)173#define CFG_RST_H_NIC_3_MASK BIT_MASK(12)174#define CFG_RST_H_NIC_4_MASK BIT_MASK(13)175#define CFG_RST_H_NIC_MASK GENMASK(13, 9)176 177#define CFG_RST_H_SM_0_MASK BIT_MASK(14)178#define CFG_RST_H_SM_1_MASK BIT_MASK(15)179#define CFG_RST_H_SM_2_MASK BIT_MASK(16)180#define CFG_RST_H_SM_3_MASK BIT_MASK(17)181#define CFG_RST_H_SM_MASK GENMASK(17, 14)182 183#define CFG_RST_H_DMA_0_MASK BIT_MASK(18)184#define CFG_RST_H_DMA_1_MASK BIT_MASK(19)185#define CFG_RST_H_DMA_MASK GENMASK(19, 18)186 187#define CFG_RST_H_CPU_MASK BIT_MASK(20)188#define CFG_RST_H_MMU_MASK BIT_MASK(21)189 190#define UNIT_RST_L_PSOC_SHIFT 0191#define UNIT_RST_L_PCIE_SHIFT 1192#define UNIT_RST_L_PCIE_IF_SHIFT 2193#define UNIT_RST_L_HBM_S_PLL_SHIFT 3194#define UNIT_RST_L_TPC_S_PLL_SHIFT 4195#define UNIT_RST_L_MME_S_PLL_SHIFT 5196#define UNIT_RST_L_CPU_PLL_SHIFT 6197#define UNIT_RST_L_PCIE_PLL_SHIFT 7198#define UNIT_RST_L_NIC_S_PLL_SHIFT 8199#define UNIT_RST_L_HBM_N_PLL_SHIFT 9200#define UNIT_RST_L_TPC_N_PLL_SHIFT 10201#define UNIT_RST_L_MME_N_PLL_SHIFT 11202#define UNIT_RST_L_NIC_N_PLL_SHIFT 12203#define UNIT_RST_L_DMA_W_PLL_SHIFT 13204#define UNIT_RST_L_SIF_W_PLL_SHIFT 14205#define UNIT_RST_L_MESH_W_PLL_SHIFT 15206#define UNIT_RST_L_SRAM_W_PLL_SHIFT 16207#define UNIT_RST_L_DMA_E_PLL_SHIFT 17208#define UNIT_RST_L_SIF_E_PLL_SHIFT 18209#define UNIT_RST_L_MESH_E_PLL_SHIFT 19210#define UNIT_RST_L_SRAM_E_PLL_SHIFT 20211#define UNIT_RST_L_TPC_0_SHIFT 21212#define UNIT_RST_L_TPC_1_SHIFT 22213#define UNIT_RST_L_TPC_2_SHIFT 23214#define UNIT_RST_L_TPC_3_SHIFT 24215#define UNIT_RST_L_TPC_4_SHIFT 25216#define UNIT_RST_L_TPC_5_SHIFT 26217#define UNIT_RST_L_TPC_6_SHIFT 27218#define UNIT_RST_L_TPC_7_SHIFT 28219#define UNIT_RST_L_MME_0_SHIFT 29220#define UNIT_RST_L_MME_1_SHIFT 30221#define UNIT_RST_L_MME_2_SHIFT 31222 223#define UNIT_RST_H_MME_3_SHIFT 0224#define UNIT_RST_H_HBM_0_SHIFT 1225#define UNIT_RST_H_HBM_1_SHIFT 2226#define UNIT_RST_H_HBM_2_SHIFT 3227#define UNIT_RST_H_HBM_3_SHIFT 4228#define UNIT_RST_H_NIC_0_SHIFT 5229#define UNIT_RST_H_NIC_1_SHIFT 6230#define UNIT_RST_H_NIC_2_SHIFT 7231#define UNIT_RST_H_NIC_3_SHIFT 8232#define UNIT_RST_H_NIC_4_SHIFT 9233#define UNIT_RST_H_SM_0_SHIFT 10234#define UNIT_RST_H_SM_1_SHIFT 11235#define UNIT_RST_H_SM_2_SHIFT 12236#define UNIT_RST_H_SM_3_SHIFT 13237#define UNIT_RST_H_IF_0_SHIFT 14238#define UNIT_RST_H_IF_1_SHIFT 15239#define UNIT_RST_H_IF_2_SHIFT 16240#define UNIT_RST_H_IF_3_SHIFT 17241#define UNIT_RST_H_DMA_0_SHIFT 18242#define UNIT_RST_H_DMA_1_SHIFT 19243#define UNIT_RST_H_CPU_SHIFT 20244#define UNIT_RST_H_MMU_SHIFT 21245 246#define UNIT_RST_H_HBM_MASK ((1 << UNIT_RST_H_HBM_0_SHIFT) | \247 (1 << UNIT_RST_H_HBM_1_SHIFT) | \248 (1 << UNIT_RST_H_HBM_2_SHIFT) | \249 (1 << UNIT_RST_H_HBM_3_SHIFT))250 251#define UNIT_RST_H_NIC_MASK ((1 << UNIT_RST_H_NIC_0_SHIFT) | \252 (1 << UNIT_RST_H_NIC_1_SHIFT) | \253 (1 << UNIT_RST_H_NIC_2_SHIFT) | \254 (1 << UNIT_RST_H_NIC_3_SHIFT) | \255 (1 << UNIT_RST_H_NIC_4_SHIFT))256 257#define UNIT_RST_H_SM_MASK ((1 << UNIT_RST_H_SM_0_SHIFT) | \258 (1 << UNIT_RST_H_SM_1_SHIFT) | \259 (1 << UNIT_RST_H_SM_2_SHIFT) | \260 (1 << UNIT_RST_H_SM_3_SHIFT))261 262#define UNIT_RST_H_MME_MASK ((1 << UNIT_RST_H_MME_0_SHIFT) | \263 (1 << UNIT_RST_H_MME_1_SHIFT) | \264 (1 << UNIT_RST_H_MME_2_SHIFT))265 266#define UNIT_RST_L_MME_MASK (1 << UNIT_RST_L_MME_3_SHIFT)267 268#define UNIT_RST_L_IF_MASK ((1 << UNIT_RST_L_IF_0_SHIFT) | \269 (1 << UNIT_RST_L_IF_1_SHIFT) | \270 (1 << UNIT_RST_L_IF_2_SHIFT) | \271 (1 << UNIT_RST_L_IF_3_SHIFT))272 273#define UNIT_RST_L_TPC_MASK ((1 << UNIT_RST_L_TPC_0_SHIFT) | \274 (1 << UNIT_RST_L_TPC_1_SHIFT) | \275 (1 << UNIT_RST_L_TPC_2_SHIFT) | \276 (1 << UNIT_RST_L_TPC_3_SHIFT) | \277 (1 << UNIT_RST_L_TPC_4_SHIFT) | \278 (1 << UNIT_RST_L_TPC_5_SHIFT) | \279 (1 << UNIT_RST_L_TPC_6_SHIFT) | \280 (1 << UNIT_RST_L_TPC_7_SHIFT))281 282/* CPU_CA53_CFG_ARM_RST_CONTROL */283#define CPU_CA53_CFG_ARM_RST_CONTROL_NCPUPORESET_SHIFT 0284#define CPU_CA53_CFG_ARM_RST_CONTROL_NCPUPORESET_MASK 0x3285#define CPU_CA53_CFG_ARM_RST_CONTROL_NCORERESET_SHIFT 4286#define CPU_CA53_CFG_ARM_RST_CONTROL_NCORERESET_MASK 0x30287#define CPU_CA53_CFG_ARM_RST_CONTROL_NL2RESET_SHIFT 8288#define CPU_CA53_CFG_ARM_RST_CONTROL_NL2RESET_MASK 0x100289#define CPU_CA53_CFG_ARM_RST_CONTROL_NPRESETDBG_SHIFT 12290#define CPU_CA53_CFG_ARM_RST_CONTROL_NPRESETDBG_MASK 0x1000291#define CPU_CA53_CFG_ARM_RST_CONTROL_NMBISTRESET_SHIFT 16292#define CPU_CA53_CFG_ARM_RST_CONTROL_NMBISTRESET_MASK 0x10000293#define CPU_CA53_CFG_ARM_RST_CONTROL_WARMRSTREQ_SHIFT 20294#define CPU_CA53_CFG_ARM_RST_CONTROL_WARMRSTREQ_MASK 0x300000295 296#define CPU_RESET_ASSERT (\297 1 << CPU_CA53_CFG_ARM_RST_CONTROL_NMBISTRESET_SHIFT)298 299#define CPU_RESET_CORE0_DEASSERT (\300 1 << CPU_CA53_CFG_ARM_RST_CONTROL_NCPUPORESET_SHIFT |\301 1 << CPU_CA53_CFG_ARM_RST_CONTROL_NCORERESET_SHIFT |\302 1 << CPU_CA53_CFG_ARM_RST_CONTROL_NL2RESET_SHIFT |\303 1 << CPU_CA53_CFG_ARM_RST_CONTROL_NMBISTRESET_SHIFT)304 305/* QM_IDLE_MASK is valid for all engines QM idle check */306#define QM_IDLE_MASK (DMA0_QM_GLBL_STS0_PQF_IDLE_MASK | \307 DMA0_QM_GLBL_STS0_CQF_IDLE_MASK | \308 DMA0_QM_GLBL_STS0_CP_IDLE_MASK)309 310/* CGM_IDLE_MASK is valid for all engines CGM idle check */311#define CGM_IDLE_MASK DMA0_QM_CGM_STS_AGENT_IDLE_MASK312 313#define TPC_IDLE_MASK ((1 << TPC0_CFG_STATUS_SCALAR_PIPE_EMPTY_SHIFT) | \314 (1 << TPC0_CFG_STATUS_VECTOR_PIPE_EMPTY_SHIFT) | \315 (1 << TPC0_CFG_STATUS_IQ_EMPTY_SHIFT) | \316 (1 << TPC0_CFG_STATUS_SB_EMPTY_SHIFT) | \317 (1 << TPC0_CFG_STATUS_QM_IDLE_SHIFT) | \318 (1 << TPC0_CFG_STATUS_QM_RDY_SHIFT))319 320#define MME0_CTRL_ARCH_STATUS_SB_A_EMPTY_MASK 0x80321#define MME0_CTRL_ARCH_STATUS_SB_B_EMPTY_MASK 0x100322#define MME0_CTRL_ARCH_STATUS_WBC_AXI_IDLE_MASK 0x1000323 324#define MME_ARCH_IDLE_MASK (MME0_CTRL_ARCH_STATUS_SB_A_EMPTY_MASK | \325 MME0_CTRL_ARCH_STATUS_SB_B_EMPTY_MASK | \326 MME0_CTRL_ARCH_STATUS_WBC_AXI_IDLE_MASK)327 328#define IS_QM_IDLE(qm_glbl_sts0, qm_cgm_sts) \329 ((((qm_glbl_sts0) & QM_IDLE_MASK) == QM_IDLE_MASK) && \330 (((qm_cgm_sts) & CGM_IDLE_MASK) == CGM_IDLE_MASK))331 332#define IS_DMA_IDLE(dma_core_sts0) \333 !(dma_core_sts0 & DMA0_CORE_STS0_BUSY_MASK)334 335#define IS_TPC_IDLE(tpc_cfg_sts) \336 (((tpc_cfg_sts) & TPC_IDLE_MASK) == TPC_IDLE_MASK)337 338#define IS_MME_IDLE(mme_arch_sts) \339 (((mme_arch_sts) & MME_ARCH_IDLE_MASK) == MME_ARCH_IDLE_MASK)340 341enum axi_id {342 AXI_ID_MME,343 AXI_ID_TPC,344 AXI_ID_DMA,345 AXI_ID_NIC, /* Local NIC */346 AXI_ID_PCI,347 AXI_ID_CPU,348 AXI_ID_PSOC,349 AXI_ID_MMU,350 AXI_ID_NIC_FT /* Feed-Through NIC */351};352 353/* RAZWI initiator ID is built from the location in the chip and the AXI ID */354 355#define RAZWI_INITIATOR_AXI_ID_SHIFT 20356#define RAZWI_INITIATOR_AXI_ID_MASK 0xF357#define RAZWI_INITIATOR_X_SHIFT 24358#define RAZWI_INITIATOR_X_MASK 0xF359#define RAZWI_INITIATOR_Y_SHIFT 28360#define RAZWI_INITIATOR_Y_MASK 0x7361 362#define RAZWI_INITIATOR_ID_AXI_ID(axi_id) \363 (((axi_id) & RAZWI_INITIATOR_AXI_ID_MASK) << \364 RAZWI_INITIATOR_AXI_ID_SHIFT)365 366#define RAZWI_INITIATOR_ID_X_Y(x, y) \367 ((((y) & RAZWI_INITIATOR_Y_MASK) << RAZWI_INITIATOR_Y_SHIFT) | \368 (((x) & RAZWI_INITIATOR_X_MASK) << RAZWI_INITIATOR_X_SHIFT))369 370#define RAZWI_INITIATOR_ID_X_Y_TPC0_NIC0 RAZWI_INITIATOR_ID_X_Y(1, 1)371#define RAZWI_INITIATOR_ID_X_Y_TPC1 RAZWI_INITIATOR_ID_X_Y(2, 1)372#define RAZWI_INITIATOR_ID_X_Y_MME0_0 RAZWI_INITIATOR_ID_X_Y(3, 1)373#define RAZWI_INITIATOR_ID_X_Y_MME0_1 RAZWI_INITIATOR_ID_X_Y(4, 1)374#define RAZWI_INITIATOR_ID_X_Y_MME1_0 RAZWI_INITIATOR_ID_X_Y(5, 1)375#define RAZWI_INITIATOR_ID_X_Y_MME1_1 RAZWI_INITIATOR_ID_X_Y(6, 1)376#define RAZWI_INITIATOR_ID_X_Y_TPC2 RAZWI_INITIATOR_ID_X_Y(7, 1)377#define RAZWI_INITIATOR_ID_X_Y_TPC3_PCI_CPU_PSOC \378 RAZWI_INITIATOR_ID_X_Y(8, 1)379#define RAZWI_INITIATOR_ID_X_Y_DMA_IF_W_S_0 RAZWI_INITIATOR_ID_X_Y(0, 1)380#define RAZWI_INITIATOR_ID_X_Y_DMA_IF_E_S_0 RAZWI_INITIATOR_ID_X_Y(9, 1)381#define RAZWI_INITIATOR_ID_X_Y_DMA_IF_W_S_1 RAZWI_INITIATOR_ID_X_Y(0, 2)382#define RAZWI_INITIATOR_ID_X_Y_DMA_IF_E_S_1 RAZWI_INITIATOR_ID_X_Y(9, 2)383#define RAZWI_INITIATOR_ID_X_Y_DMA_IF_W_N_0 RAZWI_INITIATOR_ID_X_Y(0, 3)384#define RAZWI_INITIATOR_ID_X_Y_DMA_IF_E_N_0 RAZWI_INITIATOR_ID_X_Y(9, 3)385#define RAZWI_INITIATOR_ID_X_Y_DMA_IF_W_N_1 RAZWI_INITIATOR_ID_X_Y(0, 4)386#define RAZWI_INITIATOR_ID_X_Y_DMA_IF_E_N_1 RAZWI_INITIATOR_ID_X_Y(9, 4)387#define RAZWI_INITIATOR_ID_X_Y_TPC4_NIC1_NIC2 RAZWI_INITIATOR_ID_X_Y(1, 6)388#define RAZWI_INITIATOR_ID_X_Y_TPC5 RAZWI_INITIATOR_ID_X_Y(2, 6)389#define RAZWI_INITIATOR_ID_X_Y_MME2_0 RAZWI_INITIATOR_ID_X_Y(3, 6)390#define RAZWI_INITIATOR_ID_X_Y_MME2_1 RAZWI_INITIATOR_ID_X_Y(4, 6)391#define RAZWI_INITIATOR_ID_X_Y_MME3_0 RAZWI_INITIATOR_ID_X_Y(5, 6)392#define RAZWI_INITIATOR_ID_X_Y_MME3_1 RAZWI_INITIATOR_ID_X_Y(6, 6)393#define RAZWI_INITIATOR_ID_X_Y_TPC6 RAZWI_INITIATOR_ID_X_Y(7, 6)394#define RAZWI_INITIATOR_ID_X_Y_TPC7_NIC4_NIC5 RAZWI_INITIATOR_ID_X_Y(8, 6)395 396#define PSOC_ETR_AXICTL_PROTCTRLBIT1_SHIFT 1397#define PSOC_ETR_AXICTL_PROTCTRLBIT0_MASK 0x1398#define PSOC_ETR_AXICTL_PROTCTRLBIT1_MASK 0x2399#define PSOC_ETR_AXICTL_WRBURSTLEN_MASK 0xF00400 401/* STLB_CACHE_INV */402#define STLB_CACHE_INV_PRODUCER_INDEX_SHIFT 0403#define STLB_CACHE_INV_PRODUCER_INDEX_MASK 0xFF404#define STLB_CACHE_INV_INDEX_MASK_SHIFT 8405#define STLB_CACHE_INV_INDEX_MASK_MASK 0xFF00406 407#define MME_ACC_ACC_STALL_R_SHIFT 0408#define MME_SBAB_SB_STALL_R_SHIFT 0409 410#define PCIE_WRAP_LBW_PROT_OVR_RD_EN_MASK 0x700411#define PCIE_WRAP_LBW_PROT_OVR_WR_EN_MASK 0x7000412 413#define PCIE_WRAP_LBW_DRAIN_CFG_EN_SHIFT 0414#define PCIE_WRAP_HBW_DRAIN_CFG_EN_SHIFT 0415 416/* DMA_IF_HBM_CRED_EN */417#define DMA_IF_HBM_CRED_EN_READ_CREDIT_EN_SHIFT 0418#define DMA_IF_HBM_CRED_EN_READ_CREDIT_EN_MASK 0x1419#define DMA_IF_HBM_CRED_EN_WRITE_CREDIT_EN_SHIFT 1420#define DMA_IF_HBM_CRED_EN_WRITE_CREDIT_EN_MASK 0x2421 422#define DMA_IF_DOWN_CHX_SCRAM_SRAM_EN_VAL_SHIFT 0423#define DMA_IF_DOWN_CHX_SCRAM_HBM_EN_VAL_SHIFT 0424#define DMA_IF_DOWN_CHX_E2E_HBM_EN_VAL_SHIFT 0425#define DMA_IF_DOWN_CHX_E2E_PCI_EN_VAL_SHIFT 0426 427#define IF_RTR_CTRL_SCRAM_SRAM_EN_VAL_SHIFT 0428#define IF_RTR_CTRL_SCRAM_HBM_EN_VAL_SHIFT 0429 430#define IF_RTR_CTRL_E2E_HBM_EN_VAL_SHIFT 0431#define IF_RTR_CTRL_E2E_PCI_EN_VAL_SHIFT 0432 433/* MMU_UP_PAGE_ERROR_CAPTURE */434#define MMU_UP_PAGE_ERROR_CAPTURE_VA_49_32_MASK 0x3FFFF435#define MMU_UP_PAGE_ERROR_CAPTURE_ENTRY_VALID_MASK 0x40000436 437/* MMU_UP_ACCESS_ERROR_CAPTURE */438#define MMU_UP_ACCESS_ERROR_CAPTURE_VA_49_32_MASK 0x3FFFF439#define MMU_UP_ACCESS_ERROR_CAPTURE_ENTRY_VALID_MASK 0x40000440 441#define QM_ARB_ERR_MSG_EN_CHOISE_OVF_MASK 0x1442#define QM_ARB_ERR_MSG_EN_CHOISE_WDT_MASK 0x2443#define QM_ARB_ERR_MSG_EN_AXI_LBW_ERR_MASK 0x4444 445#define QM_ARB_ERR_MSG_EN_MASK (\446 QM_ARB_ERR_MSG_EN_CHOISE_OVF_MASK |\447 QM_ARB_ERR_MSG_EN_CHOISE_WDT_MASK |\448 QM_ARB_ERR_MSG_EN_AXI_LBW_ERR_MASK)449 450#define PCIE_AUX_FLR_CTRL_HW_CTRL_MASK 0x1451#define PCIE_AUX_FLR_CTRL_INT_MASK_MASK 0x2452 453#define SYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_STATUS_0_VALID_SHIFT 0454#define SYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_STATUS_0_VALID_MASK 0x1455#define SYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_STATUS_0_PENDING_SHIFT 1456#define SYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_STATUS_0_PENDING_MASK 0x1FE457#define SYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_ARM_0_SID_SHIFT 0458#define SYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_ARM_0_SID_MASK 0xFF459#define SYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_ARM_0_MASK_SHIFT 8460#define SYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_ARM_0_MASK_MASK 0xFF00461#define SYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_ARM_0_SOP_SHIFT 16462#define SYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_ARM_0_SOP_MASK 0x10000463#define SYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_ARM_0_SOD_SHIFT 17464#define SYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_ARM_0_SOD_MASK 0xFFFE0000465#define TPC0_QM_CP_STS_0_FENCE_ID_SHIFT 20466#define TPC0_QM_CP_STS_0_FENCE_ID_MASK 0x300000467#define TPC0_QM_CP_STS_0_FENCE_IN_PROGRESS_SHIFT 22468#define TPC0_QM_CP_STS_0_FENCE_IN_PROGRESS_MASK 0x400000469 470#endif /* GAUDI_MASKS_H_ */471