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1/* SPDX-License-Identifier: GPL-2.02 *3 * Copyright 2016-2020 HabanaLabs, Ltd.4 * All Rights Reserved.5 *6 */7 8/************************************9 ** This is an auto-generated file **10 ** DO NOT EDIT BELOW **11 ************************************/12 13#ifndef ASIC_REG_CPU_IF_REGS_H_14#define ASIC_REG_CPU_IF_REGS_H_15 16/*17 *****************************************18 * CPU_IF19 * (Prototype: CPU_IF)20 *****************************************21 */22 23#define mmCPU_IF_ARUSER_OVR 0x4CC110424 25#define mmCPU_IF_ARUSER_OVR_EN 0x4CC110826 27#define mmCPU_IF_AWUSER_OVR 0x4CC110C28 29#define mmCPU_IF_AWUSER_OVR_EN 0x4CC111030 31#define mmCPU_IF_ARUSER_MSB_OVR 0x4CC111432 33#define mmCPU_IF_AWUSER_MSB_OVR 0x4CC112034 35#define mmCPU_IF_AXCACHE_OVR 0x4CC112836 37#define mmCPU_IF_LOCK_OVR 0x4CC112C38 39#define mmCPU_IF_PROT_OVR 0x4CC113040 41#define mmCPU_IF_MAX_OUTSTANDING 0x4CC113442 43#define mmCPU_IF_EARLY_BRESP_EN 0x4CC113844 45#define mmCPU_IF_FORCE_RSP_OK 0x4CC113C46 47#define mmCPU_IF_CPU_SEI_INTR_STS 0x4CC114048 49#define mmCPU_IF_CPU_SEI_INTR_CLR 0x4CC114450 51#define mmCPU_IF_CPU_SEI_INTR_MASK 0x4CC114852 53#define mmCPU_IF_AXI_SPLIT_NO_WR_INFLIGHT 0x4CC114C54 55#define mmCPU_IF_AXI_SPLIT_SEI_INTR_ID 0x4CC115056 57#define mmCPU_IF_TOTAL_WR_CNT 0x4CC115458 59#define mmCPU_IF_INFLIGHT_WR_CNT 0x4CC115860 61#define mmCPU_IF_TOTAL_RD_CNT 0x4CC115C62 63#define mmCPU_IF_INFLIGHT_RD_CNT 0x4CC116064 65#define mmCPU_IF_SRAM_MSB_ADDR 0x4CC116466 67#define mmCPU_IF_CFG_MSB_ADDR 0x4CC116868 69#define mmCPU_IF_HBM_MSB_ADDR 0x4CC116C70 71#define mmCPU_IF_PCIE_MSB_ADDR 0x4CC117072 73#define mmCPU_IF_KMD_HW_DIRTY_STATUS 0x4CC117474 75#define mmCPU_IF_MSTR_IF_E2E_FORCE_BP 0x4CC118876 77#define mmCPU_IF_MSTR_IF_E2E_GRCFL_CLR 0x4CC118C78 79#define mmCPU_IF_LBW_TERMINATE_AWADDR_ERR 0x4CC11A080 81#define mmCPU_IF_LBW_TERMINATE_ARADDR_ERR 0x4CC11A482 83#define mmCPU_IF_CFG_LBW_TERMINATE_BRESP 0x4CC11A884 85#define mmCPU_IF_CFG_LBW_TERMINATE_RRESP 0x4CC11AC86 87#define mmCPU_IF_PF_PQ_PI 0x4CC120088 89#define mmCPU_IF_PQ_BASE_ADDR_LOW 0x4CC120490 91#define mmCPU_IF_PQ_BASE_ADDR_HIGH 0x4CC120892 93#define mmCPU_IF_PQ_LENGTH 0x4CC120C94 95#define mmCPU_IF_CQ_BASE_ADDR_LOW 0x4CC121096 97#define mmCPU_IF_CQ_BASE_ADDR_HIGH 0x4CC121498 99#define mmCPU_IF_CQ_LENGTH 0x4CC1218100 101#define mmCPU_IF_EQ_BASE_ADDR_LOW 0x4CC1220102 103#define mmCPU_IF_EQ_BASE_ADDR_HIGH 0x4CC1224104 105#define mmCPU_IF_EQ_LENGTH 0x4CC1228106 107#define mmCPU_IF_EQ_RD_OFFS 0x4CC122C108 109#define mmCPU_IF_QUEUE_INIT 0x4CC1230110 111#define mmCPU_IF_TPC_SERR_INTR_STS 0x4CC1300112 113#define mmCPU_IF_TPC_SERR_INTR_CLR 0x4CC1304114 115#define mmCPU_IF_TPC_SERR_INTR_MASK 0x4CC1308116 117#define mmCPU_IF_TPC_DERR_INTR_STS 0x4CC1310118 119#define mmCPU_IF_TPC_DERR_INTR_CLR 0x4CC1314120 121#define mmCPU_IF_TPC_DERR_INTR_MASK 0x4CC1318122 123#define mmCPU_IF_MME_SERR_INTR_STS_0 0x4CC1320124 125#define mmCPU_IF_MME_SERR_INTR_STS_1 0x4CC1324126 127#define mmCPU_IF_MME_SERR_INTR_STS_2 0x4CC1328128 129#define mmCPU_IF_MME_SERR_INTR_STS_3 0x4CC132C130 131#define mmCPU_IF_MME_SERR_INTR_CLR_0 0x4CC1330132 133#define mmCPU_IF_MME_SERR_INTR_CLR_1 0x4CC1334134 135#define mmCPU_IF_MME_SERR_INTR_CLR_2 0x4CC1338136 137#define mmCPU_IF_MME_SERR_INTR_CLR_3 0x4CC133C138 139#define mmCPU_IF_MME_SERR_INTR_MASK_0 0x4CC1340140 141#define mmCPU_IF_MME_SERR_INTR_MASK_1 0x4CC1344142 143#define mmCPU_IF_MME_SERR_INTR_MASK_2 0x4CC1348144 145#define mmCPU_IF_MME_SERR_INTR_MASK_3 0x4CC134C146 147#define mmCPU_IF_MME_DERR_INTR_STS_0 0x4CC1350148 149#define mmCPU_IF_MME_DERR_INTR_STS_1 0x4CC1354150 151#define mmCPU_IF_MME_DERR_INTR_STS_2 0x4CC1358152 153#define mmCPU_IF_MME_DERR_INTR_STS_3 0x4CC135C154 155#define mmCPU_IF_MME_DERR_INTR_CLR_0 0x4CC1360156 157#define mmCPU_IF_MME_DERR_INTR_CLR_1 0x4CC1364158 159#define mmCPU_IF_MME_DERR_INTR_CLR_2 0x4CC1368160 161#define mmCPU_IF_MME_DERR_INTR_CLR_3 0x4CC136C162 163#define mmCPU_IF_MME_DERR_INTR_MASK_0 0x4CC1370164 165#define mmCPU_IF_MME_DERR_INTR_MASK_1 0x4CC1374166 167#define mmCPU_IF_MME_DERR_INTR_MASK_2 0x4CC1378168 169#define mmCPU_IF_MME_DERR_INTR_MASK_3 0x4CC137C170 171#define mmCPU_IF_HDMA_SERR_INTR_STS 0x4CC1380172 173#define mmCPU_IF_HDMA_SERR_INTR_CLR 0x4CC1384174 175#define mmCPU_IF_HDMA_SERR_INTR_MASK 0x4CC1388176 177#define mmCPU_IF_HDMA_DERR_INTR_STS 0x4CC1390178 179#define mmCPU_IF_HDMA_DERR_INTR_CLR 0x4CC1394180 181#define mmCPU_IF_HDMA_DERR_INTR_MASK 0x4CC1398182 183#define mmCPU_IF_PDMA_SERR_INTR_STS 0x4CC13A0184 185#define mmCPU_IF_PDMA_SERR_INTR_CLR 0x4CC13A4186 187#define mmCPU_IF_PDMA_SERR_INTR_MASK 0x4CC13A8188 189#define mmCPU_IF_PDMA_DERR_INTR_STS 0x4CC13B0190 191#define mmCPU_IF_PDMA_DERR_INTR_CLR 0x4CC13B4192 193#define mmCPU_IF_PDMA_DERR_INTR_MASK 0x4CC13B8194 195#define mmCPU_IF_SRAM_SERR_INTR_STS 0x4CC13C0196 197#define mmCPU_IF_SRAM_SERR_INTR_CLR 0x4CC13C4198 199#define mmCPU_IF_SRAM_SERR_INTR_MASK 0x4CC13C8200 201#define mmCPU_IF_SRAM_DERR_INTR_STS 0x4CC13D0202 203#define mmCPU_IF_SRAM_DERR_INTR_CLR 0x4CC13D4204 205#define mmCPU_IF_SRAM_DERR_INTR_MASK 0x4CC13D8206 207#define mmCPU_IF_HBM_SERR_INTR_STS 0x4CC13E0208 209#define mmCPU_IF_HBM_SERR_INTR_CLR 0x4CC13E4210 211#define mmCPU_IF_HBM_SERR_INTR_MASK 0x4CC13E8212 213#define mmCPU_IF_HBM_DERR_INTR_STS 0x4CC13F0214 215#define mmCPU_IF_HBM_DERR_INTR_CLR 0x4CC13F4216 217#define mmCPU_IF_HBM_DERR_INTR_MASK 0x4CC13F8218 219#define mmCPU_IF_HMMU_SERR_INTR_STS 0x4CC1400220 221#define mmCPU_IF_HMMU_SERR_INTR_CLR 0x4CC1404222 223#define mmCPU_IF_HMMU_SERR_INTR_MASK 0x4CC1408224 225#define mmCPU_IF_HMMU_DERR_INTR_STS 0x4CC1410226 227#define mmCPU_IF_HMMU_DERR_INTR_CLR 0x4CC1414228 229#define mmCPU_IF_HMMU_DERR_INTR_MASK 0x4CC1418230 231#define mmCPU_IF_DEC_SERR_INTR_STS 0x4CC1420232 233#define mmCPU_IF_DEC_SERR_INTR_CLR 0x4CC1424234 235#define mmCPU_IF_DEC_SERR_INTR_MASK 0x4CC1428236 237#define mmCPU_IF_DEC_DERR_INTR_STS 0x4CC1430238 239#define mmCPU_IF_DEC_DERR_INTR_CLR 0x4CC1434240 241#define mmCPU_IF_DEC_DERR_INTR_MASK 0x4CC1438242 243#define mmCPU_IF_NIC_SERR_INTR_STS 0x4CC1440244 245#define mmCPU_IF_NIC_SERR_INTR_CLR 0x4CC1444246 247#define mmCPU_IF_NIC_SERR_INTR_MASK 0x4CC1448248 249#define mmCPU_IF_NIC_DERR_INTR_STS 0x4CC1450250 251#define mmCPU_IF_NIC_DERR_INTR_CLR 0x4CC1454252 253#define mmCPU_IF_NIC_DERR_INTR_MASK 0x4CC1458254 255#define mmCPU_IF_SYNC_MNGR_SERR_INTR_STS 0x4CC1460256 257#define mmCPU_IF_SYNC_MNGR_SERR_INTR_CLR 0x4CC1464258 259#define mmCPU_IF_SYNC_MNGR_SERR_INTR_MASK 0x4CC1468260 261#define mmCPU_IF_SYNC_MNGR_DERR_INTR_STS 0x4CC1470262 263#define mmCPU_IF_SYNC_MNGR_DERR_INTR_CLR 0x4CC1474264 265#define mmCPU_IF_SYNC_MNGR_DERR_INTR_MASK 0x4CC1478266 267#define mmCPU_IF_HIF_SERR_INTR_STS 0x4CC1480268 269#define mmCPU_IF_HIF_SERR_INTR_CLR 0x4CC1484270 271#define mmCPU_IF_HIF_SERR_INTR_MASK 0x4CC1488272 273#define mmCPU_IF_HIF_DERR_INTR_STS 0x4CC1490274 275#define mmCPU_IF_HIF_DERR_INTR_CLR 0x4CC1494276 277#define mmCPU_IF_HIF_DERR_INTR_MASK 0x4CC1498278 279#define mmCPU_IF_XBAR_SERR_INTR_STS 0x4CC14A0280 281#define mmCPU_IF_XBAR_SERR_INTR_CLR 0x4CC14A4282 283#define mmCPU_IF_XBAR_SERR_INTR_MASK 0x4CC14A8284 285#define mmCPU_IF_XBAR_DERR_INTR_STS 0x4CC14B0286 287#define mmCPU_IF_XBAR_DERR_INTR_CLR 0x4CC14B4288 289#define mmCPU_IF_XBAR_DERR_INTR_MASK 0x4CC14B8290 291#define mmCPU_IF_TPC_SEI_INTR_STS 0x4CC14C0292 293#define mmCPU_IF_TPC_SEI_INTR_CLR 0x4CC14C4294 295#define mmCPU_IF_TPC_SEI_INTR_MASK 0x4CC14C8296 297#define mmCPU_IF_MME_SEI_INTR_STS_0 0x4CC14D0298 299#define mmCPU_IF_MME_SEI_INTR_STS_1 0x4CC14D4300 301#define mmCPU_IF_MME_SEI_INTR_STS_2 0x4CC14D8302 303#define mmCPU_IF_MME_SEI_INTR_STS_3 0x4CC14DC304 305#define mmCPU_IF_MME_SEI_INTR_CLR_0 0x4CC14E0306 307#define mmCPU_IF_MME_SEI_INTR_CLR_1 0x4CC14E4308 309#define mmCPU_IF_MME_SEI_INTR_CLR_2 0x4CC14E8310 311#define mmCPU_IF_MME_SEI_INTR_CLR_3 0x4CC14EC312 313#define mmCPU_IF_MME_SEI_INTR_MASK_0 0x4CC14F0314 315#define mmCPU_IF_MME_SEI_INTR_MASK_1 0x4CC14F4316 317#define mmCPU_IF_MME_SEI_INTR_MASK_2 0x4CC14F8318 319#define mmCPU_IF_MME_SEI_INTR_MASK_3 0x4CC14FC320 321#define mmCPU_IF_PLL_LSB_SEI_INTR_STS 0x4CC1500322 323#define mmCPU_IF_PLL_LSB_SEI_INTR_CLR 0x4CC1504324 325#define mmCPU_IF_PLL_LSB_SEI_INTR_MASK 0x4CC1508326 327#define mmCPU_IF_PLL_MSB_SEI_INTR_STS 0x4CC1510328 329#define mmCPU_IF_PLL_MSB_SEI_INTR_CLR 0x4CC1514330 331#define mmCPU_IF_PLL_MSB_SEI_INTR_MASK 0x4CC1518332 333#define mmCPU_IF_HMMU_SEI_INTR_STS 0x4CC1520334 335#define mmCPU_IF_HMMU_SEI_INTR_CLR 0x4CC1524336 337#define mmCPU_IF_HMMU_SEI_INTR_MASK 0x4CC1528338 339#define mmCPU_IF_HDMA_SEI_INTR_STS 0x4CC1530340 341#define mmCPU_IF_HDMA_SEI_INTR_CLR 0x4CC1534342 343#define mmCPU_IF_HDMA_SEI_INTR_MASK 0x4CC1538344 345#define mmCPU_IF_PDMA_SEI_INTR_STS 0x4CC1540346 347#define mmCPU_IF_PDMA_SEI_INTR_CLR 0x4CC1544348 349#define mmCPU_IF_PDMA_SEI_INTR_MASK 0x4CC1548350 351#define mmCPU_IF_HBM_SEI_INTR_STS 0x4CC1550352 353#define mmCPU_IF_HBM_SEI_INTR_CLR 0x4CC1554354 355#define mmCPU_IF_HBM_SEI_INTR_MASK 0x4CC1558356 357#define mmCPU_IF_DEC_SEI_INTR_STS 0x4CC1560358 359#define mmCPU_IF_DEC_SEI_INTR_CLR 0x4CC1564360 361#define mmCPU_IF_DEC_SEI_INTR_MASK 0x4CC1568362 363#define mmCPU_IF_HIF_SEI_INTR_STS 0x4CC1570364 365#define mmCPU_IF_HIF_SEI_INTR_CLR 0x4CC1574366 367#define mmCPU_IF_HIF_SEI_INTR_MASK 0x4CC1578368 369#define mmCPU_IF_SYNC_MNGR_SEI_INTR_STS 0x4CC1580370 371#define mmCPU_IF_SYNC_MNGR_SEI_INTR_CLR 0x4CC1584372 373#define mmCPU_IF_SYNC_MNGR_SEI_INTR_MASK 0x4CC1588374 375#define mmCPU_IF_NIC_SEI_INTR_STS 0x4CC1590376 377#define mmCPU_IF_NIC_SEI_INTR_CLR 0x4CC1594378 379#define mmCPU_IF_NIC_SEI_INTR_MASK 0x4CC1598380 381#define mmCPU_IF_PCIE_SPI_INTR_STS 0x4CC1600382 383#define mmCPU_IF_PCIE_SPI_INTR_CLR 0x4CC1604384 385#define mmCPU_IF_PCIE_SPI_INTR_MASK 0x4CC1608386 387#define mmCPU_IF_MME_SPI_INTR_STS_0 0x4CC1610388 389#define mmCPU_IF_MME_SPI_INTR_STS_1 0x4CC1614390 391#define mmCPU_IF_MME_SPI_INTR_STS_2 0x4CC1618392 393#define mmCPU_IF_MME_SPI_INTR_STS_3 0x4CC161C394 395#define mmCPU_IF_MME_SPI_INTR_CLR_0 0x4CC1620396 397#define mmCPU_IF_MME_SPI_INTR_CLR_1 0x4CC1624398 399#define mmCPU_IF_MME_SPI_INTR_CLR_2 0x4CC1628400 401#define mmCPU_IF_MME_SPI_INTR_CLR_3 0x4CC162C402 403#define mmCPU_IF_MME_SPI_INTR_MASK_0 0x4CC1630404 405#define mmCPU_IF_MME_SPI_INTR_MASK_1 0x4CC1634406 407#define mmCPU_IF_MME_SPI_INTR_MASK_2 0x4CC1638408 409#define mmCPU_IF_MME_SPI_INTR_MASK_3 0x4CC163C410 411#define mmCPU_IF_HMMU_SPI_INTR_STS_0 0x4CC1640412 413#define mmCPU_IF_HMMU_SPI_INTR_STS_1 0x4CC1644414 415#define mmCPU_IF_HMMU_SPI_INTR_STS_2 0x4CC1648416 417#define mmCPU_IF_HMMU_SPI_INTR_STS_3 0x4CC164C418 419#define mmCPU_IF_HMMU_SPI_INTR_STS_4 0x4CC1650420 421#define mmCPU_IF_HMMU_SPI_INTR_STS_5 0x4CC1654422 423#define mmCPU_IF_HMMU_SPI_INTR_STS_6 0x4CC1658424 425#define mmCPU_IF_HMMU_SPI_INTR_STS_7 0x4CC165C426 427#define mmCPU_IF_HMMU_SPI_INTR_STS_8 0x4CC1660428 429#define mmCPU_IF_HMMU_SPI_INTR_STS_9 0x4CC1664430 431#define mmCPU_IF_HMMU_SPI_INTR_STS_10 0x4CC1668432 433#define mmCPU_IF_HMMU_SPI_INTR_STS_11 0x4CC166C434 435#define mmCPU_IF_HMMU_SPI_INTR_STS_12 0x4CC1670436 437#define mmCPU_IF_HMMU_SPI_INTR_STS_13 0x4CC1674438 439#define mmCPU_IF_HMMU_SPI_INTR_STS_14 0x4CC1678440 441#define mmCPU_IF_HMMU_SPI_INTR_STS_15 0x4CC167C442 443#define mmCPU_IF_HMMU_SPI_INTR_CLR_0 0x4CC1680444 445#define mmCPU_IF_HMMU_SPI_INTR_CLR_1 0x4CC1684446 447#define mmCPU_IF_HMMU_SPI_INTR_CLR_2 0x4CC1688448 449#define mmCPU_IF_HMMU_SPI_INTR_CLR_3 0x4CC168C450 451#define mmCPU_IF_HMMU_SPI_INTR_CLR_4 0x4CC1690452 453#define mmCPU_IF_HMMU_SPI_INTR_CLR_5 0x4CC1694454 455#define mmCPU_IF_HMMU_SPI_INTR_CLR_6 0x4CC1698456 457#define mmCPU_IF_HMMU_SPI_INTR_CLR_7 0x4CC169C458 459#define mmCPU_IF_HMMU_SPI_INTR_CLR_8 0x4CC16A0460 461#define mmCPU_IF_HMMU_SPI_INTR_CLR_9 0x4CC16A4462 463#define mmCPU_IF_HMMU_SPI_INTR_CLR_10 0x4CC16A8464 465#define mmCPU_IF_HMMU_SPI_INTR_CLR_11 0x4CC16AC466 467#define mmCPU_IF_HMMU_SPI_INTR_CLR_12 0x4CC16B0468 469#define mmCPU_IF_HMMU_SPI_INTR_CLR_13 0x4CC16B4470 471#define mmCPU_IF_HMMU_SPI_INTR_CLR_14 0x4CC16B8472 473#define mmCPU_IF_HMMU_SPI_INTR_CLR_15 0x4CC16BC474 475#define mmCPU_IF_HMMU_SPI_INTR_MASK_0 0x4CC16C0476 477#define mmCPU_IF_HMMU_SPI_INTR_MASK_1 0x4CC16C4478 479#define mmCPU_IF_HMMU_SPI_INTR_MASK_2 0x4CC16C8480 481#define mmCPU_IF_HMMU_SPI_INTR_MASK_3 0x4CC16CC482 483#define mmCPU_IF_HMMU_SPI_INTR_MASK_4 0x4CC16D0484 485#define mmCPU_IF_HMMU_SPI_INTR_MASK_5 0x4CC16D4486 487#define mmCPU_IF_HMMU_SPI_INTR_MASK_6 0x4CC16D8488 489#define mmCPU_IF_HMMU_SPI_INTR_MASK_7 0x4CC16DC490 491#define mmCPU_IF_HMMU_SPI_INTR_MASK_8 0x4CC16E0492 493#define mmCPU_IF_HMMU_SPI_INTR_MASK_9 0x4CC16E4494 495#define mmCPU_IF_HMMU_SPI_INTR_MASK_10 0x4CC16E8496 497#define mmCPU_IF_HMMU_SPI_INTR_MASK_11 0x4CC16EC498 499#define mmCPU_IF_HMMU_SPI_INTR_MASK_12 0x4CC16F0500 501#define mmCPU_IF_HMMU_SPI_INTR_MASK_13 0x4CC16F4502 503#define mmCPU_IF_HMMU_SPI_INTR_MASK_14 0x4CC16F8504 505#define mmCPU_IF_HMMU_SPI_INTR_MASK_15 0x4CC16FC506 507#define mmCPU_IF_DEC_SPI_INTR_STS_0 0x4CC1700508 509#define mmCPU_IF_DEC_SPI_INTR_STS_1 0x4CC1704510 511#define mmCPU_IF_DEC_SPI_INTR_STS_2 0x4CC1708512 513#define mmCPU_IF_DEC_SPI_INTR_STS_3 0x4CC170C514 515#define mmCPU_IF_DEC_SPI_INTR_STS_4 0x4CC1710516 517#define mmCPU_IF_DEC_SPI_INTR_STS_5 0x4CC1714518 519#define mmCPU_IF_DEC_SPI_INTR_STS_6 0x4CC1718520 521#define mmCPU_IF_DEC_SPI_INTR_STS_7 0x4CC171C522 523#define mmCPU_IF_DEC_SPI_INTR_STS_8 0x4CC1720524 525#define mmCPU_IF_DEC_SPI_INTR_STS_9 0x4CC1724526 527#define mmCPU_IF_DEC_SPI_INTR_CLR_0 0x4CC1730528 529#define mmCPU_IF_DEC_SPI_INTR_CLR_1 0x4CC1734530 531#define mmCPU_IF_DEC_SPI_INTR_CLR_2 0x4CC1738532 533#define mmCPU_IF_DEC_SPI_INTR_CLR_3 0x4CC173C534 535#define mmCPU_IF_DEC_SPI_INTR_CLR_4 0x4CC1740536 537#define mmCPU_IF_DEC_SPI_INTR_CLR_5 0x4CC1744538 539#define mmCPU_IF_DEC_SPI_INTR_CLR_6 0x4CC1748540 541#define mmCPU_IF_DEC_SPI_INTR_CLR_7 0x4CC174C542 543#define mmCPU_IF_DEC_SPI_INTR_CLR_8 0x4CC1750544 545#define mmCPU_IF_DEC_SPI_INTR_CLR_9 0x4CC1754546 547#define mmCPU_IF_DEC_SPI_INTR_MASK_0 0x4CC1760548 549#define mmCPU_IF_DEC_SPI_INTR_MASK_1 0x4CC1764550 551#define mmCPU_IF_DEC_SPI_INTR_MASK_2 0x4CC1768552 553#define mmCPU_IF_DEC_SPI_INTR_MASK_3 0x4CC176C554 555#define mmCPU_IF_DEC_SPI_INTR_MASK_4 0x4CC1770556 557#define mmCPU_IF_DEC_SPI_INTR_MASK_5 0x4CC1774558 559#define mmCPU_IF_DEC_SPI_INTR_MASK_6 0x4CC1778560 561#define mmCPU_IF_DEC_SPI_INTR_MASK_7 0x4CC177C562 563#define mmCPU_IF_DEC_SPI_INTR_MASK_8 0x4CC1780564 565#define mmCPU_IF_DEC_SPI_INTR_MASK_9 0x4CC1784566 567#define mmCPU_IF_HIF_SPI_INTR_STS 0x4CC17A0568 569#define mmCPU_IF_HIF_SPI_INTR_CLR 0x4CC17A4570 571#define mmCPU_IF_HIF_SPI_INTR_MASK 0x4CC17A8572 573#define mmCPU_IF_NIC_SPI_INTR_STS_0 0x4CC17B0574 575#define mmCPU_IF_NIC_SPI_INTR_STS_1 0x4CC17B4576 577#define mmCPU_IF_NIC_SPI_INTR_STS_2 0x4CC17B8578 579#define mmCPU_IF_NIC_SPI_INTR_STS_3 0x4CC17BC580 581#define mmCPU_IF_NIC_SPI_INTR_STS_4 0x4CC17C0582 583#define mmCPU_IF_NIC_SPI_INTR_STS_5 0x4CC17C4584 585#define mmCPU_IF_NIC_SPI_INTR_STS_6 0x4CC17C8586 587#define mmCPU_IF_NIC_SPI_INTR_STS_7 0x4CC17CC588 589#define mmCPU_IF_NIC_SPI_INTR_STS_8 0x4CC17D0590 591#define mmCPU_IF_NIC_SPI_INTR_STS_9 0x4CC17D4592 593#define mmCPU_IF_NIC_SPI_INTR_STS_10 0x4CC17D8594 595#define mmCPU_IF_NIC_SPI_INTR_STS_11 0x4CC17DC596 597#define mmCPU_IF_NIC_SPI_INTR_CLR_0 0x4CC17E0598 599#define mmCPU_IF_NIC_SPI_INTR_CLR_1 0x4CC17E4600 601#define mmCPU_IF_NIC_SPI_INTR_CLR_2 0x4CC17E8602 603#define mmCPU_IF_NIC_SPI_INTR_CLR_3 0x4CC17EC604 605#define mmCPU_IF_NIC_SPI_INTR_CLR_4 0x4CC17F0606 607#define mmCPU_IF_NIC_SPI_INTR_CLR_5 0x4CC17F4608 609#define mmCPU_IF_NIC_SPI_INTR_CLR_6 0x4CC17F8610 611#define mmCPU_IF_NIC_SPI_INTR_CLR_7 0x4CC17FC612 613#define mmCPU_IF_NIC_SPI_INTR_CLR_8 0x4CC1800614 615#define mmCPU_IF_NIC_SPI_INTR_CLR_9 0x4CC1804616 617#define mmCPU_IF_NIC_SPI_INTR_CLR_10 0x4CC1808618 619#define mmCPU_IF_NIC_SPI_INTR_CLR_11 0x4CC180C620 621#define mmCPU_IF_NIC_SPI_INTR_MASK_0 0x4CC1810622 623#define mmCPU_IF_NIC_SPI_INTR_MASK_1 0x4CC1814624 625#define mmCPU_IF_NIC_SPI_INTR_MASK_2 0x4CC1818626 627#define mmCPU_IF_NIC_SPI_INTR_MASK_3 0x4CC181C628 629#define mmCPU_IF_NIC_SPI_INTR_MASK_4 0x4CC1820630 631#define mmCPU_IF_NIC_SPI_INTR_MASK_5 0x4CC1824632 633#define mmCPU_IF_NIC_SPI_INTR_MASK_6 0x4CC1828634 635#define mmCPU_IF_NIC_SPI_INTR_MASK_7 0x4CC182C636 637#define mmCPU_IF_NIC_SPI_INTR_MASK_8 0x4CC1830638 639#define mmCPU_IF_NIC_SPI_INTR_MASK_9 0x4CC1834640 641#define mmCPU_IF_NIC_SPI_INTR_MASK_10 0x4CC1838642 643#define mmCPU_IF_NIC_SPI_INTR_MASK_11 0x4CC183C644 645#define mmCPU_IF_DEC_ECO_INTR_STS 0x4CC1840646 647#define mmCPU_IF_DEC_ECO_INTR_CLR 0x4CC1844648 649#define mmCPU_IF_DEC_ECO_INTR_MASK 0x4CC1848650 651#define mmCPU_IF_HIF_ECO_INTR_STS 0x4CC1850652 653#define mmCPU_IF_HIF_ECO_INTR_CLR 0x4CC1854654 655#define mmCPU_IF_HIF_ECO_INTR_MASK 0x4CC1858656 657#define mmCPU_IF_HMMU_ECO_INTR_STS 0x4CC1860658 659#define mmCPU_IF_HMMU_ECO_INTR_CLR 0x4CC1864660 661#define mmCPU_IF_HMMU_ECO_INTR_MASK 0x4CC1868662 663#define mmCPU_IF_NIC_ECO_INTR_STS 0x4CC1870664 665#define mmCPU_IF_NIC_ECO_INTR_CLR 0x4CC1874666 667#define mmCPU_IF_NIC_ECO_INTR_MASK 0x4CC1878668 669#define mmCPU_IF_MSI_X_INTR_STS_0 0x4CC1900670 671#define mmCPU_IF_MSI_X_INTR_STS_1 0x4CC1904672 673#define mmCPU_IF_MSI_X_INTR_STS_2 0x4CC1908674 675#define mmCPU_IF_MSI_X_INTR_STS_3 0x4CC190C676 677#define mmCPU_IF_MSI_X_INTR_STS_4 0x4CC1910678 679#define mmCPU_IF_MSI_X_INTR_STS_5 0x4CC1914680 681#define mmCPU_IF_MSI_X_INTR_STS_6 0x4CC1918682 683#define mmCPU_IF_MSI_X_INTR_STS_7 0x4CC191C684 685#define mmCPU_IF_MSI_X_INTR_STS_8 0x4CC1920686 687#define mmCPU_IF_MSI_X_INTR_STS_9 0x4CC1924688 689#define mmCPU_IF_MSI_X_INTR_STS_10 0x4CC1928690 691#define mmCPU_IF_MSI_X_INTR_STS_11 0x4CC192C692 693#define mmCPU_IF_MSI_X_INTR_STS_12 0x4CC1930694 695#define mmCPU_IF_MSI_X_INTR_STS_13 0x4CC1934696 697#define mmCPU_IF_MSI_X_INTR_STS_14 0x4CC1938698 699#define mmCPU_IF_MSI_X_INTR_STS_15 0x4CC193C700 701#define mmCPU_IF_MSI_X_INTR_CLR_0 0x4CC1940702 703#define mmCPU_IF_MSI_X_INTR_CLR_1 0x4CC1944704 705#define mmCPU_IF_MSI_X_INTR_CLR_2 0x4CC1948706 707#define mmCPU_IF_MSI_X_INTR_CLR_3 0x4CC194C708 709#define mmCPU_IF_MSI_X_INTR_CLR_4 0x4CC1950710 711#define mmCPU_IF_MSI_X_INTR_CLR_5 0x4CC1954712 713#define mmCPU_IF_MSI_X_INTR_CLR_6 0x4CC1958714 715#define mmCPU_IF_MSI_X_INTR_CLR_7 0x4CC195C716 717#define mmCPU_IF_MSI_X_INTR_CLR_8 0x4CC1960718 719#define mmCPU_IF_MSI_X_INTR_CLR_9 0x4CC1964720 721#define mmCPU_IF_MSI_X_INTR_CLR_10 0x4CC1968722 723#define mmCPU_IF_MSI_X_INTR_CLR_11 0x4CC196C724 725#define mmCPU_IF_MSI_X_INTR_CLR_12 0x4CC1970726 727#define mmCPU_IF_MSI_X_INTR_CLR_13 0x4CC1974728 729#define mmCPU_IF_MSI_X_INTR_CLR_14 0x4CC1978730 731#define mmCPU_IF_MSI_X_INTR_CLR_15 0x4CC197C732 733#define mmCPU_IF_MSI_X_INTR_MASK_0 0x4CC1980734 735#define mmCPU_IF_MSI_X_INTR_MASK_1 0x4CC1984736 737#define mmCPU_IF_MSI_X_INTR_MASK_2 0x4CC1988738 739#define mmCPU_IF_MSI_X_INTR_MASK_3 0x4CC198C740 741#define mmCPU_IF_MSI_X_INTR_MASK_4 0x4CC1990742 743#define mmCPU_IF_MSI_X_INTR_MASK_5 0x4CC1994744 745#define mmCPU_IF_MSI_X_INTR_MASK_6 0x4CC1998746 747#define mmCPU_IF_MSI_X_INTR_MASK_7 0x4CC199C748 749#define mmCPU_IF_MSI_X_INTR_MASK_8 0x4CC19A0750 751#define mmCPU_IF_MSI_X_INTR_MASK_9 0x4CC19A4752 753#define mmCPU_IF_MSI_X_INTR_MASK_10 0x4CC19A8754 755#define mmCPU_IF_MSI_X_INTR_MASK_11 0x4CC19AC756 757#define mmCPU_IF_MSI_X_INTR_MASK_12 0x4CC19B0758 759#define mmCPU_IF_MSI_X_INTR_MASK_13 0x4CC19B4760 761#define mmCPU_IF_MSI_X_INTR_MASK_14 0x4CC19B8762 763#define mmCPU_IF_MSI_X_INTR_MASK_15 0x4CC19BC764 765#define mmCPU_IF_MSI_X_BUSY_INTR_STS 0x4CC19C0766 767#define mmCPU_IF_MSI_X_BUSY_INTR_CLR 0x4CC19C4768 769#define mmCPU_IF_MSI_X_BUSY_INTR_MASK 0x4CC19C8770 771#define mmCPU_IF_MSI_X_GEN_ADDR 0x4CC19D0772 773#define mmCPU_IF_MSI_X_GEN_DATA 0x4CC19D4774 775#define mmCPU_IF_MSI_X_GEN_AWPROT 0x4CC19D8776 777#endif /* ASIC_REG_CPU_IF_REGS_H_ */778