1058 lines · c
1/* SPDX-License-Identifier: GPL-2.02 *3 * Copyright 2016-2020 HabanaLabs, Ltd.4 * All Rights Reserved.5 *6 */7 8/************************************9 ** This is an auto-generated file **10 ** DO NOT EDIT BELOW **11 ************************************/12 13#ifndef ASIC_REG_NIC0_QM0_REGS_H_14#define ASIC_REG_NIC0_QM0_REGS_H_15 16/*17 *****************************************18 * NIC0_QM019 * (Prototype: QMAN)20 *****************************************21 */22 23#define mmNIC0_QM0_GLBL_CFG0 0x541A00024 25#define mmNIC0_QM0_GLBL_CFG1 0x541A00426 27#define mmNIC0_QM0_GLBL_CFG2 0x541A00828 29#define mmNIC0_QM0_GLBL_ERR_CFG 0x541A00C30 31#define mmNIC0_QM0_GLBL_ERR_CFG1 0x541A01032 33#define mmNIC0_QM0_GLBL_ERR_ARC_HALT_EN 0x541A01434 35#define mmNIC0_QM0_GLBL_AXCACHE 0x541A01836 37#define mmNIC0_QM0_GLBL_STS0 0x541A01C38 39#define mmNIC0_QM0_GLBL_STS1 0x541A02040 41#define mmNIC0_QM0_GLBL_ERR_STS_0 0x541A02442 43#define mmNIC0_QM0_GLBL_ERR_STS_1 0x541A02844 45#define mmNIC0_QM0_GLBL_ERR_STS_2 0x541A02C46 47#define mmNIC0_QM0_GLBL_ERR_STS_3 0x541A03048 49#define mmNIC0_QM0_GLBL_ERR_STS_4 0x541A03450 51#define mmNIC0_QM0_GLBL_ERR_MSG_EN_0 0x541A03852 53#define mmNIC0_QM0_GLBL_ERR_MSG_EN_1 0x541A03C54 55#define mmNIC0_QM0_GLBL_ERR_MSG_EN_2 0x541A04056 57#define mmNIC0_QM0_GLBL_ERR_MSG_EN_3 0x541A04458 59#define mmNIC0_QM0_GLBL_ERR_MSG_EN_4 0x541A04860 61#define mmNIC0_QM0_GLBL_PROT 0x541A04C62 63#define mmNIC0_QM0_PQ_BASE_LO_0 0x541A05064 65#define mmNIC0_QM0_PQ_BASE_LO_1 0x541A05466 67#define mmNIC0_QM0_PQ_BASE_LO_2 0x541A05868 69#define mmNIC0_QM0_PQ_BASE_LO_3 0x541A05C70 71#define mmNIC0_QM0_PQ_BASE_HI_0 0x541A06072 73#define mmNIC0_QM0_PQ_BASE_HI_1 0x541A06474 75#define mmNIC0_QM0_PQ_BASE_HI_2 0x541A06876 77#define mmNIC0_QM0_PQ_BASE_HI_3 0x541A06C78 79#define mmNIC0_QM0_PQ_SIZE_0 0x541A07080 81#define mmNIC0_QM0_PQ_SIZE_1 0x541A07482 83#define mmNIC0_QM0_PQ_SIZE_2 0x541A07884 85#define mmNIC0_QM0_PQ_SIZE_3 0x541A07C86 87#define mmNIC0_QM0_PQ_PI_0 0x541A08088 89#define mmNIC0_QM0_PQ_PI_1 0x541A08490 91#define mmNIC0_QM0_PQ_PI_2 0x541A08892 93#define mmNIC0_QM0_PQ_PI_3 0x541A08C94 95#define mmNIC0_QM0_PQ_CI_0 0x541A09096 97#define mmNIC0_QM0_PQ_CI_1 0x541A09498 99#define mmNIC0_QM0_PQ_CI_2 0x541A098100 101#define mmNIC0_QM0_PQ_CI_3 0x541A09C102 103#define mmNIC0_QM0_PQ_CFG0_0 0x541A0A0104 105#define mmNIC0_QM0_PQ_CFG0_1 0x541A0A4106 107#define mmNIC0_QM0_PQ_CFG0_2 0x541A0A8108 109#define mmNIC0_QM0_PQ_CFG0_3 0x541A0AC110 111#define mmNIC0_QM0_PQ_CFG1_0 0x541A0B0112 113#define mmNIC0_QM0_PQ_CFG1_1 0x541A0B4114 115#define mmNIC0_QM0_PQ_CFG1_2 0x541A0B8116 117#define mmNIC0_QM0_PQ_CFG1_3 0x541A0BC118 119#define mmNIC0_QM0_PQ_STS0_0 0x541A0C0120 121#define mmNIC0_QM0_PQ_STS0_1 0x541A0C4122 123#define mmNIC0_QM0_PQ_STS0_2 0x541A0C8124 125#define mmNIC0_QM0_PQ_STS0_3 0x541A0CC126 127#define mmNIC0_QM0_PQ_STS1_0 0x541A0D0128 129#define mmNIC0_QM0_PQ_STS1_1 0x541A0D4130 131#define mmNIC0_QM0_PQ_STS1_2 0x541A0D8132 133#define mmNIC0_QM0_PQ_STS1_3 0x541A0DC134 135#define mmNIC0_QM0_CQ_CFG0_0 0x541A0E0136 137#define mmNIC0_QM0_CQ_CFG0_1 0x541A0E4138 139#define mmNIC0_QM0_CQ_CFG0_2 0x541A0E8140 141#define mmNIC0_QM0_CQ_CFG0_3 0x541A0EC142 143#define mmNIC0_QM0_CQ_CFG0_4 0x541A0F0144 145#define mmNIC0_QM0_CQ_STS0_0 0x541A0F4146 147#define mmNIC0_QM0_CQ_STS0_1 0x541A0F8148 149#define mmNIC0_QM0_CQ_STS0_2 0x541A0FC150 151#define mmNIC0_QM0_CQ_STS0_3 0x541A100152 153#define mmNIC0_QM0_CQ_STS0_4 0x541A104154 155#define mmNIC0_QM0_CQ_CFG1_0 0x541A108156 157#define mmNIC0_QM0_CQ_CFG1_1 0x541A10C158 159#define mmNIC0_QM0_CQ_CFG1_2 0x541A110160 161#define mmNIC0_QM0_CQ_CFG1_3 0x541A114162 163#define mmNIC0_QM0_CQ_CFG1_4 0x541A118164 165#define mmNIC0_QM0_CQ_STS1_0 0x541A11C166 167#define mmNIC0_QM0_CQ_STS1_1 0x541A120168 169#define mmNIC0_QM0_CQ_STS1_2 0x541A124170 171#define mmNIC0_QM0_CQ_STS1_3 0x541A128172 173#define mmNIC0_QM0_CQ_STS1_4 0x541A12C174 175#define mmNIC0_QM0_CQ_PTR_LO_0 0x541A150176 177#define mmNIC0_QM0_CQ_PTR_HI_0 0x541A154178 179#define mmNIC0_QM0_CQ_TSIZE_0 0x541A158180 181#define mmNIC0_QM0_CQ_CTL_0 0x541A15C182 183#define mmNIC0_QM0_CQ_PTR_LO_1 0x541A160184 185#define mmNIC0_QM0_CQ_PTR_HI_1 0x541A164186 187#define mmNIC0_QM0_CQ_TSIZE_1 0x541A168188 189#define mmNIC0_QM0_CQ_CTL_1 0x541A16C190 191#define mmNIC0_QM0_CQ_PTR_LO_2 0x541A170192 193#define mmNIC0_QM0_CQ_PTR_HI_2 0x541A174194 195#define mmNIC0_QM0_CQ_TSIZE_2 0x541A178196 197#define mmNIC0_QM0_CQ_CTL_2 0x541A17C198 199#define mmNIC0_QM0_CQ_PTR_LO_3 0x541A180200 201#define mmNIC0_QM0_CQ_PTR_HI_3 0x541A184202 203#define mmNIC0_QM0_CQ_TSIZE_3 0x541A188204 205#define mmNIC0_QM0_CQ_CTL_3 0x541A18C206 207#define mmNIC0_QM0_CQ_PTR_LO_4 0x541A190208 209#define mmNIC0_QM0_CQ_PTR_HI_4 0x541A194210 211#define mmNIC0_QM0_CQ_TSIZE_4 0x541A198212 213#define mmNIC0_QM0_CQ_CTL_4 0x541A19C214 215#define mmNIC0_QM0_CQ_TSIZE_STS_0 0x541A1A0216 217#define mmNIC0_QM0_CQ_TSIZE_STS_1 0x541A1A4218 219#define mmNIC0_QM0_CQ_TSIZE_STS_2 0x541A1A8220 221#define mmNIC0_QM0_CQ_TSIZE_STS_3 0x541A1AC222 223#define mmNIC0_QM0_CQ_TSIZE_STS_4 0x541A1B0224 225#define mmNIC0_QM0_CQ_PTR_LO_STS_0 0x541A1B4226 227#define mmNIC0_QM0_CQ_PTR_LO_STS_1 0x541A1B8228 229#define mmNIC0_QM0_CQ_PTR_LO_STS_2 0x541A1BC230 231#define mmNIC0_QM0_CQ_PTR_LO_STS_3 0x541A1C0232 233#define mmNIC0_QM0_CQ_PTR_LO_STS_4 0x541A1C4234 235#define mmNIC0_QM0_CQ_PTR_HI_STS_0 0x541A1C8236 237#define mmNIC0_QM0_CQ_PTR_HI_STS_1 0x541A1CC238 239#define mmNIC0_QM0_CQ_PTR_HI_STS_2 0x541A1D0240 241#define mmNIC0_QM0_CQ_PTR_HI_STS_3 0x541A1D4242 243#define mmNIC0_QM0_CQ_PTR_HI_STS_4 0x541A1D8244 245#define mmNIC0_QM0_CQ_IFIFO_STS_0 0x541A1DC246 247#define mmNIC0_QM0_CQ_IFIFO_STS_1 0x541A1E0248 249#define mmNIC0_QM0_CQ_IFIFO_STS_2 0x541A1E4250 251#define mmNIC0_QM0_CQ_IFIFO_STS_3 0x541A1E8252 253#define mmNIC0_QM0_CQ_IFIFO_STS_4 0x541A1EC254 255#define mmNIC0_QM0_CP_MSG_BASE0_ADDR_LO_0 0x541A1F0256 257#define mmNIC0_QM0_CP_MSG_BASE0_ADDR_LO_1 0x541A1F4258 259#define mmNIC0_QM0_CP_MSG_BASE0_ADDR_LO_2 0x541A1F8260 261#define mmNIC0_QM0_CP_MSG_BASE0_ADDR_LO_3 0x541A1FC262 263#define mmNIC0_QM0_CP_MSG_BASE0_ADDR_LO_4 0x541A200264 265#define mmNIC0_QM0_CP_MSG_BASE0_ADDR_HI_0 0x541A204266 267#define mmNIC0_QM0_CP_MSG_BASE0_ADDR_HI_1 0x541A208268 269#define mmNIC0_QM0_CP_MSG_BASE0_ADDR_HI_2 0x541A20C270 271#define mmNIC0_QM0_CP_MSG_BASE0_ADDR_HI_3 0x541A210272 273#define mmNIC0_QM0_CP_MSG_BASE0_ADDR_HI_4 0x541A214274 275#define mmNIC0_QM0_CP_MSG_BASE1_ADDR_LO_0 0x541A218276 277#define mmNIC0_QM0_CP_MSG_BASE1_ADDR_LO_1 0x541A21C278 279#define mmNIC0_QM0_CP_MSG_BASE1_ADDR_LO_2 0x541A220280 281#define mmNIC0_QM0_CP_MSG_BASE1_ADDR_LO_3 0x541A224282 283#define mmNIC0_QM0_CP_MSG_BASE1_ADDR_LO_4 0x541A228284 285#define mmNIC0_QM0_CP_MSG_BASE1_ADDR_HI_0 0x541A22C286 287#define mmNIC0_QM0_CP_MSG_BASE1_ADDR_HI_1 0x541A230288 289#define mmNIC0_QM0_CP_MSG_BASE1_ADDR_HI_2 0x541A234290 291#define mmNIC0_QM0_CP_MSG_BASE1_ADDR_HI_3 0x541A238292 293#define mmNIC0_QM0_CP_MSG_BASE1_ADDR_HI_4 0x541A23C294 295#define mmNIC0_QM0_CP_MSG_BASE2_ADDR_LO_0 0x541A240296 297#define mmNIC0_QM0_CP_MSG_BASE2_ADDR_LO_1 0x541A244298 299#define mmNIC0_QM0_CP_MSG_BASE2_ADDR_LO_2 0x541A248300 301#define mmNIC0_QM0_CP_MSG_BASE2_ADDR_LO_3 0x541A24C302 303#define mmNIC0_QM0_CP_MSG_BASE2_ADDR_LO_4 0x541A250304 305#define mmNIC0_QM0_CP_MSG_BASE2_ADDR_HI_0 0x541A254306 307#define mmNIC0_QM0_CP_MSG_BASE2_ADDR_HI_1 0x541A258308 309#define mmNIC0_QM0_CP_MSG_BASE2_ADDR_HI_2 0x541A25C310 311#define mmNIC0_QM0_CP_MSG_BASE2_ADDR_HI_3 0x541A260312 313#define mmNIC0_QM0_CP_MSG_BASE2_ADDR_HI_4 0x541A264314 315#define mmNIC0_QM0_CP_MSG_BASE3_ADDR_LO_0 0x541A268316 317#define mmNIC0_QM0_CP_MSG_BASE3_ADDR_LO_1 0x541A26C318 319#define mmNIC0_QM0_CP_MSG_BASE3_ADDR_LO_2 0x541A270320 321#define mmNIC0_QM0_CP_MSG_BASE3_ADDR_LO_3 0x541A274322 323#define mmNIC0_QM0_CP_MSG_BASE3_ADDR_LO_4 0x541A278324 325#define mmNIC0_QM0_CP_MSG_BASE3_ADDR_HI_0 0x541A27C326 327#define mmNIC0_QM0_CP_MSG_BASE3_ADDR_HI_1 0x541A280328 329#define mmNIC0_QM0_CP_MSG_BASE3_ADDR_HI_2 0x541A284330 331#define mmNIC0_QM0_CP_MSG_BASE3_ADDR_HI_3 0x541A288332 333#define mmNIC0_QM0_CP_MSG_BASE3_ADDR_HI_4 0x541A28C334 335#define mmNIC0_QM0_CP_FENCE0_RDATA_0 0x541A290336 337#define mmNIC0_QM0_CP_FENCE0_RDATA_1 0x541A294338 339#define mmNIC0_QM0_CP_FENCE0_RDATA_2 0x541A298340 341#define mmNIC0_QM0_CP_FENCE0_RDATA_3 0x541A29C342 343#define mmNIC0_QM0_CP_FENCE0_RDATA_4 0x541A2A0344 345#define mmNIC0_QM0_CP_FENCE1_RDATA_0 0x541A2A4346 347#define mmNIC0_QM0_CP_FENCE1_RDATA_1 0x541A2A8348 349#define mmNIC0_QM0_CP_FENCE1_RDATA_2 0x541A2AC350 351#define mmNIC0_QM0_CP_FENCE1_RDATA_3 0x541A2B0352 353#define mmNIC0_QM0_CP_FENCE1_RDATA_4 0x541A2B4354 355#define mmNIC0_QM0_CP_FENCE2_RDATA_0 0x541A2B8356 357#define mmNIC0_QM0_CP_FENCE2_RDATA_1 0x541A2BC358 359#define mmNIC0_QM0_CP_FENCE2_RDATA_2 0x541A2C0360 361#define mmNIC0_QM0_CP_FENCE2_RDATA_3 0x541A2C4362 363#define mmNIC0_QM0_CP_FENCE2_RDATA_4 0x541A2C8364 365#define mmNIC0_QM0_CP_FENCE3_RDATA_0 0x541A2CC366 367#define mmNIC0_QM0_CP_FENCE3_RDATA_1 0x541A2D0368 369#define mmNIC0_QM0_CP_FENCE3_RDATA_2 0x541A2D4370 371#define mmNIC0_QM0_CP_FENCE3_RDATA_3 0x541A2D8372 373#define mmNIC0_QM0_CP_FENCE3_RDATA_4 0x541A2DC374 375#define mmNIC0_QM0_CP_FENCE0_CNT_0 0x541A2E0376 377#define mmNIC0_QM0_CP_FENCE0_CNT_1 0x541A2E4378 379#define mmNIC0_QM0_CP_FENCE0_CNT_2 0x541A2E8380 381#define mmNIC0_QM0_CP_FENCE0_CNT_3 0x541A2EC382 383#define mmNIC0_QM0_CP_FENCE0_CNT_4 0x541A2F0384 385#define mmNIC0_QM0_CP_FENCE1_CNT_0 0x541A2F4386 387#define mmNIC0_QM0_CP_FENCE1_CNT_1 0x541A2F8388 389#define mmNIC0_QM0_CP_FENCE1_CNT_2 0x541A2FC390 391#define mmNIC0_QM0_CP_FENCE1_CNT_3 0x541A300392 393#define mmNIC0_QM0_CP_FENCE1_CNT_4 0x541A304394 395#define mmNIC0_QM0_CP_FENCE2_CNT_0 0x541A308396 397#define mmNIC0_QM0_CP_FENCE2_CNT_1 0x541A30C398 399#define mmNIC0_QM0_CP_FENCE2_CNT_2 0x541A310400 401#define mmNIC0_QM0_CP_FENCE2_CNT_3 0x541A314402 403#define mmNIC0_QM0_CP_FENCE2_CNT_4 0x541A318404 405#define mmNIC0_QM0_CP_FENCE3_CNT_0 0x541A31C406 407#define mmNIC0_QM0_CP_FENCE3_CNT_1 0x541A320408 409#define mmNIC0_QM0_CP_FENCE3_CNT_2 0x541A324410 411#define mmNIC0_QM0_CP_FENCE3_CNT_3 0x541A328412 413#define mmNIC0_QM0_CP_FENCE3_CNT_4 0x541A32C414 415#define mmNIC0_QM0_CP_BARRIER_CFG 0x541A330416 417#define mmNIC0_QM0_CP_LDMA_SRC_BASE_LO_OFFSET 0x541A334418 419#define mmNIC0_QM0_CP_LDMA_DST_BASE_LO_OFFSET 0x541A338420 421#define mmNIC0_QM0_CP_LDMA_TSIZE_OFFSET 0x541A33C422 423#define mmNIC0_QM0_CP_CQ_PTR_LO_OFFSET_0 0x541A340424 425#define mmNIC0_QM0_CP_CQ_PTR_LO_OFFSET_1 0x541A344426 427#define mmNIC0_QM0_CP_CQ_PTR_LO_OFFSET_2 0x541A348428 429#define mmNIC0_QM0_CP_CQ_PTR_LO_OFFSET_3 0x541A34C430 431#define mmNIC0_QM0_CP_CQ_PTR_LO_OFFSET_4 0x541A350432 433#define mmNIC0_QM0_CP_STS_0 0x541A368434 435#define mmNIC0_QM0_CP_STS_1 0x541A36C436 437#define mmNIC0_QM0_CP_STS_2 0x541A370438 439#define mmNIC0_QM0_CP_STS_3 0x541A374440 441#define mmNIC0_QM0_CP_STS_4 0x541A378442 443#define mmNIC0_QM0_CP_CURRENT_INST_LO_0 0x541A37C444 445#define mmNIC0_QM0_CP_CURRENT_INST_LO_1 0x541A380446 447#define mmNIC0_QM0_CP_CURRENT_INST_LO_2 0x541A384448 449#define mmNIC0_QM0_CP_CURRENT_INST_LO_3 0x541A388450 451#define mmNIC0_QM0_CP_CURRENT_INST_LO_4 0x541A38C452 453#define mmNIC0_QM0_CP_CURRENT_INST_HI_0 0x541A390454 455#define mmNIC0_QM0_CP_CURRENT_INST_HI_1 0x541A394456 457#define mmNIC0_QM0_CP_CURRENT_INST_HI_2 0x541A398458 459#define mmNIC0_QM0_CP_CURRENT_INST_HI_3 0x541A39C460 461#define mmNIC0_QM0_CP_CURRENT_INST_HI_4 0x541A3A0462 463#define mmNIC0_QM0_CP_PRED_0 0x541A3A4464 465#define mmNIC0_QM0_CP_PRED_1 0x541A3A8466 467#define mmNIC0_QM0_CP_PRED_2 0x541A3AC468 469#define mmNIC0_QM0_CP_PRED_3 0x541A3B0470 471#define mmNIC0_QM0_CP_PRED_4 0x541A3B4472 473#define mmNIC0_QM0_CP_PRED_UPEN_0 0x541A3B8474 475#define mmNIC0_QM0_CP_PRED_UPEN_1 0x541A3BC476 477#define mmNIC0_QM0_CP_PRED_UPEN_2 0x541A3C0478 479#define mmNIC0_QM0_CP_PRED_UPEN_3 0x541A3C4480 481#define mmNIC0_QM0_CP_PRED_UPEN_4 0x541A3C8482 483#define mmNIC0_QM0_CP_DBG_0_0 0x541A3CC484 485#define mmNIC0_QM0_CP_DBG_0_1 0x541A3D0486 487#define mmNIC0_QM0_CP_DBG_0_2 0x541A3D4488 489#define mmNIC0_QM0_CP_DBG_0_3 0x541A3D8490 491#define mmNIC0_QM0_CP_DBG_0_4 0x541A3DC492 493#define mmNIC0_QM0_CP_CPDMA_UP_CRED_0 0x541A3E0494 495#define mmNIC0_QM0_CP_CPDMA_UP_CRED_1 0x541A3E4496 497#define mmNIC0_QM0_CP_CPDMA_UP_CRED_2 0x541A3E8498 499#define mmNIC0_QM0_CP_CPDMA_UP_CRED_3 0x541A3EC500 501#define mmNIC0_QM0_CP_CPDMA_UP_CRED_4 0x541A3F0502 503#define mmNIC0_QM0_CP_IN_DATA_LO_0 0x541A3F4504 505#define mmNIC0_QM0_CP_IN_DATA_LO_1 0x541A3F8506 507#define mmNIC0_QM0_CP_IN_DATA_LO_2 0x541A3FC508 509#define mmNIC0_QM0_CP_IN_DATA_LO_3 0x541A400510 511#define mmNIC0_QM0_CP_IN_DATA_LO_4 0x541A404512 513#define mmNIC0_QM0_CP_IN_DATA_HI_0 0x541A408514 515#define mmNIC0_QM0_CP_IN_DATA_HI_1 0x541A40C516 517#define mmNIC0_QM0_CP_IN_DATA_HI_2 0x541A410518 519#define mmNIC0_QM0_CP_IN_DATA_HI_3 0x541A414520 521#define mmNIC0_QM0_CP_IN_DATA_HI_4 0x541A418522 523#define mmNIC0_QM0_PQC_HBW_BASE_LO_0 0x541A41C524 525#define mmNIC0_QM0_PQC_HBW_BASE_LO_1 0x541A420526 527#define mmNIC0_QM0_PQC_HBW_BASE_LO_2 0x541A424528 529#define mmNIC0_QM0_PQC_HBW_BASE_LO_3 0x541A428530 531#define mmNIC0_QM0_PQC_HBW_BASE_HI_0 0x541A42C532 533#define mmNIC0_QM0_PQC_HBW_BASE_HI_1 0x541A430534 535#define mmNIC0_QM0_PQC_HBW_BASE_HI_2 0x541A434536 537#define mmNIC0_QM0_PQC_HBW_BASE_HI_3 0x541A438538 539#define mmNIC0_QM0_PQC_SIZE_0 0x541A43C540 541#define mmNIC0_QM0_PQC_SIZE_1 0x541A440542 543#define mmNIC0_QM0_PQC_SIZE_2 0x541A444544 545#define mmNIC0_QM0_PQC_SIZE_3 0x541A448546 547#define mmNIC0_QM0_PQC_PI_0 0x541A44C548 549#define mmNIC0_QM0_PQC_PI_1 0x541A450550 551#define mmNIC0_QM0_PQC_PI_2 0x541A454552 553#define mmNIC0_QM0_PQC_PI_3 0x541A458554 555#define mmNIC0_QM0_PQC_LBW_WDATA_0 0x541A45C556 557#define mmNIC0_QM0_PQC_LBW_WDATA_1 0x541A460558 559#define mmNIC0_QM0_PQC_LBW_WDATA_2 0x541A464560 561#define mmNIC0_QM0_PQC_LBW_WDATA_3 0x541A468562 563#define mmNIC0_QM0_PQC_LBW_BASE_LO_0 0x541A46C564 565#define mmNIC0_QM0_PQC_LBW_BASE_LO_1 0x541A470566 567#define mmNIC0_QM0_PQC_LBW_BASE_LO_2 0x541A474568 569#define mmNIC0_QM0_PQC_LBW_BASE_LO_3 0x541A478570 571#define mmNIC0_QM0_PQC_LBW_BASE_HI_0 0x541A47C572 573#define mmNIC0_QM0_PQC_LBW_BASE_HI_1 0x541A480574 575#define mmNIC0_QM0_PQC_LBW_BASE_HI_2 0x541A484576 577#define mmNIC0_QM0_PQC_LBW_BASE_HI_3 0x541A488578 579#define mmNIC0_QM0_PQC_CFG 0x541A48C580 581#define mmNIC0_QM0_PQC_SECURE_PUSH_IND 0x541A490582 583#define mmNIC0_QM0_ARB_MASK 0x541A4A0584 585#define mmNIC0_QM0_ARB_CFG_0 0x541A4A4586 587#define mmNIC0_QM0_ARB_CHOICE_Q_PUSH 0x541A4A8588 589#define mmNIC0_QM0_ARB_WRR_WEIGHT_0 0x541A4AC590 591#define mmNIC0_QM0_ARB_WRR_WEIGHT_1 0x541A4B0592 593#define mmNIC0_QM0_ARB_WRR_WEIGHT_2 0x541A4B4594 595#define mmNIC0_QM0_ARB_WRR_WEIGHT_3 0x541A4B8596 597#define mmNIC0_QM0_ARB_CFG_1 0x541A4BC598 599#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_0 0x541A4C0600 601#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_1 0x541A4C4602 603#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_2 0x541A4C8604 605#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_3 0x541A4CC606 607#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_4 0x541A4D0608 609#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_5 0x541A4D4610 611#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_6 0x541A4D8612 613#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_7 0x541A4DC614 615#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_8 0x541A4E0616 617#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_9 0x541A4E4618 619#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_10 0x541A4E8620 621#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_11 0x541A4EC622 623#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_12 0x541A4F0624 625#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_13 0x541A4F4626 627#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_14 0x541A4F8628 629#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_15 0x541A4FC630 631#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_16 0x541A500632 633#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_17 0x541A504634 635#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_18 0x541A508636 637#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_19 0x541A50C638 639#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_20 0x541A510640 641#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_21 0x541A514642 643#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_22 0x541A518644 645#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_23 0x541A51C646 647#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_24 0x541A520648 649#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_25 0x541A524650 651#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_26 0x541A528652 653#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_27 0x541A52C654 655#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_28 0x541A530656 657#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_29 0x541A534658 659#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_30 0x541A538660 661#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_31 0x541A53C662 663#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_32 0x541A540664 665#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_33 0x541A544666 667#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_34 0x541A548668 669#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_35 0x541A54C670 671#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_36 0x541A550672 673#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_37 0x541A554674 675#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_38 0x541A558676 677#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_39 0x541A55C678 679#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_40 0x541A560680 681#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_41 0x541A564682 683#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_42 0x541A568684 685#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_43 0x541A56C686 687#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_44 0x541A570688 689#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_45 0x541A574690 691#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_46 0x541A578692 693#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_47 0x541A57C694 695#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_48 0x541A580696 697#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_49 0x541A584698 699#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_50 0x541A588700 701#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_51 0x541A58C702 703#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_52 0x541A590704 705#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_53 0x541A594706 707#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_54 0x541A598708 709#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_55 0x541A59C710 711#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_56 0x541A5A0712 713#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_57 0x541A5A4714 715#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_58 0x541A5A8716 717#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_59 0x541A5AC718 719#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_60 0x541A5B0720 721#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_61 0x541A5B4722 723#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_62 0x541A5B8724 725#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_63 0x541A5BC726 727#define mmNIC0_QM0_ARB_MST_CRED_INC 0x541A5E0728 729#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_0 0x541A5E4730 731#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_1 0x541A5E8732 733#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_2 0x541A5EC734 735#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_3 0x541A5F0736 737#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_4 0x541A5F4738 739#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_5 0x541A5F8740 741#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_6 0x541A5FC742 743#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_7 0x541A600744 745#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_8 0x541A604746 747#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_9 0x541A608748 749#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_10 0x541A60C750 751#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_11 0x541A610752 753#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_12 0x541A614754 755#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_13 0x541A618756 757#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_14 0x541A61C758 759#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_15 0x541A620760 761#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_16 0x541A624762 763#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_17 0x541A628764 765#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_18 0x541A62C766 767#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_19 0x541A630768 769#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_20 0x541A634770 771#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_21 0x541A638772 773#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_22 0x541A63C774 775#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_23 0x541A640776 777#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_24 0x541A644778 779#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_25 0x541A648780 781#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_26 0x541A64C782 783#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_27 0x541A650784 785#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_28 0x541A654786 787#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_29 0x541A658788 789#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_30 0x541A65C790 791#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_31 0x541A660792 793#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_32 0x541A664794 795#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_33 0x541A668796 797#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_34 0x541A66C798 799#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_35 0x541A670800 801#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_36 0x541A674802 803#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_37 0x541A678804 805#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_38 0x541A67C806 807#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_39 0x541A680808 809#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_40 0x541A684810 811#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_41 0x541A688812 813#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_42 0x541A68C814 815#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_43 0x541A690816 817#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_44 0x541A694818 819#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_45 0x541A698820 821#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_46 0x541A69C822 823#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_47 0x541A6A0824 825#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_48 0x541A6A4826 827#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_49 0x541A6A8828 829#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_50 0x541A6AC830 831#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_51 0x541A6B0832 833#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_52 0x541A6B4834 835#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_53 0x541A6B8836 837#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_54 0x541A6BC838 839#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_55 0x541A6C0840 841#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_56 0x541A6C4842 843#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_57 0x541A6C8844 845#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_58 0x541A6CC846 847#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_59 0x541A6D0848 849#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_60 0x541A6D4850 851#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_61 0x541A6D8852 853#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_62 0x541A6DC854 855#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_63 0x541A6E0856 857#define mmNIC0_QM0_ARB_SLV_MASTER_INC_CRED_OFST 0x541A704858 859#define mmNIC0_QM0_ARB_MST_SLAVE_EN 0x541A708860 861#define mmNIC0_QM0_ARB_MST_SLAVE_EN_1 0x541A70C862 863#define mmNIC0_QM0_ARB_SLV_CHOICE_WDT 0x541A710864 865#define mmNIC0_QM0_ARB_SLV_ID 0x541A714866 867#define mmNIC0_QM0_ARB_MST_QUIET_PER 0x541A718868 869#define mmNIC0_QM0_ARB_MSG_MAX_INFLIGHT 0x541A744870 871#define mmNIC0_QM0_ARB_BASE_LO 0x541A754872 873#define mmNIC0_QM0_ARB_BASE_HI 0x541A758874 875#define mmNIC0_QM0_ARB_STATE_STS 0x541A780876 877#define mmNIC0_QM0_ARB_CHOICE_FULLNESS_STS 0x541A784878 879#define mmNIC0_QM0_ARB_MSG_STS 0x541A788880 881#define mmNIC0_QM0_ARB_SLV_CHOICE_Q_HEAD 0x541A78C882 883#define mmNIC0_QM0_ARB_ERR_CAUSE 0x541A79C884 885#define mmNIC0_QM0_ARB_ERR_MSG_EN 0x541A7A0886 887#define mmNIC0_QM0_ARB_ERR_STS_DRP 0x541A7A8888 889#define mmNIC0_QM0_ARB_MST_CRED_STS 0x541A7B0890 891#define mmNIC0_QM0_ARB_MST_CRED_STS_1 0x541A7B4892 893#define mmNIC0_QM0_CSMR_STRICT_PRIO_CFG 0x541A7FC894 895#define mmNIC0_QM0_ARC_CQ_CFG0 0x541A800896 897#define mmNIC0_QM0_ARC_CQ_CFG1 0x541A804898 899#define mmNIC0_QM0_ARC_CQ_PTR_LO 0x541A808900 901#define mmNIC0_QM0_ARC_CQ_PTR_HI 0x541A80C902 903#define mmNIC0_QM0_ARC_CQ_TSIZE 0x541A810904 905#define mmNIC0_QM0_ARC_CQ_CTL 0x541A814906 907#define mmNIC0_QM0_ARC_CQ_IFIFO_STS 0x541A81C908 909#define mmNIC0_QM0_ARC_CQ_STS0 0x541A820910 911#define mmNIC0_QM0_ARC_CQ_STS1 0x541A824912 913#define mmNIC0_QM0_ARC_CQ_TSIZE_STS 0x541A828914 915#define mmNIC0_QM0_ARC_CQ_PTR_LO_STS 0x541A82C916 917#define mmNIC0_QM0_ARC_CQ_PTR_HI_STS 0x541A830918 919#define mmNIC0_QM0_CP_WR_ARC_ADDR_HI 0x541A834920 921#define mmNIC0_QM0_CP_WR_ARC_ADDR_LO 0x541A838922 923#define mmNIC0_QM0_ARC_CQ_IFIFO_MSG_BASE_HI 0x541A83C924 925#define mmNIC0_QM0_ARC_CQ_IFIFO_MSG_BASE_LO 0x541A840926 927#define mmNIC0_QM0_ARC_CQ_CTL_MSG_BASE_HI 0x541A844928 929#define mmNIC0_QM0_ARC_CQ_CTL_MSG_BASE_LO 0x541A848930 931#define mmNIC0_QM0_CQ_IFIFO_MSG_BASE_HI 0x541A84C932 933#define mmNIC0_QM0_CQ_IFIFO_MSG_BASE_LO 0x541A850934 935#define mmNIC0_QM0_CQ_CTL_MSG_BASE_HI 0x541A854936 937#define mmNIC0_QM0_CQ_CTL_MSG_BASE_LO 0x541A858938 939#define mmNIC0_QM0_ADDR_OVRD 0x541A85C940 941#define mmNIC0_QM0_CQ_IFIFO_CI_0 0x541A860942 943#define mmNIC0_QM0_CQ_IFIFO_CI_1 0x541A864944 945#define mmNIC0_QM0_CQ_IFIFO_CI_2 0x541A868946 947#define mmNIC0_QM0_CQ_IFIFO_CI_3 0x541A86C948 949#define mmNIC0_QM0_CQ_IFIFO_CI_4 0x541A870950 951#define mmNIC0_QM0_ARC_CQ_IFIFO_CI 0x541A874952 953#define mmNIC0_QM0_CQ_CTL_CI_0 0x541A878954 955#define mmNIC0_QM0_CQ_CTL_CI_1 0x541A87C956 957#define mmNIC0_QM0_CQ_CTL_CI_2 0x541A880958 959#define mmNIC0_QM0_CQ_CTL_CI_3 0x541A884960 961#define mmNIC0_QM0_CQ_CTL_CI_4 0x541A888962 963#define mmNIC0_QM0_ARC_CQ_CTL_CI 0x541A88C964 965#define mmNIC0_QM0_CP_CFG 0x541A890966 967#define mmNIC0_QM0_CP_EXT_SWITCH 0x541A894968 969#define mmNIC0_QM0_CP_SWITCH_WD_SET 0x541A898970 971#define mmNIC0_QM0_CP_SWITCH_WD 0x541A89C972 973#define mmNIC0_QM0_ARC_LB_ADDR_BASE_LO 0x541A8A4974 975#define mmNIC0_QM0_ARC_LB_ADDR_BASE_HI 0x541A8A8976 977#define mmNIC0_QM0_ENGINE_BASE_ADDR_HI 0x541A8AC978 979#define mmNIC0_QM0_ENGINE_BASE_ADDR_LO 0x541A8B0980 981#define mmNIC0_QM0_ENGINE_ADDR_RANGE_SIZE 0x541A8B4982 983#define mmNIC0_QM0_QM_ARC_AUX_BASE_ADDR_HI 0x541A8B8984 985#define mmNIC0_QM0_QM_ARC_AUX_BASE_ADDR_LO 0x541A8BC986 987#define mmNIC0_QM0_QM_BASE_ADDR_HI 0x541A8C0988 989#define mmNIC0_QM0_QM_BASE_ADDR_LO 0x541A8C4990 991#define mmNIC0_QM0_ARC_PQC_SECURE_PUSH_IND 0x541A8C8992 993#define mmNIC0_QM0_PQC_STS_0_0 0x541A8D0994 995#define mmNIC0_QM0_PQC_STS_0_1 0x541A8D4996 997#define mmNIC0_QM0_PQC_STS_0_2 0x541A8D8998 999#define mmNIC0_QM0_PQC_STS_0_3 0x541A8DC1000 1001#define mmNIC0_QM0_PQC_STS_1_0 0x541A8E01002 1003#define mmNIC0_QM0_PQC_STS_1_1 0x541A8E41004 1005#define mmNIC0_QM0_PQC_STS_1_2 0x541A8E81006 1007#define mmNIC0_QM0_PQC_STS_1_3 0x541A8EC1008 1009#define mmNIC0_QM0_SEI_STATUS 0x541A8F01010 1011#define mmNIC0_QM0_SEI_MASK 0x541A8F41012 1013#define mmNIC0_QM0_GLBL_ERR_ADDR_LO 0x541AD001014 1015#define mmNIC0_QM0_GLBL_ERR_ADDR_HI 0x541AD041016 1017#define mmNIC0_QM0_GLBL_ERR_WDATA 0x541AD081018 1019#define mmNIC0_QM0_L2H_MASK_LO 0x541AD141020 1021#define mmNIC0_QM0_L2H_MASK_HI 0x541AD181022 1023#define mmNIC0_QM0_L2H_CMPR_LO 0x541AD1C1024 1025#define mmNIC0_QM0_L2H_CMPR_HI 0x541AD201026 1027#define mmNIC0_QM0_LOCAL_RANGE_BASE 0x541AD241028 1029#define mmNIC0_QM0_LOCAL_RANGE_SIZE 0x541AD281030 1031#define mmNIC0_QM0_HBW_RD_RATE_LIM_CFG_1 0x541AD301032 1033#define mmNIC0_QM0_LBW_WR_RATE_LIM_CFG_0 0x541AD341034 1035#define mmNIC0_QM0_LBW_WR_RATE_LIM_CFG_1 0x541AD381036 1037#define mmNIC0_QM0_HBW_RD_RATE_LIM_CFG_0 0x541AD3C1038 1039#define mmNIC0_QM0_IND_GW_APB_CFG 0x541AD401040 1041#define mmNIC0_QM0_IND_GW_APB_WDATA 0x541AD441042 1043#define mmNIC0_QM0_IND_GW_APB_RDATA 0x541AD481044 1045#define mmNIC0_QM0_IND_GW_APB_STATUS 0x541AD4C1046 1047#define mmNIC0_QM0_PERF_CNT_FREE_LO 0x541AD601048 1049#define mmNIC0_QM0_PERF_CNT_FREE_HI 0x541AD641050 1051#define mmNIC0_QM0_PERF_CNT_IDLE_LO 0x541AD681052 1053#define mmNIC0_QM0_PERF_CNT_IDLE_HI 0x541AD6C1054 1055#define mmNIC0_QM0_PERF_CNT_CFG 0x541AD701056 1057#endif /* ASIC_REG_NIC0_QM0_REGS_H_ */1058