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1/* SPDX-License-Identifier: GPL-2.02 *3 * Copyright 2016-2020 HabanaLabs, Ltd.4 * All Rights Reserved.5 *6 */7 8/************************************9 ** This is an auto-generated file **10 ** DO NOT EDIT BELOW **11 ************************************/12 13#ifndef ASIC_REG_NIC0_QPC0_REGS_H_14#define ASIC_REG_NIC0_QPC0_REGS_H_15 16/*17 *****************************************18 * NIC0_QPC019 * (Prototype: NIC_QPC)20 *****************************************21 */22 23#define mmNIC0_QPC0_REQ_QPC_CACHE_INVALIDATE 0x541F00024 25#define mmNIC0_QPC0_REQ_QPC_CACHE_INV_STATUS 0x541F00426 27#define mmNIC0_QPC0_REQ_STATIC_CONFIG 0x541F00828 29#define mmNIC0_QPC0_REQ_BASE_ADDRESS_63_32 0x541F00C30 31#define mmNIC0_QPC0_REQ_BASE_ADDRESS_31_7 0x541F01032 33#define mmNIC0_QPC0_REQ_CLEAN_LINK_LIST 0x541F01434 35#define mmNIC0_QPC0_REQ_ERR_FIFO_PUSH_63_32 0x541F01836 37#define mmNIC0_QPC0_REQ_ERR_FIFO_PUSH_31_0 0x541F01C38 39#define mmNIC0_QPC0_REQ_ERR_QP_STATE_63_32 0x541F02040 41#define mmNIC0_QPC0_REQ_ERR_QP_STATE_31_0 0x541F02442 43#define mmNIC0_QPC0_RETRY_COUNT_MAX 0x541F02844 45#define mmNIC0_QPC0_AXI_PROT 0x541F03046 47#define mmNIC0_QPC0_RES_QPC_CACHE_INVALIDATE 0x541F03448 49#define mmNIC0_QPC0_RES_QPC_CACHE_INV_STATUS 0x541F03850 51#define mmNIC0_QPC0_RES_STATIC_CONFIG 0x541F03C52 53#define mmNIC0_QPC0_RES_BASE_ADDRESS_63_32 0x541F04054 55#define mmNIC0_QPC0_RES_BASE_ADDRESS_31_7 0x541F04456 57#define mmNIC0_QPC0_RES_CLEAN_LINK_LIST 0x541F04858 59#define mmNIC0_QPC0_ERR_FIFO_WRITE_INDEX 0x541F05060 61#define mmNIC0_QPC0_ERR_FIFO_PRODUCER_INDEX 0x541F05462 63#define mmNIC0_QPC0_ERR_FIFO_CONSUMER_INDEX 0x541F05864 65#define mmNIC0_QPC0_ERR_FIFO_MASK 0x541F05C66 67#define mmNIC0_QPC0_ERR_FIFO_CREDIT 0x541F06068 69#define mmNIC0_QPC0_ERR_FIFO_CFG 0x541F06470 71#define mmNIC0_QPC0_ERR_FIFO_INTR_MASK 0x541F06872 73#define mmNIC0_QPC0_ERR_FIFO_BASE_ADDR_63_32 0x541F06C74 75#define mmNIC0_QPC0_ERR_FIFO_BASE_ADDR_31_7 0x541F07076 77#define mmNIC0_QPC0_GW_BUSY 0x541F08078 79#define mmNIC0_QPC0_GW_CTRL 0x541F08480 81#define mmNIC0_QPC0_GW_DATA_0 0x541F08C82 83#define mmNIC0_QPC0_GW_DATA_1 0x541F09084 85#define mmNIC0_QPC0_GW_DATA_2 0x541F09486 87#define mmNIC0_QPC0_GW_DATA_3 0x541F09888 89#define mmNIC0_QPC0_GW_DATA_4 0x541F09C90 91#define mmNIC0_QPC0_GW_DATA_5 0x541F0A092 93#define mmNIC0_QPC0_GW_DATA_6 0x541F0A494 95#define mmNIC0_QPC0_GW_DATA_7 0x541F0A896 97#define mmNIC0_QPC0_GW_DATA_8 0x541F0AC98 99#define mmNIC0_QPC0_GW_DATA_9 0x541F0B0100 101#define mmNIC0_QPC0_GW_DATA_10 0x541F0B4102 103#define mmNIC0_QPC0_GW_DATA_11 0x541F0B8104 105#define mmNIC0_QPC0_GW_DATA_12 0x541F0BC106 107#define mmNIC0_QPC0_GW_DATA_13 0x541F0C0108 109#define mmNIC0_QPC0_GW_DATA_14 0x541F0C4110 111#define mmNIC0_QPC0_GW_DATA_15 0x541F0C8112 113#define mmNIC0_QPC0_GW_DATA_16 0x541F0CC114 115#define mmNIC0_QPC0_GW_DATA_17 0x541F0D0116 117#define mmNIC0_QPC0_GW_DATA_18 0x541F0D4118 119#define mmNIC0_QPC0_GW_DATA_19 0x541F0D8120 121#define mmNIC0_QPC0_GW_DATA_20 0x541F0DC122 123#define mmNIC0_QPC0_GW_DATA_21 0x541F0E0124 125#define mmNIC0_QPC0_GW_DATA_22 0x541F0E4126 127#define mmNIC0_QPC0_GW_DATA_23 0x541F0E8128 129#define mmNIC0_QPC0_GW_DATA_24 0x541F0EC130 131#define mmNIC0_QPC0_GW_DATA_25 0x541F0F0132 133#define mmNIC0_QPC0_GW_DATA_26 0x541F0F4134 135#define mmNIC0_QPC0_GW_DATA_27 0x541F0F8136 137#define mmNIC0_QPC0_GW_DATA_28 0x541F0FC138 139#define mmNIC0_QPC0_GW_DATA_29 0x541F100140 141#define mmNIC0_QPC0_GW_DATA_30 0x541F104142 143#define mmNIC0_QPC0_GW_DATA_31 0x541F108144 145#define mmNIC0_QPC0_GW_MASK_0 0x541F124146 147#define mmNIC0_QPC0_GW_MASK_1 0x541F128148 149#define mmNIC0_QPC0_GW_MASK_2 0x541F12C150 151#define mmNIC0_QPC0_GW_MASK_3 0x541F130152 153#define mmNIC0_QPC0_GW_MASK_4 0x541F134154 155#define mmNIC0_QPC0_GW_MASK_5 0x541F138156 157#define mmNIC0_QPC0_GW_MASK_6 0x541F13C158 159#define mmNIC0_QPC0_GW_MASK_7 0x541F140160 161#define mmNIC0_QPC0_GW_MASK_8 0x541F144162 163#define mmNIC0_QPC0_GW_MASK_9 0x541F148164 165#define mmNIC0_QPC0_GW_MASK_10 0x541F14C166 167#define mmNIC0_QPC0_GW_MASK_11 0x541F150168 169#define mmNIC0_QPC0_GW_MASK_12 0x541F154170 171#define mmNIC0_QPC0_GW_MASK_13 0x541F158172 173#define mmNIC0_QPC0_GW_MASK_14 0x541F15C174 175#define mmNIC0_QPC0_GW_MASK_15 0x541F160176 177#define mmNIC0_QPC0_GW_MASK_16 0x541F164178 179#define mmNIC0_QPC0_GW_MASK_17 0x541F168180 181#define mmNIC0_QPC0_GW_MASK_18 0x541F16C182 183#define mmNIC0_QPC0_GW_MASK_19 0x541F170184 185#define mmNIC0_QPC0_GW_MASK_20 0x541F174186 187#define mmNIC0_QPC0_GW_MASK_21 0x541F178188 189#define mmNIC0_QPC0_GW_MASK_22 0x541F17C190 191#define mmNIC0_QPC0_GW_MASK_23 0x541F180192 193#define mmNIC0_QPC0_GW_MASK_24 0x541F184194 195#define mmNIC0_QPC0_GW_MASK_25 0x541F188196 197#define mmNIC0_QPC0_GW_MASK_26 0x541F18C198 199#define mmNIC0_QPC0_GW_MASK_27 0x541F190200 201#define mmNIC0_QPC0_GW_MASK_28 0x541F194202 203#define mmNIC0_QPC0_GW_MASK_29 0x541F198204 205#define mmNIC0_QPC0_GW_MASK_30 0x541F19C206 207#define mmNIC0_QPC0_GW_MASK_31 0x541F1A0208 209#define mmNIC0_QPC0_CC_TIMEOUT 0x541F1B0210 211#define mmNIC0_QPC0_CC_WINDOW_INC_EN 0x541F1FC212 213#define mmNIC0_QPC0_CC_TICK_WRAP 0x541F200214 215#define mmNIC0_QPC0_CC_ROLLBACK 0x541F204216 217#define mmNIC0_QPC0_CC_MAX_WINDOW_SIZE 0x541F208218 219#define mmNIC0_QPC0_CC_MIN_WINDOW_SIZE 0x541F20C220 221#define mmNIC0_QPC0_CC_ALPHA_LINEAR_0 0x541F210222 223#define mmNIC0_QPC0_CC_ALPHA_LINEAR_1 0x541F214224 225#define mmNIC0_QPC0_CC_ALPHA_LINEAR_2 0x541F218226 227#define mmNIC0_QPC0_CC_ALPHA_LINEAR_3 0x541F21C228 229#define mmNIC0_QPC0_CC_ALPHA_LINEAR_4 0x541F220230 231#define mmNIC0_QPC0_CC_ALPHA_LINEAR_5 0x541F224232 233#define mmNIC0_QPC0_CC_ALPHA_LINEAR_6 0x541F228234 235#define mmNIC0_QPC0_CC_ALPHA_LINEAR_7 0x541F22C236 237#define mmNIC0_QPC0_CC_ALPHA_LINEAR_8 0x541F230238 239#define mmNIC0_QPC0_CC_ALPHA_LINEAR_9 0x541F234240 241#define mmNIC0_QPC0_CC_ALPHA_LINEAR_10 0x541F238242 243#define mmNIC0_QPC0_CC_ALPHA_LINEAR_11 0x541F23C244 245#define mmNIC0_QPC0_CC_ALPHA_LINEAR_12 0x541F240246 247#define mmNIC0_QPC0_CC_ALPHA_LINEAR_13 0x541F244248 249#define mmNIC0_QPC0_CC_ALPHA_LINEAR_14 0x541F248250 251#define mmNIC0_QPC0_CC_ALPHA_LINEAR_15 0x541F24C252 253#define mmNIC0_QPC0_CC_ALPHA_LOG_0 0x541F250254 255#define mmNIC0_QPC0_CC_ALPHA_LOG_1 0x541F254256 257#define mmNIC0_QPC0_CC_ALPHA_LOG_2 0x541F258258 259#define mmNIC0_QPC0_CC_ALPHA_LOG_3 0x541F25C260 261#define mmNIC0_QPC0_CC_ALPHA_LOG_4 0x541F260262 263#define mmNIC0_QPC0_CC_ALPHA_LOG_5 0x541F264264 265#define mmNIC0_QPC0_CC_ALPHA_LOG_6 0x541F268266 267#define mmNIC0_QPC0_CC_ALPHA_LOG_7 0x541F26C268 269#define mmNIC0_QPC0_CC_ALPHA_LOG_8 0x541F270270 271#define mmNIC0_QPC0_CC_ALPHA_LOG_9 0x541F274272 273#define mmNIC0_QPC0_CC_ALPHA_LOG_10 0x541F278274 275#define mmNIC0_QPC0_CC_ALPHA_LOG_11 0x541F27C276 277#define mmNIC0_QPC0_CC_ALPHA_LOG_12 0x541F280278 279#define mmNIC0_QPC0_CC_ALPHA_LOG_13 0x541F284280 281#define mmNIC0_QPC0_CC_ALPHA_LOG_14 0x541F288282 283#define mmNIC0_QPC0_CC_ALPHA_LOG_15 0x541F28C284 285#define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_0 0x541F290286 287#define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_1 0x541F294288 289#define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_2 0x541F298290 291#define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_3 0x541F29C292 293#define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_4 0x541F2A0294 295#define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_5 0x541F2A4296 297#define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_6 0x541F2A8298 299#define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_7 0x541F2AC300 301#define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_8 0x541F2B0302 303#define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_9 0x541F2B4304 305#define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_10 0x541F2B8306 307#define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_11 0x541F2BC308 309#define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_12 0x541F2C0310 311#define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_13 0x541F2C4312 313#define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_14 0x541F2C8314 315#define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_15 0x541F2CC316 317#define mmNIC0_QPC0_CC_WINDOW_INC_0 0x541F2D0318 319#define mmNIC0_QPC0_CC_WINDOW_INC_1 0x541F2D4320 321#define mmNIC0_QPC0_CC_WINDOW_INC_2 0x541F2D8322 323#define mmNIC0_QPC0_CC_WINDOW_INC_3 0x541F2DC324 325#define mmNIC0_QPC0_CC_WINDOW_INC_4 0x541F2E0326 327#define mmNIC0_QPC0_CC_WINDOW_INC_5 0x541F2E4328 329#define mmNIC0_QPC0_CC_WINDOW_INC_6 0x541F2E8330 331#define mmNIC0_QPC0_CC_WINDOW_INC_7 0x541F2EC332 333#define mmNIC0_QPC0_CC_WINDOW_INC_8 0x541F2F0334 335#define mmNIC0_QPC0_CC_WINDOW_INC_9 0x541F2F4336 337#define mmNIC0_QPC0_CC_WINDOW_INC_10 0x541F2F8338 339#define mmNIC0_QPC0_CC_WINDOW_INC_11 0x541F2FC340 341#define mmNIC0_QPC0_CC_WINDOW_INC_12 0x541F300342 343#define mmNIC0_QPC0_CC_WINDOW_INC_13 0x541F304344 345#define mmNIC0_QPC0_CC_WINDOW_INC_14 0x541F308346 347#define mmNIC0_QPC0_CC_WINDOW_INC_15 0x541F30C348 349#define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_0 0x541F310350 351#define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_1 0x541F314352 353#define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_2 0x541F318354 355#define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_3 0x541F31C356 357#define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_4 0x541F320358 359#define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_5 0x541F324360 361#define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_6 0x541F328362 363#define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_7 0x541F32C364 365#define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_8 0x541F330366 367#define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_9 0x541F334368 369#define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_10 0x541F338370 371#define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_11 0x541F33C372 373#define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_12 0x541F340374 375#define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_13 0x541F344376 377#define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_14 0x541F348378 379#define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_15 0x541F34C380 381#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_0 0x541F360382 383#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_1 0x541F364384 385#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_2 0x541F368386 387#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_3 0x541F36C388 389#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_4 0x541F370390 391#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_5 0x541F374392 393#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_6 0x541F378394 395#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_7 0x541F37C396 397#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_8 0x541F380398 399#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_9 0x541F384400 401#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_10 0x541F388402 403#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_11 0x541F38C404 405#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_12 0x541F390406 407#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_13 0x541F394408 409#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_14 0x541F398410 411#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_15 0x541F39C412 413#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_16 0x541F3A0414 415#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_17 0x541F3A4416 417#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_18 0x541F3A8418 419#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_19 0x541F3AC420 421#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_20 0x541F3B0422 423#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_21 0x541F3B4424 425#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_22 0x541F3B8426 427#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_23 0x541F3BC428 429#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_24 0x541F3C0430 431#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_25 0x541F3C4432 433#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_26 0x541F3C8434 435#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_27 0x541F3CC436 437#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_28 0x541F3D0438 439#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_29 0x541F3D4440 441#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_30 0x541F3D8442 443#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_31 0x541F3DC444 445#define mmNIC0_QPC0_DB_FIFO_CFG_0 0x541F3E0446 447#define mmNIC0_QPC0_DB_FIFO_CFG_1 0x541F3E4448 449#define mmNIC0_QPC0_DB_FIFO_CFG_2 0x541F3E8450 451#define mmNIC0_QPC0_DB_FIFO_CFG_3 0x541F3EC452 453#define mmNIC0_QPC0_DB_FIFO_CFG_4 0x541F3F0454 455#define mmNIC0_QPC0_DB_FIFO_CFG_5 0x541F3F4456 457#define mmNIC0_QPC0_DB_FIFO_CFG_6 0x541F3F8458 459#define mmNIC0_QPC0_DB_FIFO_CFG_7 0x541F3FC460 461#define mmNIC0_QPC0_DB_FIFO_CFG_8 0x541F400462 463#define mmNIC0_QPC0_DB_FIFO_CFG_9 0x541F404464 465#define mmNIC0_QPC0_DB_FIFO_CFG_10 0x541F408466 467#define mmNIC0_QPC0_DB_FIFO_CFG_11 0x541F40C468 469#define mmNIC0_QPC0_DB_FIFO_CFG_12 0x541F410470 471#define mmNIC0_QPC0_DB_FIFO_CFG_13 0x541F414472 473#define mmNIC0_QPC0_DB_FIFO_CFG_14 0x541F418474 475#define mmNIC0_QPC0_DB_FIFO_CFG_15 0x541F41C476 477#define mmNIC0_QPC0_DB_FIFO_CFG_16 0x541F420478 479#define mmNIC0_QPC0_DB_FIFO_CFG_17 0x541F424480 481#define mmNIC0_QPC0_DB_FIFO_CFG_18 0x541F428482 483#define mmNIC0_QPC0_DB_FIFO_CFG_19 0x541F42C484 485#define mmNIC0_QPC0_DB_FIFO_CFG_20 0x541F430486 487#define mmNIC0_QPC0_DB_FIFO_CFG_21 0x541F434488 489#define mmNIC0_QPC0_DB_FIFO_CFG_22 0x541F438490 491#define mmNIC0_QPC0_DB_FIFO_CFG_23 0x541F43C492 493#define mmNIC0_QPC0_DB_FIFO_CFG_24 0x541F440494 495#define mmNIC0_QPC0_DB_FIFO_CFG_25 0x541F444496 497#define mmNIC0_QPC0_DB_FIFO_CFG_26 0x541F448498 499#define mmNIC0_QPC0_DB_FIFO_CFG_27 0x541F44C500 501#define mmNIC0_QPC0_DB_FIFO_CFG_28 0x541F450502 503#define mmNIC0_QPC0_DB_FIFO_CFG_29 0x541F454504 505#define mmNIC0_QPC0_DB_FIFO_CFG_30 0x541F458506 507#define mmNIC0_QPC0_DB_FIFO_CFG_31 0x541F45C508 509#define mmNIC0_QPC0_SECURED_DB_FIRST32 0x541F460510 511#define mmNIC0_QPC0_SECURED_DB_SECOND32 0x541F464512 513#define mmNIC0_QPC0_SECURED_DB_THIRD32 0x541F468514 515#define mmNIC0_QPC0_SECURED_DB_FOURTH32 0x541F46C516 517#define mmNIC0_QPC0_PRIVILEGE_DB_FIRST32 0x541F470518 519#define mmNIC0_QPC0_PRIVILEGE_DB_SECOND32 0x541F474520 521#define mmNIC0_QPC0_PRIVILEGE_DB_THIRD32 0x541F478522 523#define mmNIC0_QPC0_PRIVILEGE_DB_FOURTH32 0x541F47C524 525#define mmNIC0_QPC0_DBG_INDICATION 0x541F480526 527#define mmNIC0_QPC0_WTD_WC_FSM 0x541F484528 529#define mmNIC0_QPC0_WTD_SLICE_FSM 0x541F488530 531#define mmNIC0_QPC0_REQ_TX_EMPTY_CNT 0x541F48C532 533#define mmNIC0_QPC0_RES_TX_EMPTY_CNT 0x541F490534 535#define mmNIC0_QPC0_NUM_ROLLBACKS 0x541F494536 537#define mmNIC0_QPC0_LAST_QP_ROLLED_BACK 0x541F498538 539#define mmNIC0_QPC0_NUM_TIMEOUTS 0x541F49C540 541#define mmNIC0_QPC0_LAST_QP_TIMED_OUT 0x541F4A0542 543#define mmNIC0_QPC0_WTD_SLICE_FSM_HI 0x541F4A4544 545#define mmNIC0_QPC0_INTERRUPT_BASE_0 0x541F4B0546 547#define mmNIC0_QPC0_INTERRUPT_BASE_1 0x541F4B4548 549#define mmNIC0_QPC0_INTERRUPT_BASE_2 0x541F4B8550 551#define mmNIC0_QPC0_INTERRUPT_BASE_3 0x541F4BC552 553#define mmNIC0_QPC0_INTERRUPT_BASE_4 0x541F4C0554 555#define mmNIC0_QPC0_INTERRUPT_BASE_5 0x541F4C4556 557#define mmNIC0_QPC0_INTERRUPT_BASE_6 0x541F4C8558 559#define mmNIC0_QPC0_INTERRUPT_BASE_7 0x541F4CC560 561#define mmNIC0_QPC0_INTERRUPT_BASE_8 0x541F4D0562 563#define mmNIC0_QPC0_INTERRUPT_BASE_9 0x541F4D4564 565#define mmNIC0_QPC0_INTERRUPT_BASE_10 0x541F4D8566 567#define mmNIC0_QPC0_INTERRUPT_DATA_0 0x541F4DC568 569#define mmNIC0_QPC0_INTERRUPT_DATA_1 0x541F4E0570 571#define mmNIC0_QPC0_INTERRUPT_DATA_2 0x541F4E4572 573#define mmNIC0_QPC0_INTERRUPT_DATA_3 0x541F4E8574 575#define mmNIC0_QPC0_INTERRUPT_DATA_4 0x541F4EC576 577#define mmNIC0_QPC0_INTERRUPT_DATA_5 0x541F4F0578 579#define mmNIC0_QPC0_INTERRUPT_DATA_6 0x541F4F4580 581#define mmNIC0_QPC0_INTERRUPT_DATA_7 0x541F4F8582 583#define mmNIC0_QPC0_INTERRUPT_DATA_8 0x541F4FC584 585#define mmNIC0_QPC0_INTERRUPT_DATA_9 0x541F500586 587#define mmNIC0_QPC0_INTERRUPT_DATA_10 0x541F504588 589#define mmNIC0_QPC0_DBG_COUNT_SELECT_0 0x541F600590 591#define mmNIC0_QPC0_DBG_COUNT_SELECT_1 0x541F604592 593#define mmNIC0_QPC0_DBG_COUNT_SELECT_2 0x541F608594 595#define mmNIC0_QPC0_DBG_COUNT_SELECT_3 0x541F60C596 597#define mmNIC0_QPC0_DBG_COUNT_SELECT_4 0x541F610598 599#define mmNIC0_QPC0_DBG_COUNT_SELECT_5 0x541F614600 601#define mmNIC0_QPC0_DBG_COUNT_SELECT_6 0x541F618602 603#define mmNIC0_QPC0_DBG_COUNT_SELECT_7 0x541F61C604 605#define mmNIC0_QPC0_DBG_COUNT_SELECT_8 0x541F620606 607#define mmNIC0_QPC0_DBG_COUNT_SELECT_9 0x541F624608 609#define mmNIC0_QPC0_DBG_COUNT_SELECT_10 0x541F628610 611#define mmNIC0_QPC0_DBG_COUNT_SELECT_11 0x541F62C612 613#define mmNIC0_QPC0_DOORBELL_SECURITY 0x541F648614 615#define mmNIC0_QPC0_DBG_CFG 0x541F64C616 617#define mmNIC0_QPC0_RES_RING0_PI 0x541F650618 619#define mmNIC0_QPC0_RES_RING0_CI 0x541F654620 621#define mmNIC0_QPC0_RES_RING0_CFG 0x541F658622 623#define mmNIC0_QPC0_RES_RING1_PI 0x541F65C624 625#define mmNIC0_QPC0_RES_RING1_CI 0x541F660626 627#define mmNIC0_QPC0_RES_RING1_CFG 0x541F664628 629#define mmNIC0_QPC0_RES_RING2_PI 0x541F668630 631#define mmNIC0_QPC0_RES_RING2_CI 0x541F66C632 633#define mmNIC0_QPC0_RES_RING2_CFG 0x541F670634 635#define mmNIC0_QPC0_RES_RING3_PI 0x541F674636 637#define mmNIC0_QPC0_RES_RING3_CI 0x541F678638 639#define mmNIC0_QPC0_RES_RING3_CFG 0x541F67C640 641#define mmNIC0_QPC0_REQ_RING0_CI 0x541F680642 643#define mmNIC0_QPC0_REQ_RING1_CI 0x541F684644 645#define mmNIC0_QPC0_REQ_RING2_CI 0x541F688646 647#define mmNIC0_QPC0_REQ_RING3_CI 0x541F68C648 649#define mmNIC0_QPC0_INTERRUPT_CAUSE 0x541F690650 651#define mmNIC0_QPC0_INTERRUPT_MASK 0x541F694652 653#define mmNIC0_QPC0_INTERRUPT_CLR 0x541F698654 655#define mmNIC0_QPC0_INTERRUPT_EN 0x541F69C656 657#define mmNIC0_QPC0_INTERRUPT_CFG 0x541F6F0658 659#define mmNIC0_QPC0_INTERRUPT_RESP_ERR_CAUSE 0x541F6F4660 661#define mmNIC0_QPC0_INTERRUPT_RESP_ERR_MASK 0x541F6F8662 663#define mmNIC0_QPC0_INTERRUPR_RESP_ERR_CLR 0x541F700664 665#define mmNIC0_QPC0_TMR_GW_VALID 0x541F704666 667#define mmNIC0_QPC0_TMR_GW_DATA0 0x541F708668 669#define mmNIC0_QPC0_TMR_GW_DATA1 0x541F70C670 671#define mmNIC0_QPC0_RNR_RETRY_COUNT_EN 0x541F710672 673#define mmNIC0_QPC0_EVENT_QUE_BASE_ADDR_63_32 0x541F830674 675#define mmNIC0_QPC0_EVENT_QUE_BASE_ADDR_31_7 0x541F834676 677#define mmNIC0_QPC0_EVENT_QUE_LOG_SIZE 0x541F838678 679#define mmNIC0_QPC0_EVENT_QUE_WRITE_INDEX 0x541F83C680 681#define mmNIC0_QPC0_EVENT_QUE_PRODUCER_INDEX 0x541F840682 683#define mmNIC0_QPC0_EVENT_QUE_PI_ADDR_63_32 0x541F844684 685#define mmNIC0_QPC0_EVENT_QUE_PI_ADDR_31_7 0x541F848686 687#define mmNIC0_QPC0_EVENT_QUE_CONSUMER_INDEX_CB 0x541F84C688 689#define mmNIC0_QPC0_EVENT_QUE_CFG 0x541F850690 691#define mmNIC0_QPC0_LBW_PROT 0x541F858692 693#define mmNIC0_QPC0_MEM_WRITE_INIT 0x541F85C694 695#define mmNIC0_QPC0_QMAN_DOORBELL 0x541F8E8696 697#define mmNIC0_QPC0_QMAN_DOORBELL_QPN 0x541F8EC698 699#define mmNIC0_QPC0_SECURED_CQ_NUMBER 0x541F8F0700 701#define mmNIC0_QPC0_SECURED_CQ_CONSUMER_INDEX 0x541F8F4702 703#define mmNIC0_QPC0_PRIVILEGE_CQ_NUMBER 0x541F8F8704 705#define mmNIC0_QPC0_PRIVILEGE_CQ_CONSUMER_INDEX 0x541F8FC706 707#define mmNIC0_QPC0_TX_WQ_BASE_ADDR_63_32_0 0x541F900708 709#define mmNIC0_QPC0_TX_WQ_BASE_ADDR_63_32_1 0x541F904710 711#define mmNIC0_QPC0_TX_WQ_BASE_ADDR_63_32_2 0x541F908712 713#define mmNIC0_QPC0_TX_WQ_BASE_ADDR_63_32_3 0x541F90C714 715#define mmNIC0_QPC0_TX_WQ_BASE_ADDR_31_0_0 0x541F910716 717#define mmNIC0_QPC0_TX_WQ_BASE_ADDR_31_0_1 0x541F914718 719#define mmNIC0_QPC0_TX_WQ_BASE_ADDR_31_0_2 0x541F918720 721#define mmNIC0_QPC0_TX_WQ_BASE_ADDR_31_0_3 0x541F91C722 723#define mmNIC0_QPC0_LOG_MAX_TX_WQ_SIZE_0 0x541F920724 725#define mmNIC0_QPC0_LOG_MAX_TX_WQ_SIZE_1 0x541F924726 727#define mmNIC0_QPC0_LOG_MAX_TX_WQ_SIZE_2 0x541F928728 729#define mmNIC0_QPC0_LOG_MAX_TX_WQ_SIZE_3 0x541F92C730 731#define mmNIC0_QPC0_MMU_BYPASS_TX_WQ_0 0x541F930732 733#define mmNIC0_QPC0_MMU_BYPASS_TX_WQ_1 0x541F934734 735#define mmNIC0_QPC0_MMU_BYPASS_TX_WQ_2 0x541F938736 737#define mmNIC0_QPC0_MMU_BYPASS_TX_WQ_3 0x541F93C738 739#define mmNIC0_QPC0_RX_WQ_BASE_ADDR_63_32_0 0x541F940740 741#define mmNIC0_QPC0_RX_WQ_BASE_ADDR_63_32_1 0x541F944742 743#define mmNIC0_QPC0_RX_WQ_BASE_ADDR_63_32_2 0x541F948744 745#define mmNIC0_QPC0_RX_WQ_BASE_ADDR_63_32_3 0x541F94C746 747#define mmNIC0_QPC0_RX_WQ_BASE_ADDR_31_0_0 0x541F950748 749#define mmNIC0_QPC0_RX_WQ_BASE_ADDR_31_0_1 0x541F954750 751#define mmNIC0_QPC0_RX_WQ_BASE_ADDR_31_0_2 0x541F958752 753#define mmNIC0_QPC0_RX_WQ_BASE_ADDR_31_0_3 0x541F95C754 755#define mmNIC0_QPC0_LOG_MAX_RX_WQ_SIZE_0 0x541F960756 757#define mmNIC0_QPC0_LOG_MAX_RX_WQ_SIZE_1 0x541F964758 759#define mmNIC0_QPC0_LOG_MAX_RX_WQ_SIZE_2 0x541F968760 761#define mmNIC0_QPC0_LOG_MAX_RX_WQ_SIZE_3 0x541F96C762 763#define mmNIC0_QPC0_MMU_BYPASS_RX_WQ_0 0x541F970764 765#define mmNIC0_QPC0_MMU_BYPASS_RX_WQ_1 0x541F974766 767#define mmNIC0_QPC0_MMU_BYPASS_RX_WQ_2 0x541F978768 769#define mmNIC0_QPC0_MMU_BYPASS_RX_WQ_3 0x541F97C770 771#define mmNIC0_QPC0_WQE_MEM_WRITE_AXI_PROT 0x541F980772 773#define mmNIC0_QPC0_WQ_UPPER_THRESHOLD 0x541F984774 775#define mmNIC0_QPC0_WQ_LOWER_THRESHOLD 0x541F988776 777#define mmNIC0_QPC0_WQ_BP_2ARC_ADDR 0x541F98C778 779#define mmNIC0_QPC0_WQ_BP_2QMAN_ADDR 0x541F990780 781#define mmNIC0_QPC0_WTD_CONFIG 0x541F994782 783#define mmNIC0_QPC0_REQTX_ERR_FIFO_PUSH_63_32 0x541F998784 785#define mmNIC0_QPC0_REQTX_ERR_FIFO_PUSH_31_0 0x541F99C786 787#define mmNIC0_QPC0_REQTX_ERR_QP_STATE_63_32 0x541F9A0788 789#define mmNIC0_QPC0_REQTX_ERR_QP_STATE_31_0 0x541F9A4790 791#define mmNIC0_QPC0_EVENT_QUE_CONSUMER_INDEX 0x541F9A8792 793#define mmNIC0_QPC0_ARM_CQ_NUM 0x541F9AC794 795#define mmNIC0_QPC0_ARM_CQ_INDEX 0x541F9B0796 797#define mmNIC0_QPC0_QPC_CLOCK_GATE 0x541F9B4798 799#define mmNIC0_QPC0_QPC_CLOCK_GATE_DIS 0x541F9B8800 801#define mmNIC0_QPC0_CONG_QUE_BASE_ADDR_63_32 0x541F9BC802 803#define mmNIC0_QPC0_CONG_QUE_BASE_ADDR_31_7 0x541F9C0804 805#define mmNIC0_QPC0_CONG_QUE_LOG_SIZE 0x541F9C4806 807#define mmNIC0_QPC0_CONG_QUE_WRITE_INDEX 0x541F9C8808 809#define mmNIC0_QPC0_CONG_QUE_PRODUCER_INDEX 0x541F9CC810 811#define mmNIC0_QPC0_CONG_QUE_PI_ADDR_63_32 0x541F9D0812 813#define mmNIC0_QPC0_CONG_QUE_PI_ADDR_31_7 0x541F9D4814 815#define mmNIC0_QPC0_CONG_QUE_CONSUMER_INDEX_CB 0x541F9D8816 817#define mmNIC0_QPC0_CONG_QUE_CFG 0x541F9DC818 819#define mmNIC0_QPC0_CONG_QUE_CONSUMER_INDEX 0x541F9E0820 821#define mmNIC0_QPC0_LINEAR_WQE_STATIC_0 0x541FA00822 823#define mmNIC0_QPC0_LINEAR_WQE_STATIC_1 0x541FA04824 825#define mmNIC0_QPC0_LINEAR_WQE_STATIC_2 0x541FA08826 827#define mmNIC0_QPC0_LINEAR_WQE_STATIC_3 0x541FA0C828 829#define mmNIC0_QPC0_LINEAR_WQE_STATIC_4 0x541FA10830 831#define mmNIC0_QPC0_LINEAR_WQE_STATIC_5 0x541FA14832 833#define mmNIC0_QPC0_LINEAR_WQE_STATIC_6 0x541FA18834 835#define mmNIC0_QPC0_LINEAR_WQE_STATIC_7 0x541FA1C836 837#define mmNIC0_QPC0_LINEAR_WQE_STATIC_8 0x541FA20838 839#define mmNIC0_QPC0_LINEAR_WQE_STATIC_9 0x541FA24840 841#define mmNIC0_QPC0_LINEAR_WQE_DYNAMIC_0 0x541FA40842 843#define mmNIC0_QPC0_LINEAR_WQE_DYNAMIC_1 0x541FA44844 845#define mmNIC0_QPC0_LINEAR_WQE_DYNAMIC_2 0x541FA48846 847#define mmNIC0_QPC0_LINEAR_WQE_DYNAMIC_3 0x541FA4C848 849#define mmNIC0_QPC0_LINEAR_WQE_DYNAMIC_4 0x541FA50850 851#define mmNIC0_QPC0_LINEAR_WQE_DYNAMIC_5 0x541FA54852 853#define mmNIC0_QPC0_LINEAR_WQE_QPN 0x541FA58854 855#define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_0 0x541FA80856 857#define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_1 0x541FA84858 859#define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_2 0x541FA88860 861#define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_3 0x541FA8C862 863#define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_4 0x541FA90864 865#define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_5 0x541FA94866 867#define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_6 0x541FA98868 869#define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_7 0x541FA9C870 871#define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_8 0x541FAA0872 873#define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_9 0x541FAA4874 875#define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_10 0x541FAA8876 877#define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_11 0x541FAAC878 879#define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_12 0x541FAB0880 881#define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_13 0x541FAB4882 883#define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_14 0x541FAB8884 885#define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_15 0x541FABC886 887#define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_16 0x541FAC0888 889#define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_17 0x541FAC4890 891#define mmNIC0_QPC0_MULTI_STRIDE_WQE_DYNAMIC_0 0x541FAE0892 893#define mmNIC0_QPC0_MULTI_STRIDE_WQE_DYNAMIC_1 0x541FAE4894 895#define mmNIC0_QPC0_MULTI_STRIDE_WQE_DYNAMIC_2 0x541FAE8896 897#define mmNIC0_QPC0_MULTI_STRIDE_WQE_DYNAMIC_3 0x541FAEC898 899#define mmNIC0_QPC0_MULTI_STRIDE_WQE_DYNAMIC_4 0x541FAF0900 901#define mmNIC0_QPC0_MULTI_STRIDE_WQE_DYNAMIC_5 0x541FAF4902 903#define mmNIC0_QPC0_MULTI_STRIDE_WQE_QPN 0x541FAF8904 905#endif /* ASIC_REG_NIC0_QPC0_REGS_H_ */906