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1/* SPDX-License-Identifier: GPL-2.02 *3 * Copyright 2016-2020 HabanaLabs, Ltd.4 * All Rights Reserved.5 *6 */7 8/************************************9 ** This is an auto-generated file **10 ** DO NOT EDIT BELOW **11 ************************************/12 13#ifndef ASIC_REG_PDMA0_QM_MASKS_H_14#define ASIC_REG_PDMA0_QM_MASKS_H_15 16/*17 *****************************************18 * PDMA0_QM19 * (Prototype: QMAN)20 *****************************************21 */22 23/* PDMA0_QM_GLBL_CFG0 */24#define PDMA0_QM_GLBL_CFG0_PQF_EN_SHIFT 025#define PDMA0_QM_GLBL_CFG0_PQF_EN_MASK 0xF26#define PDMA0_QM_GLBL_CFG0_CQF_EN_SHIFT 427#define PDMA0_QM_GLBL_CFG0_CQF_EN_MASK 0x1F028#define PDMA0_QM_GLBL_CFG0_CP_EN_SHIFT 929#define PDMA0_QM_GLBL_CFG0_CP_EN_MASK 0x3E0030#define PDMA0_QM_GLBL_CFG0_ARC_CQF_EN_SHIFT 1431#define PDMA0_QM_GLBL_CFG0_ARC_CQF_EN_MASK 0x400032 33/* PDMA0_QM_GLBL_CFG1 */34#define PDMA0_QM_GLBL_CFG1_PQF_STOP_SHIFT 035#define PDMA0_QM_GLBL_CFG1_PQF_STOP_MASK 0xF36#define PDMA0_QM_GLBL_CFG1_CQF_STOP_SHIFT 437#define PDMA0_QM_GLBL_CFG1_CQF_STOP_MASK 0x1F038#define PDMA0_QM_GLBL_CFG1_CP_STOP_SHIFT 939#define PDMA0_QM_GLBL_CFG1_CP_STOP_MASK 0x3E0040#define PDMA0_QM_GLBL_CFG1_PQF_FLUSH_SHIFT 1641#define PDMA0_QM_GLBL_CFG1_PQF_FLUSH_MASK 0xF000042#define PDMA0_QM_GLBL_CFG1_CQF_FLUSH_SHIFT 2043#define PDMA0_QM_GLBL_CFG1_CQF_FLUSH_MASK 0x1F0000044#define PDMA0_QM_GLBL_CFG1_CP_FLUSH_SHIFT 2545#define PDMA0_QM_GLBL_CFG1_CP_FLUSH_MASK 0x3E00000046 47/* PDMA0_QM_GLBL_CFG2 */48#define PDMA0_QM_GLBL_CFG2_ARC_CQF_STOP_SHIFT 049#define PDMA0_QM_GLBL_CFG2_ARC_CQF_STOP_MASK 0x150#define PDMA0_QM_GLBL_CFG2_ARC_CQF_FLUSH_SHIFT 151#define PDMA0_QM_GLBL_CFG2_ARC_CQF_FLUSH_MASK 0x252#define PDMA0_QM_GLBL_CFG2_ARC_HBW_AWUSER_OVRD_SHIFT 453#define PDMA0_QM_GLBL_CFG2_ARC_HBW_AWUSER_OVRD_MASK 0x1054#define PDMA0_QM_GLBL_CFG2_ARC_HBW_ARUSER_OVRD_SHIFT 555#define PDMA0_QM_GLBL_CFG2_ARC_HBW_ARUSER_OVRD_MASK 0x2056#define PDMA0_QM_GLBL_CFG2_ARC_LBW_AWUSER_OVRD_SHIFT 657#define PDMA0_QM_GLBL_CFG2_ARC_LBW_AWUSER_OVRD_MASK 0x4058#define PDMA0_QM_GLBL_CFG2_ARC_LBW_ARUSER_OVRD_SHIFT 759#define PDMA0_QM_GLBL_CFG2_ARC_LBW_ARUSER_OVRD_MASK 0x8060#define PDMA0_QM_GLBL_CFG2_ARC_HBW_AWPROT_OVRD_SHIFT 861#define PDMA0_QM_GLBL_CFG2_ARC_HBW_AWPROT_OVRD_MASK 0x10062#define PDMA0_QM_GLBL_CFG2_ARC_HBW_ARPROT_OVRD_SHIFT 963#define PDMA0_QM_GLBL_CFG2_ARC_HBW_ARPROT_OVRD_MASK 0x20064#define PDMA0_QM_GLBL_CFG2_ARC_LBW_AWPROT_OVRD_SHIFT 1065#define PDMA0_QM_GLBL_CFG2_ARC_LBW_AWPROT_OVRD_MASK 0x40066#define PDMA0_QM_GLBL_CFG2_ARC_LBW_ARPROT_OVRD_SHIFT 1167#define PDMA0_QM_GLBL_CFG2_ARC_LBW_ARPROT_OVRD_MASK 0x80068#define PDMA0_QM_GLBL_CFG2_ARC_HBW_AWCACHE_OVRD_SHIFT 1269#define PDMA0_QM_GLBL_CFG2_ARC_HBW_AWCACHE_OVRD_MASK 0x100070#define PDMA0_QM_GLBL_CFG2_ARC_HBW_ARCACHE_OVRD_SHIFT 1371#define PDMA0_QM_GLBL_CFG2_ARC_HBW_ARCACHE_OVRD_MASK 0x200072#define PDMA0_QM_GLBL_CFG2_ARC_LBW_AWCACHE_OVRD_SHIFT 1473#define PDMA0_QM_GLBL_CFG2_ARC_LBW_AWCACHE_OVRD_MASK 0x400074#define PDMA0_QM_GLBL_CFG2_ARC_LBW_ARCACHE_OVRD_SHIFT 1575#define PDMA0_QM_GLBL_CFG2_ARC_LBW_ARCACHE_OVRD_MASK 0x800076#define PDMA0_QM_GLBL_CFG2_ARC_LBW_BUSER_OVRD_SHIFT 1677#define PDMA0_QM_GLBL_CFG2_ARC_LBW_BUSER_OVRD_MASK 0x1000078 79/* PDMA0_QM_GLBL_ERR_CFG */80#define PDMA0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_SHIFT 081#define PDMA0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_MASK 0xF82#define PDMA0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_SHIFT 483#define PDMA0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_MASK 0x1F084#define PDMA0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_SHIFT 985#define PDMA0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_MASK 0x3E0086#define PDMA0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_SHIFT 1687#define PDMA0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_MASK 0xF000088#define PDMA0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_SHIFT 2089#define PDMA0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_MASK 0x1F0000090#define PDMA0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_SHIFT 2591#define PDMA0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_MASK 0x3E00000092#define PDMA0_QM_GLBL_ERR_CFG_ARB_STOP_ON_ERR_SHIFT 3193#define PDMA0_QM_GLBL_ERR_CFG_ARB_STOP_ON_ERR_MASK 0x8000000094 95/* PDMA0_QM_GLBL_ERR_CFG1 */96#define PDMA0_QM_GLBL_ERR_CFG1_CQF_ERR_MSG_EN_SHIFT 097#define PDMA0_QM_GLBL_ERR_CFG1_CQF_ERR_MSG_EN_MASK 0x198#define PDMA0_QM_GLBL_ERR_CFG1_CQF_STOP_ON_ERR_SHIFT 199#define PDMA0_QM_GLBL_ERR_CFG1_CQF_STOP_ON_ERR_MASK 0x2100#define PDMA0_QM_GLBL_ERR_CFG1_ARC_STOP_ON_ERR_SHIFT 2101#define PDMA0_QM_GLBL_ERR_CFG1_ARC_STOP_ON_ERR_MASK 0x4102 103/* PDMA0_QM_GLBL_ERR_ARC_HALT_EN */104#define PDMA0_QM_GLBL_ERR_ARC_HALT_EN_ERR_IND_SHIFT 0105#define PDMA0_QM_GLBL_ERR_ARC_HALT_EN_ERR_IND_MASK 0xFFFFFF106 107/* PDMA0_QM_GLBL_AXCACHE */108#define PDMA0_QM_GLBL_AXCACHE_HBW_AR_SHIFT 0109#define PDMA0_QM_GLBL_AXCACHE_HBW_AR_MASK 0xF110#define PDMA0_QM_GLBL_AXCACHE_HBW_AW_SHIFT 16111#define PDMA0_QM_GLBL_AXCACHE_HBW_AW_MASK 0xF0000112#define PDMA0_QM_GLBL_AXCACHE_LBW_AW_SHIFT 20113#define PDMA0_QM_GLBL_AXCACHE_LBW_AW_MASK 0xF00000114#define PDMA0_QM_GLBL_AXCACHE_LBW_AR_SHIFT 24115#define PDMA0_QM_GLBL_AXCACHE_LBW_AR_MASK 0xF000000116 117/* PDMA0_QM_GLBL_STS0 */118#define PDMA0_QM_GLBL_STS0_PQF_IDLE_SHIFT 0119#define PDMA0_QM_GLBL_STS0_PQF_IDLE_MASK 0xF120#define PDMA0_QM_GLBL_STS0_CQF_IDLE_SHIFT 4121#define PDMA0_QM_GLBL_STS0_CQF_IDLE_MASK 0x1F0122#define PDMA0_QM_GLBL_STS0_CP_IDLE_SHIFT 9123#define PDMA0_QM_GLBL_STS0_CP_IDLE_MASK 0x3E00124#define PDMA0_QM_GLBL_STS0_PQF_IS_STOP_SHIFT 16125#define PDMA0_QM_GLBL_STS0_PQF_IS_STOP_MASK 0xF0000126#define PDMA0_QM_GLBL_STS0_CQF_IS_STOP_SHIFT 20127#define PDMA0_QM_GLBL_STS0_CQF_IS_STOP_MASK 0x1F00000128#define PDMA0_QM_GLBL_STS0_CP_IS_STOP_SHIFT 25129#define PDMA0_QM_GLBL_STS0_CP_IS_STOP_MASK 0x3E000000130#define PDMA0_QM_GLBL_STS0_ARB_IS_STOP_SHIFT 31131#define PDMA0_QM_GLBL_STS0_ARB_IS_STOP_MASK 0x80000000132 133/* PDMA0_QM_GLBL_STS1 */134#define PDMA0_QM_GLBL_STS1_ARC_CQF_IDLE_SHIFT 0135#define PDMA0_QM_GLBL_STS1_ARC_CQF_IDLE_MASK 0x1136#define PDMA0_QM_GLBL_STS1_ARC_CQF_IS_STOP_SHIFT 1137#define PDMA0_QM_GLBL_STS1_ARC_CQF_IS_STOP_MASK 0x2138 139/* PDMA0_QM_GLBL_ERR_STS */140#define PDMA0_QM_GLBL_ERR_STS_PQF_RD_ERR_SHIFT 0141#define PDMA0_QM_GLBL_ERR_STS_PQF_RD_ERR_MASK 0x1142#define PDMA0_QM_GLBL_ERR_STS_CQF_RD_ERR_SHIFT 1143#define PDMA0_QM_GLBL_ERR_STS_CQF_RD_ERR_MASK 0x2144#define PDMA0_QM_GLBL_ERR_STS_CP_RD_ERR_SHIFT 2145#define PDMA0_QM_GLBL_ERR_STS_CP_RD_ERR_MASK 0x4146#define PDMA0_QM_GLBL_ERR_STS_CP_UNDEF_CMD_ERR_SHIFT 3147#define PDMA0_QM_GLBL_ERR_STS_CP_UNDEF_CMD_ERR_MASK 0x8148#define PDMA0_QM_GLBL_ERR_STS_CP_STOP_OP_SHIFT 4149#define PDMA0_QM_GLBL_ERR_STS_CP_STOP_OP_MASK 0x10150#define PDMA0_QM_GLBL_ERR_STS_CP_MSG_WR_ERR_SHIFT 5151#define PDMA0_QM_GLBL_ERR_STS_CP_MSG_WR_ERR_MASK 0x20152#define PDMA0_QM_GLBL_ERR_STS_CP_WREG_ERR_SHIFT 6153#define PDMA0_QM_GLBL_ERR_STS_CP_WREG_ERR_MASK 0x40154#define PDMA0_QM_GLBL_ERR_STS_CP_FENCE0_OVF_ERR_SHIFT 8155#define PDMA0_QM_GLBL_ERR_STS_CP_FENCE0_OVF_ERR_MASK 0x100156#define PDMA0_QM_GLBL_ERR_STS_CP_FENCE1_OVF_ERR_SHIFT 9157#define PDMA0_QM_GLBL_ERR_STS_CP_FENCE1_OVF_ERR_MASK 0x200158#define PDMA0_QM_GLBL_ERR_STS_CP_FENCE2_OVF_ERR_SHIFT 10159#define PDMA0_QM_GLBL_ERR_STS_CP_FENCE2_OVF_ERR_MASK 0x400160#define PDMA0_QM_GLBL_ERR_STS_CP_FENCE3_OVF_ERR_SHIFT 11161#define PDMA0_QM_GLBL_ERR_STS_CP_FENCE3_OVF_ERR_MASK 0x800162#define PDMA0_QM_GLBL_ERR_STS_CP_FENCE0_UDF_ERR_SHIFT 12163#define PDMA0_QM_GLBL_ERR_STS_CP_FENCE0_UDF_ERR_MASK 0x1000164#define PDMA0_QM_GLBL_ERR_STS_CP_FENCE1_UDF_ERR_SHIFT 13165#define PDMA0_QM_GLBL_ERR_STS_CP_FENCE1_UDF_ERR_MASK 0x2000166#define PDMA0_QM_GLBL_ERR_STS_CP_FENCE2_UDF_ERR_SHIFT 14167#define PDMA0_QM_GLBL_ERR_STS_CP_FENCE2_UDF_ERR_MASK 0x4000168#define PDMA0_QM_GLBL_ERR_STS_CP_FENCE3_UDF_ERR_SHIFT 15169#define PDMA0_QM_GLBL_ERR_STS_CP_FENCE3_UDF_ERR_MASK 0x8000170#define PDMA0_QM_GLBL_ERR_STS_CPDMA_UP_OVF_ERR_SHIFT 16171#define PDMA0_QM_GLBL_ERR_STS_CPDMA_UP_OVF_ERR_MASK 0x10000172#define PDMA0_QM_GLBL_ERR_STS_PQC_L2H_ERR_SHIFT 17173#define PDMA0_QM_GLBL_ERR_STS_PQC_L2H_ERR_MASK 0x20000174#define PDMA0_QM_GLBL_ERR_STS_RSVD_18_24_SHIFT 18175#define PDMA0_QM_GLBL_ERR_STS_RSVD_18_24_MASK 0x1FC0000176 177/* PDMA0_QM_GLBL_ERR_STS_4 */178#define PDMA0_QM_GLBL_ERR_STS_4_RSVD0_SHIFT 0179#define PDMA0_QM_GLBL_ERR_STS_4_RSVD0_MASK 0x1180#define PDMA0_QM_GLBL_ERR_STS_4_CQF_RD_ERR_SHIFT 1181#define PDMA0_QM_GLBL_ERR_STS_4_CQF_RD_ERR_MASK 0x2182#define PDMA0_QM_GLBL_ERR_STS_4_CP_RD_ERR_SHIFT 2183#define PDMA0_QM_GLBL_ERR_STS_4_CP_RD_ERR_MASK 0x4184#define PDMA0_QM_GLBL_ERR_STS_4_CP_UNDEF_CMD_ERR_SHIFT 3185#define PDMA0_QM_GLBL_ERR_STS_4_CP_UNDEF_CMD_ERR_MASK 0x8186#define PDMA0_QM_GLBL_ERR_STS_4_CP_STOP_OP_SHIFT 4187#define PDMA0_QM_GLBL_ERR_STS_4_CP_STOP_OP_MASK 0x10188#define PDMA0_QM_GLBL_ERR_STS_4_CP_MSG_WR_ERR_SHIFT 5189#define PDMA0_QM_GLBL_ERR_STS_4_CP_MSG_WR_ERR_MASK 0x20190#define PDMA0_QM_GLBL_ERR_STS_4_CP_WREG_ERR_SHIFT 6191#define PDMA0_QM_GLBL_ERR_STS_4_CP_WREG_ERR_MASK 0x40192#define PDMA0_QM_GLBL_ERR_STS_4_CP_FENCE0_OVF_ERR_SHIFT 8193#define PDMA0_QM_GLBL_ERR_STS_4_CP_FENCE0_OVF_ERR_MASK 0x100194#define PDMA0_QM_GLBL_ERR_STS_4_CP_FENCE1_OVF_ERR_SHIFT 9195#define PDMA0_QM_GLBL_ERR_STS_4_CP_FENCE1_OVF_ERR_MASK 0x200196#define PDMA0_QM_GLBL_ERR_STS_4_CP_FENCE2_OVF_ERR_SHIFT 10197#define PDMA0_QM_GLBL_ERR_STS_4_CP_FENCE2_OVF_ERR_MASK 0x400198#define PDMA0_QM_GLBL_ERR_STS_4_CP_FENCE3_OVF_ERR_SHIFT 11199#define PDMA0_QM_GLBL_ERR_STS_4_CP_FENCE3_OVF_ERR_MASK 0x800200#define PDMA0_QM_GLBL_ERR_STS_4_CP_FENCE0_UDF_ERR_SHIFT 12201#define PDMA0_QM_GLBL_ERR_STS_4_CP_FENCE0_UDF_ERR_MASK 0x1000202#define PDMA0_QM_GLBL_ERR_STS_4_CP_FENCE1_UDF_ERR_SHIFT 13203#define PDMA0_QM_GLBL_ERR_STS_4_CP_FENCE1_UDF_ERR_MASK 0x2000204#define PDMA0_QM_GLBL_ERR_STS_4_CP_FENCE2_UDF_ERR_SHIFT 14205#define PDMA0_QM_GLBL_ERR_STS_4_CP_FENCE2_UDF_ERR_MASK 0x4000206#define PDMA0_QM_GLBL_ERR_STS_4_CP_FENCE3_UDF_ERR_SHIFT 15207#define PDMA0_QM_GLBL_ERR_STS_4_CP_FENCE3_UDF_ERR_MASK 0x8000208#define PDMA0_QM_GLBL_ERR_STS_4_CPDMA_UP_OVF_ERR_SHIFT 16209#define PDMA0_QM_GLBL_ERR_STS_4_CPDMA_UP_OVF_ERR_MASK 0x10000210#define PDMA0_QM_GLBL_ERR_STS_4_RSVD17_SHIFT 17211#define PDMA0_QM_GLBL_ERR_STS_4_RSVD17_MASK 0x20000212#define PDMA0_QM_GLBL_ERR_STS_4_CQ_WR_IFIFO_CI_ERR_SHIFT 18213#define PDMA0_QM_GLBL_ERR_STS_4_CQ_WR_IFIFO_CI_ERR_MASK 0x40000214#define PDMA0_QM_GLBL_ERR_STS_4_CQ_WR_CTL_CI_ERR_SHIFT 19215#define PDMA0_QM_GLBL_ERR_STS_4_CQ_WR_CTL_CI_ERR_MASK 0x80000216#define PDMA0_QM_GLBL_ERR_STS_4_ARC_CQF_RD_ERR_SHIFT 20217#define PDMA0_QM_GLBL_ERR_STS_4_ARC_CQF_RD_ERR_MASK 0x100000218#define PDMA0_QM_GLBL_ERR_STS_4_ARC_CQ_WR_IFIFO_CI_ERR_SHIFT 21219#define PDMA0_QM_GLBL_ERR_STS_4_ARC_CQ_WR_IFIFO_CI_ERR_MASK 0x200000220#define PDMA0_QM_GLBL_ERR_STS_4_ARC_CQ_WR_CTL_CI_ERR_SHIFT 22221#define PDMA0_QM_GLBL_ERR_STS_4_ARC_CQ_WR_CTL_CI_ERR_MASK 0x400000222#define PDMA0_QM_GLBL_ERR_STS_4_ARC_AXI_ERR_SHIFT 23223#define PDMA0_QM_GLBL_ERR_STS_4_ARC_AXI_ERR_MASK 0x800000224#define PDMA0_QM_GLBL_ERR_STS_4_CP_SWITCH_WDT_ERR_SHIFT 24225#define PDMA0_QM_GLBL_ERR_STS_4_CP_SWITCH_WDT_ERR_MASK 0x1000000226 227/* PDMA0_QM_GLBL_ERR_MSG_EN */228#define PDMA0_QM_GLBL_ERR_MSG_EN_PQF_RD_ERR_SHIFT 0229#define PDMA0_QM_GLBL_ERR_MSG_EN_PQF_RD_ERR_MASK 0x1230#define PDMA0_QM_GLBL_ERR_MSG_EN_CQF_RD_ERR_SHIFT 1231#define PDMA0_QM_GLBL_ERR_MSG_EN_CQF_RD_ERR_MASK 0x2232#define PDMA0_QM_GLBL_ERR_MSG_EN_CP_RD_ERR_SHIFT 2233#define PDMA0_QM_GLBL_ERR_MSG_EN_CP_RD_ERR_MASK 0x4234#define PDMA0_QM_GLBL_ERR_MSG_EN_CP_UNDEF_CMD_ERR_SHIFT 3235#define PDMA0_QM_GLBL_ERR_MSG_EN_CP_UNDEF_CMD_ERR_MASK 0x8236#define PDMA0_QM_GLBL_ERR_MSG_EN_CP_STOP_OP_SHIFT 4237#define PDMA0_QM_GLBL_ERR_MSG_EN_CP_STOP_OP_MASK 0x10238#define PDMA0_QM_GLBL_ERR_MSG_EN_CP_MSG_WR_ERR_SHIFT 5239#define PDMA0_QM_GLBL_ERR_MSG_EN_CP_MSG_WR_ERR_MASK 0x20240#define PDMA0_QM_GLBL_ERR_MSG_EN_CP_WREG_ERR_SHIFT 6241#define PDMA0_QM_GLBL_ERR_MSG_EN_CP_WREG_ERR_MASK 0x40242#define PDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE0_OVF_ERR_SHIFT 8243#define PDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE0_OVF_ERR_MASK 0x100244#define PDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE1_OVF_ERR_SHIFT 9245#define PDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE1_OVF_ERR_MASK 0x200246#define PDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE2_OVF_ERR_SHIFT 10247#define PDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE2_OVF_ERR_MASK 0x400248#define PDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE3_OVF_ERR_SHIFT 11249#define PDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE3_OVF_ERR_MASK 0x800250#define PDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE0_UDF_ERR_SHIFT 12251#define PDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE0_UDF_ERR_MASK 0x1000252#define PDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE1_UDF_ERR_SHIFT 13253#define PDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE1_UDF_ERR_MASK 0x2000254#define PDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE2_UDF_ERR_SHIFT 14255#define PDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE2_UDF_ERR_MASK 0x4000256#define PDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE3_UDF_ERR_SHIFT 15257#define PDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE3_UDF_ERR_MASK 0x8000258#define PDMA0_QM_GLBL_ERR_MSG_EN_CPDMA_UP_OVF_ERR_SHIFT 16259#define PDMA0_QM_GLBL_ERR_MSG_EN_CPDMA_UP_OVF_ERR_MASK 0x10000260#define PDMA0_QM_GLBL_ERR_MSG_EN_PQC_L2H_ERR_SHIFT 17261#define PDMA0_QM_GLBL_ERR_MSG_EN_PQC_L2H_ERR_MASK 0x20000262#define PDMA0_QM_GLBL_ERR_MSG_EN_RSVD_18_24_SHIFT 18263#define PDMA0_QM_GLBL_ERR_MSG_EN_RSVD_18_24_MASK 0x1FC0000264 265/* PDMA0_QM_GLBL_ERR_MSG_EN_4 */266#define PDMA0_QM_GLBL_ERR_MSG_EN_4_RSVD0_SHIFT 0267#define PDMA0_QM_GLBL_ERR_MSG_EN_4_RSVD0_MASK 0x1268#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CQF_RD_ERR_SHIFT 1269#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CQF_RD_ERR_MASK 0x2270#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_RD_ERR_SHIFT 2271#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_RD_ERR_MASK 0x4272#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_UNDEF_CMD_ERR_SHIFT 3273#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_UNDEF_CMD_ERR_MASK 0x8274#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_STOP_OP_SHIFT 4275#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_STOP_OP_MASK 0x10276#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_MSG_WR_ERR_SHIFT 5277#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_MSG_WR_ERR_MASK 0x20278#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_WREG_ERR_SHIFT 6279#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_WREG_ERR_MASK 0x40280#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE0_OVF_ERR_SHIFT 8281#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE0_OVF_ERR_MASK 0x100282#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE1_OVF_ERR_SHIFT 9283#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE1_OVF_ERR_MASK 0x200284#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE2_OVF_ERR_SHIFT 10285#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE2_OVF_ERR_MASK 0x400286#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE3_OVF_ERR_SHIFT 11287#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE3_OVF_ERR_MASK 0x800288#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE0_UDF_ERR_SHIFT 12289#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE0_UDF_ERR_MASK 0x1000290#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE1_UDF_ERR_SHIFT 13291#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE1_UDF_ERR_MASK 0x2000292#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE2_UDF_ERR_SHIFT 14293#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE2_UDF_ERR_MASK 0x4000294#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE3_UDF_ERR_SHIFT 15295#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE3_UDF_ERR_MASK 0x8000296#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CPDMA_UP_OVF_ERR_SHIFT 16297#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CPDMA_UP_OVF_ERR_MASK 0x10000298#define PDMA0_QM_GLBL_ERR_MSG_EN_4_RSVD17_SHIFT 17299#define PDMA0_QM_GLBL_ERR_MSG_EN_4_RSVD17_MASK 0x20000300#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CQ_WR_IFIFO_CI_ERR_SHIFT 18301#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CQ_WR_IFIFO_CI_ERR_MASK 0x40000302#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CQ_WR_CTL_CI_ERR_SHIFT 19303#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CQ_WR_CTL_CI_ERR_MASK 0x80000304#define PDMA0_QM_GLBL_ERR_MSG_EN_4_ARC_CQF_RD_ERR_SHIFT 20305#define PDMA0_QM_GLBL_ERR_MSG_EN_4_ARC_CQF_RD_ERR_MASK 0x100000306#define PDMA0_QM_GLBL_ERR_MSG_EN_4_ARC_CQ_WR_IFIFO_CI_ERR_SHIFT 21307#define PDMA0_QM_GLBL_ERR_MSG_EN_4_ARC_CQ_WR_IFIFO_CI_ERR_MASK 0x200000308#define PDMA0_QM_GLBL_ERR_MSG_EN_4_ARC_CQ_WR_CTL_CI_ERR_SHIFT 22309#define PDMA0_QM_GLBL_ERR_MSG_EN_4_ARC_CQ_WR_CTL_CI_ERR_MASK 0x400000310#define PDMA0_QM_GLBL_ERR_MSG_EN_4_ARC_AXI_ERR_SHIFT 23311#define PDMA0_QM_GLBL_ERR_MSG_EN_4_ARC_AXI_ERR_MASK 0x800000312#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_SWITCH_WDT_ERR_SHIFT 24313#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_SWITCH_WDT_ERR_MASK 0x1000000314 315/* PDMA0_QM_GLBL_PROT */316#define PDMA0_QM_GLBL_PROT_PQF_SHIFT 0317#define PDMA0_QM_GLBL_PROT_PQF_MASK 0xF318#define PDMA0_QM_GLBL_PROT_CQF_SHIFT 4319#define PDMA0_QM_GLBL_PROT_CQF_MASK 0x1F0320#define PDMA0_QM_GLBL_PROT_CP_SHIFT 9321#define PDMA0_QM_GLBL_PROT_CP_MASK 0x3E00322#define PDMA0_QM_GLBL_PROT_ERR_SHIFT 14323#define PDMA0_QM_GLBL_PROT_ERR_MASK 0x4000324#define PDMA0_QM_GLBL_PROT_ARB_SHIFT 15325#define PDMA0_QM_GLBL_PROT_ARB_MASK 0x8000326#define PDMA0_QM_GLBL_PROT_PQC_SHIFT 16327#define PDMA0_QM_GLBL_PROT_PQC_MASK 0x10000328#define PDMA0_QM_GLBL_PROT_CQ_IFIFO_MSG_SHIFT 17329#define PDMA0_QM_GLBL_PROT_CQ_IFIFO_MSG_MASK 0x20000330#define PDMA0_QM_GLBL_PROT_ARC_CQ_IFIFO_MSG_SHIFT 18331#define PDMA0_QM_GLBL_PROT_ARC_CQ_IFIFO_MSG_MASK 0x40000332#define PDMA0_QM_GLBL_PROT_CQ_CTL_MSG_SHIFT 19333#define PDMA0_QM_GLBL_PROT_CQ_CTL_MSG_MASK 0x80000334#define PDMA0_QM_GLBL_PROT_ARC_CQ_CTL_MSG_SHIFT 20335#define PDMA0_QM_GLBL_PROT_ARC_CQ_CTL_MSG_MASK 0x100000336#define PDMA0_QM_GLBL_PROT_CP_WR_ARC_SHIFT 21337#define PDMA0_QM_GLBL_PROT_CP_WR_ARC_MASK 0x200000338#define PDMA0_QM_GLBL_PROT_ARC_CQF_SHIFT 22339#define PDMA0_QM_GLBL_PROT_ARC_CQF_MASK 0x400000340#define PDMA0_QM_GLBL_PROT_ARC_CORE_SHIFT 23341#define PDMA0_QM_GLBL_PROT_ARC_CORE_MASK 0x800000342 343/* PDMA0_QM_PQ_BASE_LO */344#define PDMA0_QM_PQ_BASE_LO_VAL_SHIFT 0345#define PDMA0_QM_PQ_BASE_LO_VAL_MASK 0xFFFFFFFF346 347/* PDMA0_QM_PQ_BASE_HI */348#define PDMA0_QM_PQ_BASE_HI_VAL_SHIFT 0349#define PDMA0_QM_PQ_BASE_HI_VAL_MASK 0xFFFFFFFF350 351/* PDMA0_QM_PQ_SIZE */352#define PDMA0_QM_PQ_SIZE_VAL_SHIFT 0353#define PDMA0_QM_PQ_SIZE_VAL_MASK 0x1F354 355/* PDMA0_QM_PQ_PI */356#define PDMA0_QM_PQ_PI_VAL_SHIFT 0357#define PDMA0_QM_PQ_PI_VAL_MASK 0xFFFFFFFF358 359/* PDMA0_QM_PQ_CI */360#define PDMA0_QM_PQ_CI_VAL_SHIFT 0361#define PDMA0_QM_PQ_CI_VAL_MASK 0xFFFFFFFF362 363/* PDMA0_QM_PQ_CFG0 */364#define PDMA0_QM_PQ_CFG0_FORCE_STALL_SHIFT 0365#define PDMA0_QM_PQ_CFG0_FORCE_STALL_MASK 0x1366 367/* PDMA0_QM_PQ_CFG1 */368#define PDMA0_QM_PQ_CFG1_CREDIT_LIM_SHIFT 0369#define PDMA0_QM_PQ_CFG1_CREDIT_LIM_MASK 0xFF370#define PDMA0_QM_PQ_CFG1_MAX_INFLIGHT_SHIFT 16371#define PDMA0_QM_PQ_CFG1_MAX_INFLIGHT_MASK 0xFF0000372 373/* PDMA0_QM_PQ_STS0 */374#define PDMA0_QM_PQ_STS0_CREDIT_CNT_SHIFT 0375#define PDMA0_QM_PQ_STS0_CREDIT_CNT_MASK 0xFF376#define PDMA0_QM_PQ_STS0_FREE_CNT_SHIFT 8377#define PDMA0_QM_PQ_STS0_FREE_CNT_MASK 0xFF00378#define PDMA0_QM_PQ_STS0_INFLIGHT_CNT_SHIFT 16379#define PDMA0_QM_PQ_STS0_INFLIGHT_CNT_MASK 0xFF0000380 381/* PDMA0_QM_PQ_STS1 */382#define PDMA0_QM_PQ_STS1_BUF_EMPTY_SHIFT 0383#define PDMA0_QM_PQ_STS1_BUF_EMPTY_MASK 0x1384#define PDMA0_QM_PQ_STS1_BUSY_SHIFT 1385#define PDMA0_QM_PQ_STS1_BUSY_MASK 0x2386 387/* PDMA0_QM_CQ_CFG0 */388#define PDMA0_QM_CQ_CFG0_IF_B2B_EN_SHIFT 0389#define PDMA0_QM_CQ_CFG0_IF_B2B_EN_MASK 0x1390#define PDMA0_QM_CQ_CFG0_IF_MSG_EN_SHIFT 1391#define PDMA0_QM_CQ_CFG0_IF_MSG_EN_MASK 0x2392#define PDMA0_QM_CQ_CFG0_CTL_MSG_EN_SHIFT 2393#define PDMA0_QM_CQ_CFG0_CTL_MSG_EN_MASK 0x4394 395/* PDMA0_QM_CQ_STS0 */396#define PDMA0_QM_CQ_STS0_CREDIT_CNT_SHIFT 0397#define PDMA0_QM_CQ_STS0_CREDIT_CNT_MASK 0xFF398#define PDMA0_QM_CQ_STS0_FREE_CNT_SHIFT 8399#define PDMA0_QM_CQ_STS0_FREE_CNT_MASK 0xFF00400#define PDMA0_QM_CQ_STS0_INFLIGHT_CNT_SHIFT 16401#define PDMA0_QM_CQ_STS0_INFLIGHT_CNT_MASK 0xFF0000402 403/* PDMA0_QM_CQ_CFG1 */404#define PDMA0_QM_CQ_CFG1_CREDIT_LIM_SHIFT 0405#define PDMA0_QM_CQ_CFG1_CREDIT_LIM_MASK 0xFF406#define PDMA0_QM_CQ_CFG1_MAX_INFLIGHT_SHIFT 16407#define PDMA0_QM_CQ_CFG1_MAX_INFLIGHT_MASK 0xFF0000408 409/* PDMA0_QM_CQ_STS1 */410#define PDMA0_QM_CQ_STS1_BUF_EMPTY_SHIFT 0411#define PDMA0_QM_CQ_STS1_BUF_EMPTY_MASK 0x1412#define PDMA0_QM_CQ_STS1_BUSY_SHIFT 1413#define PDMA0_QM_CQ_STS1_BUSY_MASK 0x2414 415/* PDMA0_QM_CQ_PTR_LO_0 */416#define PDMA0_QM_CQ_PTR_LO_0_VAL_SHIFT 0417#define PDMA0_QM_CQ_PTR_LO_0_VAL_MASK 0xFFFFFFFF418 419/* PDMA0_QM_CQ_PTR_HI_0 */420#define PDMA0_QM_CQ_PTR_HI_0_VAL_SHIFT 0421#define PDMA0_QM_CQ_PTR_HI_0_VAL_MASK 0xFFFFFFFF422 423/* PDMA0_QM_CQ_TSIZE_0 */424#define PDMA0_QM_CQ_TSIZE_0_VAL_SHIFT 0425#define PDMA0_QM_CQ_TSIZE_0_VAL_MASK 0xFFFFFFFF426 427/* PDMA0_QM_CQ_CTL_0 */428#define PDMA0_QM_CQ_CTL_0_UP_SHIFT 28429#define PDMA0_QM_CQ_CTL_0_UP_MASK 0xF0000000430 431/* PDMA0_QM_CQ_PTR_LO_1 */432#define PDMA0_QM_CQ_PTR_LO_1_VAL_SHIFT 0433#define PDMA0_QM_CQ_PTR_LO_1_VAL_MASK 0xFFFFFFFF434 435/* PDMA0_QM_CQ_PTR_HI_1 */436#define PDMA0_QM_CQ_PTR_HI_1_VAL_SHIFT 0437#define PDMA0_QM_CQ_PTR_HI_1_VAL_MASK 0xFFFFFFFF438 439/* PDMA0_QM_CQ_TSIZE_1 */440#define PDMA0_QM_CQ_TSIZE_1_VAL_SHIFT 0441#define PDMA0_QM_CQ_TSIZE_1_VAL_MASK 0xFFFFFFFF442 443/* PDMA0_QM_CQ_CTL_1 */444#define PDMA0_QM_CQ_CTL_1_UP_SHIFT 28445#define PDMA0_QM_CQ_CTL_1_UP_MASK 0xF0000000446 447/* PDMA0_QM_CQ_PTR_LO_2 */448#define PDMA0_QM_CQ_PTR_LO_2_VAL_SHIFT 0449#define PDMA0_QM_CQ_PTR_LO_2_VAL_MASK 0xFFFFFFFF450 451/* PDMA0_QM_CQ_PTR_HI_2 */452#define PDMA0_QM_CQ_PTR_HI_2_VAL_SHIFT 0453#define PDMA0_QM_CQ_PTR_HI_2_VAL_MASK 0xFFFFFFFF454 455/* PDMA0_QM_CQ_TSIZE_2 */456#define PDMA0_QM_CQ_TSIZE_2_VAL_SHIFT 0457#define PDMA0_QM_CQ_TSIZE_2_VAL_MASK 0xFFFFFFFF458 459/* PDMA0_QM_CQ_CTL_2 */460#define PDMA0_QM_CQ_CTL_2_UP_SHIFT 28461#define PDMA0_QM_CQ_CTL_2_UP_MASK 0xF0000000462 463/* PDMA0_QM_CQ_PTR_LO_3 */464#define PDMA0_QM_CQ_PTR_LO_3_VAL_SHIFT 0465#define PDMA0_QM_CQ_PTR_LO_3_VAL_MASK 0xFFFFFFFF466 467/* PDMA0_QM_CQ_PTR_HI_3 */468#define PDMA0_QM_CQ_PTR_HI_3_VAL_SHIFT 0469#define PDMA0_QM_CQ_PTR_HI_3_VAL_MASK 0xFFFFFFFF470 471/* PDMA0_QM_CQ_TSIZE_3 */472#define PDMA0_QM_CQ_TSIZE_3_VAL_SHIFT 0473#define PDMA0_QM_CQ_TSIZE_3_VAL_MASK 0xFFFFFFFF474 475/* PDMA0_QM_CQ_CTL_3 */476#define PDMA0_QM_CQ_CTL_3_UP_SHIFT 28477#define PDMA0_QM_CQ_CTL_3_UP_MASK 0xF0000000478 479/* PDMA0_QM_CQ_PTR_LO_4 */480#define PDMA0_QM_CQ_PTR_LO_4_VAL_SHIFT 0481#define PDMA0_QM_CQ_PTR_LO_4_VAL_MASK 0xFFFFFFFF482 483/* PDMA0_QM_CQ_PTR_HI_4 */484#define PDMA0_QM_CQ_PTR_HI_4_VAL_SHIFT 0485#define PDMA0_QM_CQ_PTR_HI_4_VAL_MASK 0xFFFFFFFF486 487/* PDMA0_QM_CQ_TSIZE_4 */488#define PDMA0_QM_CQ_TSIZE_4_VAL_SHIFT 0489#define PDMA0_QM_CQ_TSIZE_4_VAL_MASK 0xFFFFFFFF490 491/* PDMA0_QM_CQ_CTL_4 */492#define PDMA0_QM_CQ_CTL_4_UP_SHIFT 28493#define PDMA0_QM_CQ_CTL_4_UP_MASK 0xF0000000494 495/* PDMA0_QM_CQ_TSIZE_STS */496#define PDMA0_QM_CQ_TSIZE_STS_VAL_SHIFT 0497#define PDMA0_QM_CQ_TSIZE_STS_VAL_MASK 0xFFFFFFFF498 499/* PDMA0_QM_CQ_PTR_LO_STS */500#define PDMA0_QM_CQ_PTR_LO_STS_VAL_SHIFT 0501#define PDMA0_QM_CQ_PTR_LO_STS_VAL_MASK 0xFFFFFFFF502 503/* PDMA0_QM_CQ_PTR_HI_STS */504#define PDMA0_QM_CQ_PTR_HI_STS_VAL_SHIFT 0505#define PDMA0_QM_CQ_PTR_HI_STS_VAL_MASK 0xFFFFFFFF506 507/* PDMA0_QM_CQ_IFIFO_STS */508#define PDMA0_QM_CQ_IFIFO_STS_CNT_SHIFT 0509#define PDMA0_QM_CQ_IFIFO_STS_CNT_MASK 0x7510#define PDMA0_QM_CQ_IFIFO_STS_RDY_SHIFT 4511#define PDMA0_QM_CQ_IFIFO_STS_RDY_MASK 0x10512#define PDMA0_QM_CQ_IFIFO_STS_CTL_STALL_SHIFT 8513#define PDMA0_QM_CQ_IFIFO_STS_CTL_STALL_MASK 0x100514 515/* PDMA0_QM_CP_MSG_BASE0_ADDR_LO */516#define PDMA0_QM_CP_MSG_BASE0_ADDR_LO_VAL_SHIFT 0517#define PDMA0_QM_CP_MSG_BASE0_ADDR_LO_VAL_MASK 0xFFFFFFFF518 519/* PDMA0_QM_CP_MSG_BASE0_ADDR_HI */520#define PDMA0_QM_CP_MSG_BASE0_ADDR_HI_VAL_SHIFT 0521#define PDMA0_QM_CP_MSG_BASE0_ADDR_HI_VAL_MASK 0xFFFFFFFF522 523/* PDMA0_QM_CP_MSG_BASE1_ADDR_LO */524#define PDMA0_QM_CP_MSG_BASE1_ADDR_LO_VAL_SHIFT 0525#define PDMA0_QM_CP_MSG_BASE1_ADDR_LO_VAL_MASK 0xFFFFFFFF526 527/* PDMA0_QM_CP_MSG_BASE1_ADDR_HI */528#define PDMA0_QM_CP_MSG_BASE1_ADDR_HI_VAL_SHIFT 0529#define PDMA0_QM_CP_MSG_BASE1_ADDR_HI_VAL_MASK 0xFFFFFFFF530 531/* PDMA0_QM_CP_MSG_BASE2_ADDR_LO */532#define PDMA0_QM_CP_MSG_BASE2_ADDR_LO_VAL_SHIFT 0533#define PDMA0_QM_CP_MSG_BASE2_ADDR_LO_VAL_MASK 0xFFFFFFFF534 535/* PDMA0_QM_CP_MSG_BASE2_ADDR_HI */536#define PDMA0_QM_CP_MSG_BASE2_ADDR_HI_VAL_SHIFT 0537#define PDMA0_QM_CP_MSG_BASE2_ADDR_HI_VAL_MASK 0xFFFFFFFF538 539/* PDMA0_QM_CP_MSG_BASE3_ADDR_LO */540#define PDMA0_QM_CP_MSG_BASE3_ADDR_LO_VAL_SHIFT 0541#define PDMA0_QM_CP_MSG_BASE3_ADDR_LO_VAL_MASK 0xFFFFFFFF542 543/* PDMA0_QM_CP_MSG_BASE3_ADDR_HI */544#define PDMA0_QM_CP_MSG_BASE3_ADDR_HI_VAL_SHIFT 0545#define PDMA0_QM_CP_MSG_BASE3_ADDR_HI_VAL_MASK 0xFFFFFFFF546 547/* PDMA0_QM_CP_FENCE0_RDATA */548#define PDMA0_QM_CP_FENCE0_RDATA_INC_VAL_SHIFT 0549#define PDMA0_QM_CP_FENCE0_RDATA_INC_VAL_MASK 0xF550 551/* PDMA0_QM_CP_FENCE1_RDATA */552#define PDMA0_QM_CP_FENCE1_RDATA_INC_VAL_SHIFT 0553#define PDMA0_QM_CP_FENCE1_RDATA_INC_VAL_MASK 0xF554 555/* PDMA0_QM_CP_FENCE2_RDATA */556#define PDMA0_QM_CP_FENCE2_RDATA_INC_VAL_SHIFT 0557#define PDMA0_QM_CP_FENCE2_RDATA_INC_VAL_MASK 0xF558 559/* PDMA0_QM_CP_FENCE3_RDATA */560#define PDMA0_QM_CP_FENCE3_RDATA_INC_VAL_SHIFT 0561#define PDMA0_QM_CP_FENCE3_RDATA_INC_VAL_MASK 0xF562 563/* PDMA0_QM_CP_FENCE0_CNT */564#define PDMA0_QM_CP_FENCE0_CNT_VAL_SHIFT 0565#define PDMA0_QM_CP_FENCE0_CNT_VAL_MASK 0x3FFF566 567/* PDMA0_QM_CP_FENCE1_CNT */568#define PDMA0_QM_CP_FENCE1_CNT_VAL_SHIFT 0569#define PDMA0_QM_CP_FENCE1_CNT_VAL_MASK 0x3FFF570 571/* PDMA0_QM_CP_FENCE2_CNT */572#define PDMA0_QM_CP_FENCE2_CNT_VAL_SHIFT 0573#define PDMA0_QM_CP_FENCE2_CNT_VAL_MASK 0x3FFF574 575/* PDMA0_QM_CP_FENCE3_CNT */576#define PDMA0_QM_CP_FENCE3_CNT_VAL_SHIFT 0577#define PDMA0_QM_CP_FENCE3_CNT_VAL_MASK 0x3FFF578 579/* PDMA0_QM_CP_BARRIER_CFG */580#define PDMA0_QM_CP_BARRIER_CFG_EBGUARD_SHIFT 0581#define PDMA0_QM_CP_BARRIER_CFG_EBGUARD_MASK 0xFFF582#define PDMA0_QM_CP_BARRIER_CFG_RBGUARD_SHIFT 16583#define PDMA0_QM_CP_BARRIER_CFG_RBGUARD_MASK 0xF0000584 585/* PDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET */586#define PDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_VAL_SHIFT 0587#define PDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_VAL_MASK 0xFFFF588 589/* PDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET */590#define PDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_VAL_SHIFT 0591#define PDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_VAL_MASK 0xFFFF592 593/* PDMA0_QM_CP_LDMA_TSIZE_OFFSET */594#define PDMA0_QM_CP_LDMA_TSIZE_OFFSET_VAL_SHIFT 0595#define PDMA0_QM_CP_LDMA_TSIZE_OFFSET_VAL_MASK 0xFFFF596 597/* PDMA0_QM_CP_CQ_PTR_LO_OFFSET_0 */598#define PDMA0_QM_CP_CQ_PTR_LO_OFFSET_0_VAL_SHIFT 0599#define PDMA0_QM_CP_CQ_PTR_LO_OFFSET_0_VAL_MASK 0xFFFF600 601/* PDMA0_QM_CP_CQ_PTR_LO_OFFSET_1 */602#define PDMA0_QM_CP_CQ_PTR_LO_OFFSET_1_VAL_SHIFT 0603#define PDMA0_QM_CP_CQ_PTR_LO_OFFSET_1_VAL_MASK 0xFFFF604 605/* PDMA0_QM_CP_CQ_PTR_LO_OFFSET_2 */606#define PDMA0_QM_CP_CQ_PTR_LO_OFFSET_2_VAL_SHIFT 0607#define PDMA0_QM_CP_CQ_PTR_LO_OFFSET_2_VAL_MASK 0xFFFF608 609/* PDMA0_QM_CP_CQ_PTR_LO_OFFSET_3 */610#define PDMA0_QM_CP_CQ_PTR_LO_OFFSET_3_VAL_SHIFT 0611#define PDMA0_QM_CP_CQ_PTR_LO_OFFSET_3_VAL_MASK 0xFFFF612 613/* PDMA0_QM_CP_CQ_PTR_LO_OFFSET_4 */614#define PDMA0_QM_CP_CQ_PTR_LO_OFFSET_4_VAL_SHIFT 0615#define PDMA0_QM_CP_CQ_PTR_LO_OFFSET_4_VAL_MASK 0xFFFF616 617/* PDMA0_QM_CP_STS */618#define PDMA0_QM_CP_STS_MSG_INFLIGHT_CNT_SHIFT 0619#define PDMA0_QM_CP_STS_MSG_INFLIGHT_CNT_MASK 0xFF620#define PDMA0_QM_CP_STS_ERDY_SHIFT 8621#define PDMA0_QM_CP_STS_ERDY_MASK 0x100622#define PDMA0_QM_CP_STS_SWITCH_EN_SHIFT 9623#define PDMA0_QM_CP_STS_SWITCH_EN_MASK 0x200624#define PDMA0_QM_CP_STS_MRDY_SHIFT 10625#define PDMA0_QM_CP_STS_MRDY_MASK 0x400626#define PDMA0_QM_CP_STS_SW_STOP_SHIFT 11627#define PDMA0_QM_CP_STS_SW_STOP_MASK 0x800628#define PDMA0_QM_CP_STS_FENCE_ID_SHIFT 12629#define PDMA0_QM_CP_STS_FENCE_ID_MASK 0x3000630#define PDMA0_QM_CP_STS_FENCE_IN_PROGRESS_SHIFT 14631#define PDMA0_QM_CP_STS_FENCE_IN_PROGRESS_MASK 0x4000632#define PDMA0_QM_CP_STS_FENCE_TARGET_SHIFT 16633#define PDMA0_QM_CP_STS_FENCE_TARGET_MASK 0x3FFF0000634#define PDMA0_QM_CP_STS_CUR_CQ_SHIFT 30635#define PDMA0_QM_CP_STS_CUR_CQ_MASK 0x40000000636 637/* PDMA0_QM_CP_CURRENT_INST_LO */638#define PDMA0_QM_CP_CURRENT_INST_LO_VAL_SHIFT 0639#define PDMA0_QM_CP_CURRENT_INST_LO_VAL_MASK 0xFFFFFFFF640 641/* PDMA0_QM_CP_CURRENT_INST_HI */642#define PDMA0_QM_CP_CURRENT_INST_HI_VAL_SHIFT 0643#define PDMA0_QM_CP_CURRENT_INST_HI_VAL_MASK 0xFFFFFFFF644 645/* PDMA0_QM_CP_PRED */646#define PDMA0_QM_CP_PRED_VAL_SHIFT 0647#define PDMA0_QM_CP_PRED_VAL_MASK 0xFFFFFFFF648 649/* PDMA0_QM_CP_PRED_UPEN */650#define PDMA0_QM_CP_PRED_UPEN_VAL_SHIFT 0651#define PDMA0_QM_CP_PRED_UPEN_VAL_MASK 0xFFFFFFFF652 653/* PDMA0_QM_CP_DBG_0 */654#define PDMA0_QM_CP_DBG_0_CS_SHIFT 0655#define PDMA0_QM_CP_DBG_0_CS_MASK 0x1F656#define PDMA0_QM_CP_DBG_0_EB_CNT_NOT_ZERO_SHIFT 5657#define PDMA0_QM_CP_DBG_0_EB_CNT_NOT_ZERO_MASK 0x20658#define PDMA0_QM_CP_DBG_0_BULK_CNT_NOT_ZERO_SHIFT 6659#define PDMA0_QM_CP_DBG_0_BULK_CNT_NOT_ZERO_MASK 0x40660#define PDMA0_QM_CP_DBG_0_MREB_STALL_SHIFT 7661#define PDMA0_QM_CP_DBG_0_MREB_STALL_MASK 0x80662#define PDMA0_QM_CP_DBG_0_STALL_SHIFT 8663#define PDMA0_QM_CP_DBG_0_STALL_MASK 0x100664 665/* PDMA0_QM_CP_CPDMA_UP_CRED */666#define PDMA0_QM_CP_CPDMA_UP_CRED_TH_SHIFT 0667#define PDMA0_QM_CP_CPDMA_UP_CRED_TH_MASK 0x3668#define PDMA0_QM_CP_CPDMA_UP_CRED_VAL_SHIFT 8669#define PDMA0_QM_CP_CPDMA_UP_CRED_VAL_MASK 0x300670 671/* PDMA0_QM_CP_IN_DATA_LO */672#define PDMA0_QM_CP_IN_DATA_LO_VAL_SHIFT 0673#define PDMA0_QM_CP_IN_DATA_LO_VAL_MASK 0xFFFFFFFF674 675/* PDMA0_QM_CP_IN_DATA_HI */676#define PDMA0_QM_CP_IN_DATA_HI_VAL_SHIFT 0677#define PDMA0_QM_CP_IN_DATA_HI_VAL_MASK 0xFFFFFFFF678 679/* PDMA0_QM_PQC_HBW_BASE_LO */680#define PDMA0_QM_PQC_HBW_BASE_LO_VAL_SHIFT 0681#define PDMA0_QM_PQC_HBW_BASE_LO_VAL_MASK 0xFFFFFFFF682 683/* PDMA0_QM_PQC_HBW_BASE_HI */684#define PDMA0_QM_PQC_HBW_BASE_HI_VAL_SHIFT 0685#define PDMA0_QM_PQC_HBW_BASE_HI_VAL_MASK 0xFFFFFFFF686 687/* PDMA0_QM_PQC_SIZE */688#define PDMA0_QM_PQC_SIZE_VAL_SHIFT 0689#define PDMA0_QM_PQC_SIZE_VAL_MASK 0xFFFFFFFF690 691/* PDMA0_QM_PQC_PI */692#define PDMA0_QM_PQC_PI_VAL_SHIFT 0693#define PDMA0_QM_PQC_PI_VAL_MASK 0xFFFFFFFF694 695/* PDMA0_QM_PQC_LBW_WDATA */696#define PDMA0_QM_PQC_LBW_WDATA_VAL_SHIFT 0697#define PDMA0_QM_PQC_LBW_WDATA_VAL_MASK 0xFFFFFFFF698 699/* PDMA0_QM_PQC_LBW_BASE_LO */700#define PDMA0_QM_PQC_LBW_BASE_LO_VAL_SHIFT 0701#define PDMA0_QM_PQC_LBW_BASE_LO_VAL_MASK 0xFFFFFFFF702 703/* PDMA0_QM_PQC_LBW_BASE_HI */704#define PDMA0_QM_PQC_LBW_BASE_HI_VAL_SHIFT 0705#define PDMA0_QM_PQC_LBW_BASE_HI_VAL_MASK 0xFFFFFFFF706 707/* PDMA0_QM_PQC_CFG */708#define PDMA0_QM_PQC_CFG_EN_SHIFT 0709#define PDMA0_QM_PQC_CFG_EN_MASK 0x1710#define PDMA0_QM_PQC_CFG_DIRECT_SHIFT 4711#define PDMA0_QM_PQC_CFG_DIRECT_MASK 0x10712 713/* PDMA0_QM_PQC_SECURE_PUSH_IND */714#define PDMA0_QM_PQC_SECURE_PUSH_IND_CP_NUM_SHIFT 0715#define PDMA0_QM_PQC_SECURE_PUSH_IND_CP_NUM_MASK 0x3716 717/* PDMA0_QM_ARB_MASK */718#define PDMA0_QM_ARB_MASK_VAL_SHIFT 0719#define PDMA0_QM_ARB_MASK_VAL_MASK 0xF720 721/* PDMA0_QM_ARB_CFG_0 */722#define PDMA0_QM_ARB_CFG_0_PRIO_TYPE_SHIFT 0723#define PDMA0_QM_ARB_CFG_0_PRIO_TYPE_MASK 0x1724#define PDMA0_QM_ARB_CFG_0_IS_MASTER_SHIFT 4725#define PDMA0_QM_ARB_CFG_0_IS_MASTER_MASK 0x10726#define PDMA0_QM_ARB_CFG_0_EN_SHIFT 8727#define PDMA0_QM_ARB_CFG_0_EN_MASK 0x100728#define PDMA0_QM_ARB_CFG_0_MST_MSG_NOSTALL_SHIFT 9729#define PDMA0_QM_ARB_CFG_0_MST_MSG_NOSTALL_MASK 0x200730 731/* PDMA0_QM_ARB_CHOICE_Q_PUSH */732#define PDMA0_QM_ARB_CHOICE_Q_PUSH_VAL_SHIFT 0733#define PDMA0_QM_ARB_CHOICE_Q_PUSH_VAL_MASK 0x3734 735/* PDMA0_QM_ARB_WRR_WEIGHT */736#define PDMA0_QM_ARB_WRR_WEIGHT_VAL_SHIFT 0737#define PDMA0_QM_ARB_WRR_WEIGHT_VAL_MASK 0xFF738 739/* PDMA0_QM_ARB_CFG_1 */740#define PDMA0_QM_ARB_CFG_1_CLR_SHIFT 0741#define PDMA0_QM_ARB_CFG_1_CLR_MASK 0x1742 743/* PDMA0_QM_ARB_MST_AVAIL_CRED */744#define PDMA0_QM_ARB_MST_AVAIL_CRED_VAL_SHIFT 0745#define PDMA0_QM_ARB_MST_AVAIL_CRED_VAL_MASK 0x7F746 747/* PDMA0_QM_ARB_MST_CRED_INC */748#define PDMA0_QM_ARB_MST_CRED_INC_VAL_SHIFT 0749#define PDMA0_QM_ARB_MST_CRED_INC_VAL_MASK 0xFFFFFFFF750 751/* PDMA0_QM_ARB_MST_CHOICE_PUSH_OFST */752#define PDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_VAL_SHIFT 0753#define PDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_VAL_MASK 0xFFFFFFFF754 755/* PDMA0_QM_ARB_SLV_MASTER_INC_CRED_OFST */756#define PDMA0_QM_ARB_SLV_MASTER_INC_CRED_OFST_VAL_SHIFT 0757#define PDMA0_QM_ARB_SLV_MASTER_INC_CRED_OFST_VAL_MASK 0xFFFFFFFF758 759/* PDMA0_QM_ARB_MST_SLAVE_EN */760#define PDMA0_QM_ARB_MST_SLAVE_EN_VAL_SHIFT 0761#define PDMA0_QM_ARB_MST_SLAVE_EN_VAL_MASK 0xFFFFFFFF762 763/* PDMA0_QM_ARB_MST_SLAVE_EN_1 */764#define PDMA0_QM_ARB_MST_SLAVE_EN_1_VAL_SHIFT 0765#define PDMA0_QM_ARB_MST_SLAVE_EN_1_VAL_MASK 0xFFFFFFFF766 767/* PDMA0_QM_ARB_SLV_CHOICE_WDT */768#define PDMA0_QM_ARB_SLV_CHOICE_WDT_VAL_SHIFT 0769#define PDMA0_QM_ARB_SLV_CHOICE_WDT_VAL_MASK 0xFFFFFFFF770 771/* PDMA0_QM_ARB_SLV_ID */772#define PDMA0_QM_ARB_SLV_ID_VAL_SHIFT 0773#define PDMA0_QM_ARB_SLV_ID_VAL_MASK 0x7F774 775/* PDMA0_QM_ARB_MST_QUIET_PER */776#define PDMA0_QM_ARB_MST_QUIET_PER_VAL_SHIFT 0777#define PDMA0_QM_ARB_MST_QUIET_PER_VAL_MASK 0xFFFFFFFF778 779/* PDMA0_QM_ARB_MSG_MAX_INFLIGHT */780#define PDMA0_QM_ARB_MSG_MAX_INFLIGHT_VAL_SHIFT 0781#define PDMA0_QM_ARB_MSG_MAX_INFLIGHT_VAL_MASK 0x3F782 783/* PDMA0_QM_ARB_BASE_LO */784#define PDMA0_QM_ARB_BASE_LO_VAL_SHIFT 0785#define PDMA0_QM_ARB_BASE_LO_VAL_MASK 0xFFFFFFFF786 787/* PDMA0_QM_ARB_BASE_HI */788#define PDMA0_QM_ARB_BASE_HI_VAL_SHIFT 0789#define PDMA0_QM_ARB_BASE_HI_VAL_MASK 0xFFFFFFFF790 791/* PDMA0_QM_ARB_STATE_STS */792#define PDMA0_QM_ARB_STATE_STS_VAL_SHIFT 0793#define PDMA0_QM_ARB_STATE_STS_VAL_MASK 0xFFFFFFFF794 795/* PDMA0_QM_ARB_CHOICE_FULLNESS_STS */796#define PDMA0_QM_ARB_CHOICE_FULLNESS_STS_VAL_SHIFT 0797#define PDMA0_QM_ARB_CHOICE_FULLNESS_STS_VAL_MASK 0x7F798 799/* PDMA0_QM_ARB_MSG_STS */800#define PDMA0_QM_ARB_MSG_STS_FULL_SHIFT 0801#define PDMA0_QM_ARB_MSG_STS_FULL_MASK 0x1802#define PDMA0_QM_ARB_MSG_STS_NO_INFLIGHT_SHIFT 1803#define PDMA0_QM_ARB_MSG_STS_NO_INFLIGHT_MASK 0x2804 805/* PDMA0_QM_ARB_SLV_CHOICE_Q_HEAD */806#define PDMA0_QM_ARB_SLV_CHOICE_Q_HEAD_VAL_SHIFT 0807#define PDMA0_QM_ARB_SLV_CHOICE_Q_HEAD_VAL_MASK 0x3808 809/* PDMA0_QM_ARB_ERR_CAUSE */810#define PDMA0_QM_ARB_ERR_CAUSE_CHOICE_OVF_SHIFT 0811#define PDMA0_QM_ARB_ERR_CAUSE_CHOICE_OVF_MASK 0x1812#define PDMA0_QM_ARB_ERR_CAUSE_CHOICE_WDT_SHIFT 1813#define PDMA0_QM_ARB_ERR_CAUSE_CHOICE_WDT_MASK 0x2814#define PDMA0_QM_ARB_ERR_CAUSE_AXI_LBW_ERR_SHIFT 2815#define PDMA0_QM_ARB_ERR_CAUSE_AXI_LBW_ERR_MASK 0x4816 817/* PDMA0_QM_ARB_ERR_MSG_EN */818#define PDMA0_QM_ARB_ERR_MSG_EN_CHOICE_OVF_SHIFT 0819#define PDMA0_QM_ARB_ERR_MSG_EN_CHOICE_OVF_MASK 0x1820#define PDMA0_QM_ARB_ERR_MSG_EN_CHOICE_WDT_SHIFT 1821#define PDMA0_QM_ARB_ERR_MSG_EN_CHOICE_WDT_MASK 0x2822#define PDMA0_QM_ARB_ERR_MSG_EN_AXI_LBW_ERR_SHIFT 2823#define PDMA0_QM_ARB_ERR_MSG_EN_AXI_LBW_ERR_MASK 0x4824 825/* PDMA0_QM_ARB_ERR_STS_DRP */826#define PDMA0_QM_ARB_ERR_STS_DRP_VAL_SHIFT 0827#define PDMA0_QM_ARB_ERR_STS_DRP_VAL_MASK 0x3828 829/* PDMA0_QM_ARB_MST_CRED_STS */830#define PDMA0_QM_ARB_MST_CRED_STS_VAL_SHIFT 0831#define PDMA0_QM_ARB_MST_CRED_STS_VAL_MASK 0x7F832#define PDMA0_QM_ARB_MST_CRED_STS_IDX_SHIFT 24833#define PDMA0_QM_ARB_MST_CRED_STS_IDX_MASK 0x1F000000834 835/* PDMA0_QM_ARB_MST_CRED_STS_1 */836#define PDMA0_QM_ARB_MST_CRED_STS_1_VAL_SHIFT 0837#define PDMA0_QM_ARB_MST_CRED_STS_1_VAL_MASK 0x7F838#define PDMA0_QM_ARB_MST_CRED_STS_1_IDX_SHIFT 24839#define PDMA0_QM_ARB_MST_CRED_STS_1_IDX_MASK 0x1F000000840 841/* PDMA0_QM_CSMR_STRICT_PRIO_CFG */842#define PDMA0_QM_CSMR_STRICT_PRIO_CFG_ARB_TYPE_SHIFT 0843#define PDMA0_QM_CSMR_STRICT_PRIO_CFG_ARB_TYPE_MASK 0x1844#define PDMA0_QM_CSMR_STRICT_PRIO_CFG_PER_ENTRY_SHIFT 4845#define PDMA0_QM_CSMR_STRICT_PRIO_CFG_PER_ENTRY_MASK 0x10846 847/* PDMA0_QM_ARC_CQ_CFG0 */848#define PDMA0_QM_ARC_CQ_CFG0_IF_B2B_EN_SHIFT 0849#define PDMA0_QM_ARC_CQ_CFG0_IF_B2B_EN_MASK 0x1850#define PDMA0_QM_ARC_CQ_CFG0_IF_MSG_EN_SHIFT 1851#define PDMA0_QM_ARC_CQ_CFG0_IF_MSG_EN_MASK 0x2852#define PDMA0_QM_ARC_CQ_CFG0_CTL_MSG_EN_SHIFT 2853#define PDMA0_QM_ARC_CQ_CFG0_CTL_MSG_EN_MASK 0x4854 855/* PDMA0_QM_ARC_CQ_CFG1 */856#define PDMA0_QM_ARC_CQ_CFG1_CREDIT_LIM_SHIFT 0857#define PDMA0_QM_ARC_CQ_CFG1_CREDIT_LIM_MASK 0xFF858#define PDMA0_QM_ARC_CQ_CFG1_MAX_INFLIGHT_SHIFT 16859#define PDMA0_QM_ARC_CQ_CFG1_MAX_INFLIGHT_MASK 0xFF0000860 861/* PDMA0_QM_ARC_CQ_PTR_LO */862#define PDMA0_QM_ARC_CQ_PTR_LO_VAL_SHIFT 0863#define PDMA0_QM_ARC_CQ_PTR_LO_VAL_MASK 0xFFFFFFFF864 865/* PDMA0_QM_ARC_CQ_PTR_HI */866#define PDMA0_QM_ARC_CQ_PTR_HI_VAL_SHIFT 0867#define PDMA0_QM_ARC_CQ_PTR_HI_VAL_MASK 0xFFFFFFFF868 869/* PDMA0_QM_ARC_CQ_TSIZE */870#define PDMA0_QM_ARC_CQ_TSIZE_VAL_SHIFT 0871#define PDMA0_QM_ARC_CQ_TSIZE_VAL_MASK 0xFFFFFFFF872 873/* PDMA0_QM_ARC_CQ_CTL */874#define PDMA0_QM_ARC_CQ_CTL_UP_SHIFT 28875#define PDMA0_QM_ARC_CQ_CTL_UP_MASK 0xF0000000876 877/* PDMA0_QM_ARC_CQ_IFIFO_STS */878#define PDMA0_QM_ARC_CQ_IFIFO_STS_CNT_SHIFT 0879#define PDMA0_QM_ARC_CQ_IFIFO_STS_CNT_MASK 0x7880#define PDMA0_QM_ARC_CQ_IFIFO_STS_RDY_SHIFT 4881#define PDMA0_QM_ARC_CQ_IFIFO_STS_RDY_MASK 0x10882#define PDMA0_QM_ARC_CQ_IFIFO_STS_CTL_STALL_SHIFT 8883#define PDMA0_QM_ARC_CQ_IFIFO_STS_CTL_STALL_MASK 0x100884 885/* PDMA0_QM_ARC_CQ_STS0 */886#define PDMA0_QM_ARC_CQ_STS0_CREDIT_CNT_SHIFT 0887#define PDMA0_QM_ARC_CQ_STS0_CREDIT_CNT_MASK 0xFF888#define PDMA0_QM_ARC_CQ_STS0_FREE_CNT_SHIFT 8889#define PDMA0_QM_ARC_CQ_STS0_FREE_CNT_MASK 0xFF00890#define PDMA0_QM_ARC_CQ_STS0_INFLIGHT_CNT_SHIFT 16891#define PDMA0_QM_ARC_CQ_STS0_INFLIGHT_CNT_MASK 0xFF0000892 893/* PDMA0_QM_ARC_CQ_STS1 */894#define PDMA0_QM_ARC_CQ_STS1_BUF_EMPTY_SHIFT 0895#define PDMA0_QM_ARC_CQ_STS1_BUF_EMPTY_MASK 0x1896#define PDMA0_QM_ARC_CQ_STS1_BUSY_SHIFT 1897#define PDMA0_QM_ARC_CQ_STS1_BUSY_MASK 0x2898 899/* PDMA0_QM_ARC_CQ_TSIZE_STS */900#define PDMA0_QM_ARC_CQ_TSIZE_STS_VAL_SHIFT 0901#define PDMA0_QM_ARC_CQ_TSIZE_STS_VAL_MASK 0xFFFFFFFF902 903/* PDMA0_QM_ARC_CQ_PTR_LO_STS */904#define PDMA0_QM_ARC_CQ_PTR_LO_STS_VAL_SHIFT 0905#define PDMA0_QM_ARC_CQ_PTR_LO_STS_VAL_MASK 0xFFFFFFFF906 907/* PDMA0_QM_ARC_CQ_PTR_HI_STS */908#define PDMA0_QM_ARC_CQ_PTR_HI_STS_VAL_SHIFT 0909#define PDMA0_QM_ARC_CQ_PTR_HI_STS_VAL_MASK 0xFFFFFFFF910 911/* PDMA0_QM_CP_WR_ARC_ADDR_HI */912#define PDMA0_QM_CP_WR_ARC_ADDR_HI_VAL_SHIFT 0913#define PDMA0_QM_CP_WR_ARC_ADDR_HI_VAL_MASK 0xFFFFFFFF914 915/* PDMA0_QM_CP_WR_ARC_ADDR_LO */916#define PDMA0_QM_CP_WR_ARC_ADDR_LO_VAL_SHIFT 0917#define PDMA0_QM_CP_WR_ARC_ADDR_LO_VAL_MASK 0xFFFFFFFF918 919/* PDMA0_QM_ARC_CQ_IFIFO_MSG_BASE_HI */920#define PDMA0_QM_ARC_CQ_IFIFO_MSG_BASE_HI_VAL_SHIFT 0921#define PDMA0_QM_ARC_CQ_IFIFO_MSG_BASE_HI_VAL_MASK 0xFFFFFFFF922 923/* PDMA0_QM_ARC_CQ_IFIFO_MSG_BASE_LO */924#define PDMA0_QM_ARC_CQ_IFIFO_MSG_BASE_LO_VAL_SHIFT 0925#define PDMA0_QM_ARC_CQ_IFIFO_MSG_BASE_LO_VAL_MASK 0xFFFFFFFF926 927/* PDMA0_QM_ARC_CQ_CTL_MSG_BASE_HI */928#define PDMA0_QM_ARC_CQ_CTL_MSG_BASE_HI_VAL_SHIFT 0929#define PDMA0_QM_ARC_CQ_CTL_MSG_BASE_HI_VAL_MASK 0xFFFFFFFF930 931/* PDMA0_QM_ARC_CQ_CTL_MSG_BASE_LO */932#define PDMA0_QM_ARC_CQ_CTL_MSG_BASE_LO_VAL_SHIFT 0933#define PDMA0_QM_ARC_CQ_CTL_MSG_BASE_LO_VAL_MASK 0xFFFFFFFF934 935/* PDMA0_QM_CQ_IFIFO_MSG_BASE_HI */936#define PDMA0_QM_CQ_IFIFO_MSG_BASE_HI_VAL_SHIFT 0937#define PDMA0_QM_CQ_IFIFO_MSG_BASE_HI_VAL_MASK 0xFFFFFFFF938 939/* PDMA0_QM_CQ_IFIFO_MSG_BASE_LO */940#define PDMA0_QM_CQ_IFIFO_MSG_BASE_LO_VAL_SHIFT 0941#define PDMA0_QM_CQ_IFIFO_MSG_BASE_LO_VAL_MASK 0xFFFFFFFF942 943/* PDMA0_QM_CQ_CTL_MSG_BASE_HI */944#define PDMA0_QM_CQ_CTL_MSG_BASE_HI_VAL_SHIFT 0945#define PDMA0_QM_CQ_CTL_MSG_BASE_HI_VAL_MASK 0xFFFFFFFF946 947/* PDMA0_QM_CQ_CTL_MSG_BASE_LO */948#define PDMA0_QM_CQ_CTL_MSG_BASE_LO_VAL_SHIFT 0949#define PDMA0_QM_CQ_CTL_MSG_BASE_LO_VAL_MASK 0xFFFFFFFF950 951/* PDMA0_QM_ADDR_OVRD */952#define PDMA0_QM_ADDR_OVRD_IDX_SHIFT 0953#define PDMA0_QM_ADDR_OVRD_IDX_MASK 0xFF954 955/* PDMA0_QM_CQ_IFIFO_CI */956#define PDMA0_QM_CQ_IFIFO_CI_VAL_SHIFT 0957#define PDMA0_QM_CQ_IFIFO_CI_VAL_MASK 0xFFFFFFFF958 959/* PDMA0_QM_ARC_CQ_IFIFO_CI */960#define PDMA0_QM_ARC_CQ_IFIFO_CI_VAL_SHIFT 0961#define PDMA0_QM_ARC_CQ_IFIFO_CI_VAL_MASK 0xFFFFFFFF962 963/* PDMA0_QM_CQ_CTL_CI */964#define PDMA0_QM_CQ_CTL_CI_VAL_SHIFT 0965#define PDMA0_QM_CQ_CTL_CI_VAL_MASK 0xFFFFFFFF966 967/* PDMA0_QM_ARC_CQ_CTL_CI */968#define PDMA0_QM_ARC_CQ_CTL_CI_VAL_SHIFT 0969#define PDMA0_QM_ARC_CQ_CTL_CI_VAL_MASK 0xFFFFFFFF970 971/* PDMA0_QM_CP_CFG */972#define PDMA0_QM_CP_CFG_SWITCH_EN_SHIFT 0973#define PDMA0_QM_CP_CFG_SWITCH_EN_MASK 0x1974#define PDMA0_QM_CP_CFG_SWITCH_WD_EN_SHIFT 1975#define PDMA0_QM_CP_CFG_SWITCH_WD_EN_MASK 0x2976 977/* PDMA0_QM_CP_EXT_SWITCH */978#define PDMA0_QM_CP_EXT_SWITCH_VAL_SHIFT 0979#define PDMA0_QM_CP_EXT_SWITCH_VAL_MASK 0x1980 981/* PDMA0_QM_CP_SWITCH_WD_SET */982#define PDMA0_QM_CP_SWITCH_WD_SET_VAL_SHIFT 0983#define PDMA0_QM_CP_SWITCH_WD_SET_VAL_MASK 0xFFFFFFFF984 985/* PDMA0_QM_CP_SWITCH_WD */986#define PDMA0_QM_CP_SWITCH_WD_VAL_SHIFT 0987#define PDMA0_QM_CP_SWITCH_WD_VAL_MASK 0xFFFFFFFF988 989/* PDMA0_QM_ARC_LB_ADDR_BASE_LO */990#define PDMA0_QM_ARC_LB_ADDR_BASE_LO_VAL_SHIFT 0991#define PDMA0_QM_ARC_LB_ADDR_BASE_LO_VAL_MASK 0xFFFFFFFF992 993/* PDMA0_QM_ARC_LB_ADDR_BASE_HI */994#define PDMA0_QM_ARC_LB_ADDR_BASE_HI_VAL_SHIFT 0995#define PDMA0_QM_ARC_LB_ADDR_BASE_HI_VAL_MASK 0xFFFFFFFF996 997/* PDMA0_QM_ENGINE_BASE_ADDR_HI */998#define PDMA0_QM_ENGINE_BASE_ADDR_HI_VAL_SHIFT 0999#define PDMA0_QM_ENGINE_BASE_ADDR_HI_VAL_MASK 0xFFFFFFFF1000 1001/* PDMA0_QM_ENGINE_BASE_ADDR_LO */1002#define PDMA0_QM_ENGINE_BASE_ADDR_LO_VAL_SHIFT 01003#define PDMA0_QM_ENGINE_BASE_ADDR_LO_VAL_MASK 0xFFFFFFFF1004 1005/* PDMA0_QM_ENGINE_ADDR_RANGE_SIZE */1006#define PDMA0_QM_ENGINE_ADDR_RANGE_SIZE_VAL_SHIFT 01007#define PDMA0_QM_ENGINE_ADDR_RANGE_SIZE_VAL_MASK 0xFFFFFFFF1008 1009/* PDMA0_QM_QM_ARC_AUX_BASE_ADDR_HI */1010#define PDMA0_QM_QM_ARC_AUX_BASE_ADDR_HI_VAL_SHIFT 01011#define PDMA0_QM_QM_ARC_AUX_BASE_ADDR_HI_VAL_MASK 0xFFFFFFFF1012 1013/* PDMA0_QM_QM_ARC_AUX_BASE_ADDR_LO */1014#define PDMA0_QM_QM_ARC_AUX_BASE_ADDR_LO_VAL_SHIFT 01015#define PDMA0_QM_QM_ARC_AUX_BASE_ADDR_LO_VAL_MASK 0xFFFFFFFF1016 1017/* PDMA0_QM_QM_BASE_ADDR_HI */1018#define PDMA0_QM_QM_BASE_ADDR_HI_VAL_SHIFT 01019#define PDMA0_QM_QM_BASE_ADDR_HI_VAL_MASK 0xFFFFFFFF1020 1021/* PDMA0_QM_QM_BASE_ADDR_LO */1022#define PDMA0_QM_QM_BASE_ADDR_LO_VAL_SHIFT 01023#define PDMA0_QM_QM_BASE_ADDR_LO_VAL_MASK 0xFFFFFFFF1024 1025/* PDMA0_QM_ARC_PQC_SECURE_PUSH_IND */1026#define PDMA0_QM_ARC_PQC_SECURE_PUSH_IND_CP_NUM_SHIFT 01027#define PDMA0_QM_ARC_PQC_SECURE_PUSH_IND_CP_NUM_MASK 0x31028 1029/* PDMA0_QM_PQC_STS_0 */1030#define PDMA0_QM_PQC_STS_0_COMP_DATA_SHIFT 01031#define PDMA0_QM_PQC_STS_0_COMP_DATA_MASK 0xFFFF1032#define PDMA0_QM_PQC_STS_0_COMP_OFST_SHIFT 161033#define PDMA0_QM_PQC_STS_0_COMP_OFST_MASK 0xFFFF00001034 1035/* PDMA0_QM_PQC_STS_1 */1036#define PDMA0_QM_PQC_STS_1_COMP_FIFO_CNTR_SHIFT 01037#define PDMA0_QM_PQC_STS_1_COMP_FIFO_CNTR_MASK 0xF1038#define PDMA0_QM_PQC_STS_1_COMP_FIFO_EMPTY_SHIFT 41039#define PDMA0_QM_PQC_STS_1_COMP_FIFO_EMPTY_MASK 0x101040#define PDMA0_QM_PQC_STS_1_COMP_FIFO_FULL_SHIFT 51041#define PDMA0_QM_PQC_STS_1_COMP_FIFO_FULL_MASK 0x201042 1043/* PDMA0_QM_SEI_STATUS */1044#define PDMA0_QM_SEI_STATUS_QM_INT_SHIFT 01045#define PDMA0_QM_SEI_STATUS_QM_INT_MASK 0x11046#define PDMA0_QM_SEI_STATUS_ARC_INT_SHIFT 11047#define PDMA0_QM_SEI_STATUS_ARC_INT_MASK 0x21048 1049/* PDMA0_QM_SEI_MASK */1050#define PDMA0_QM_SEI_MASK_QM_INT_SHIFT 01051#define PDMA0_QM_SEI_MASK_QM_INT_MASK 0x11052#define PDMA0_QM_SEI_MASK_ARC_INT_SHIFT 11053#define PDMA0_QM_SEI_MASK_ARC_INT_MASK 0x21054 1055/* PDMA0_QM_GLBL_ERR_ADDR_LO */1056#define PDMA0_QM_GLBL_ERR_ADDR_LO_VAL_SHIFT 01057#define PDMA0_QM_GLBL_ERR_ADDR_LO_VAL_MASK 0xFFFFFFFF1058 1059/* PDMA0_QM_GLBL_ERR_ADDR_HI */1060#define PDMA0_QM_GLBL_ERR_ADDR_HI_VAL_SHIFT 01061#define PDMA0_QM_GLBL_ERR_ADDR_HI_VAL_MASK 0xFFFFFFFF1062 1063/* PDMA0_QM_GLBL_ERR_WDATA */1064#define PDMA0_QM_GLBL_ERR_WDATA_VAL_SHIFT 01065#define PDMA0_QM_GLBL_ERR_WDATA_VAL_MASK 0xFFFFFFFF1066 1067/* PDMA0_QM_L2H_MASK_LO */1068#define PDMA0_QM_L2H_MASK_LO_VAL_SHIFT 201069#define PDMA0_QM_L2H_MASK_LO_VAL_MASK 0xFFF000001070 1071/* PDMA0_QM_L2H_MASK_HI */1072#define PDMA0_QM_L2H_MASK_HI_VAL_SHIFT 01073#define PDMA0_QM_L2H_MASK_HI_VAL_MASK 0xFFFFFFFF1074 1075/* PDMA0_QM_L2H_CMPR_LO */1076#define PDMA0_QM_L2H_CMPR_LO_VAL_SHIFT 201077#define PDMA0_QM_L2H_CMPR_LO_VAL_MASK 0xFFF000001078 1079/* PDMA0_QM_L2H_CMPR_HI */1080#define PDMA0_QM_L2H_CMPR_HI_VAL_SHIFT 01081#define PDMA0_QM_L2H_CMPR_HI_VAL_MASK 0xFFFFFFFF1082 1083/* PDMA0_QM_LOCAL_RANGE_BASE */1084#define PDMA0_QM_LOCAL_RANGE_BASE_VAL_SHIFT 01085#define PDMA0_QM_LOCAL_RANGE_BASE_VAL_MASK 0xFFFF1086 1087/* PDMA0_QM_LOCAL_RANGE_SIZE */1088#define PDMA0_QM_LOCAL_RANGE_SIZE_VAL_SHIFT 01089#define PDMA0_QM_LOCAL_RANGE_SIZE_VAL_MASK 0xFFFF1090 1091/* PDMA0_QM_HBW_RD_RATE_LIM_CFG_1 */1092#define PDMA0_QM_HBW_RD_RATE_LIM_CFG_1_TOUT_SHIFT 01093#define PDMA0_QM_HBW_RD_RATE_LIM_CFG_1_TOUT_MASK 0xFF1094#define PDMA0_QM_HBW_RD_RATE_LIM_CFG_1_EN_SHIFT 311095#define PDMA0_QM_HBW_RD_RATE_LIM_CFG_1_EN_MASK 0x800000001096 1097/* PDMA0_QM_LBW_WR_RATE_LIM_CFG_0 */1098#define PDMA0_QM_LBW_WR_RATE_LIM_CFG_0_RST_TOKEN_SHIFT 01099#define PDMA0_QM_LBW_WR_RATE_LIM_CFG_0_RST_TOKEN_MASK 0xFF1100#define PDMA0_QM_LBW_WR_RATE_LIM_CFG_0_SAT_SHIFT 161101#define PDMA0_QM_LBW_WR_RATE_LIM_CFG_0_SAT_MASK 0xFF00001102 1103/* PDMA0_QM_LBW_WR_RATE_LIM_CFG_1 */1104#define PDMA0_QM_LBW_WR_RATE_LIM_CFG_1_TOUT_SHIFT 01105#define PDMA0_QM_LBW_WR_RATE_LIM_CFG_1_TOUT_MASK 0xFF1106#define PDMA0_QM_LBW_WR_RATE_LIM_CFG_1_EN_SHIFT 311107#define PDMA0_QM_LBW_WR_RATE_LIM_CFG_1_EN_MASK 0x800000001108 1109/* PDMA0_QM_HBW_RD_RATE_LIM_CFG_0 */1110#define PDMA0_QM_HBW_RD_RATE_LIM_CFG_0_RST_TOKEN_SHIFT 01111#define PDMA0_QM_HBW_RD_RATE_LIM_CFG_0_RST_TOKEN_MASK 0xFF1112#define PDMA0_QM_HBW_RD_RATE_LIM_CFG_0_SAT_SHIFT 161113#define PDMA0_QM_HBW_RD_RATE_LIM_CFG_0_SAT_MASK 0xFF00001114 1115/* PDMA0_QM_IND_GW_APB_CFG */1116#define PDMA0_QM_IND_GW_APB_CFG_ADDR_SHIFT 01117#define PDMA0_QM_IND_GW_APB_CFG_ADDR_MASK 0x7FFFFFFF1118#define PDMA0_QM_IND_GW_APB_CFG_CMD_SHIFT 311119#define PDMA0_QM_IND_GW_APB_CFG_CMD_MASK 0x800000001120 1121/* PDMA0_QM_IND_GW_APB_WDATA */1122#define PDMA0_QM_IND_GW_APB_WDATA_VAL_SHIFT 01123#define PDMA0_QM_IND_GW_APB_WDATA_VAL_MASK 0xFFFFFFFF1124 1125/* PDMA0_QM_IND_GW_APB_RDATA */1126#define PDMA0_QM_IND_GW_APB_RDATA_VAL_SHIFT 01127#define PDMA0_QM_IND_GW_APB_RDATA_VAL_MASK 0xFFFFFFFF1128 1129/* PDMA0_QM_IND_GW_APB_STATUS */1130#define PDMA0_QM_IND_GW_APB_STATUS_RDY_SHIFT 01131#define PDMA0_QM_IND_GW_APB_STATUS_RDY_MASK 0x11132#define PDMA0_QM_IND_GW_APB_STATUS_ERR_SHIFT 11133#define PDMA0_QM_IND_GW_APB_STATUS_ERR_MASK 0x21134 1135/* PDMA0_QM_PERF_CNT_FREE_LO */1136#define PDMA0_QM_PERF_CNT_FREE_LO_VAL_SHIFT 01137#define PDMA0_QM_PERF_CNT_FREE_LO_VAL_MASK 0xFFFFFFFF1138 1139/* PDMA0_QM_PERF_CNT_FREE_HI */1140#define PDMA0_QM_PERF_CNT_FREE_HI_VAL_SHIFT 01141#define PDMA0_QM_PERF_CNT_FREE_HI_VAL_MASK 0xFFFFFFFF1142 1143/* PDMA0_QM_PERF_CNT_IDLE_LO */1144#define PDMA0_QM_PERF_CNT_IDLE_LO_VAL_SHIFT 01145#define PDMA0_QM_PERF_CNT_IDLE_LO_VAL_MASK 0xFFFFFFFF1146 1147/* PDMA0_QM_PERF_CNT_IDLE_HI */1148#define PDMA0_QM_PERF_CNT_IDLE_HI_VAL_SHIFT 01149#define PDMA0_QM_PERF_CNT_IDLE_HI_VAL_MASK 0xFFFFFFFF1150 1151/* PDMA0_QM_PERF_CNT_CFG */1152#define PDMA0_QM_PERF_CNT_CFG_PQ_MASK_SHIFT 01153#define PDMA0_QM_PERF_CNT_CFG_PQ_MASK_MASK 0xF1154#define PDMA0_QM_PERF_CNT_CFG_CQ_MASK_SHIFT 81155#define PDMA0_QM_PERF_CNT_CFG_CQ_MASK_MASK 0x1F001156#define PDMA0_QM_PERF_CNT_CFG_CP_MASK_SHIFT 161157#define PDMA0_QM_PERF_CNT_CFG_CP_MASK_MASK 0x1F00001158#define PDMA0_QM_PERF_CNT_CFG_AGENT_MASK_SHIFT 241159#define PDMA0_QM_PERF_CNT_CFG_AGENT_MASK_MASK 0x10000001160#define PDMA0_QM_PERF_CNT_CFG_EN_FREE_SHIFT 301161#define PDMA0_QM_PERF_CNT_CFG_EN_FREE_MASK 0x400000001162#define PDMA0_QM_PERF_CNT_CFG_EN_IDLE_SHIFT 311163#define PDMA0_QM_PERF_CNT_CFG_EN_IDLE_MASK 0x800000001164 1165#endif /* ASIC_REG_PDMA0_QM_MASKS_H_ */1166