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1/* SPDX-License-Identifier: GPL-2.02 *3 * Copyright 2016-2020 HabanaLabs, Ltd.4 * All Rights Reserved.5 *6 */7 8/************************************9 ** This is an auto-generated file **10 ** DO NOT EDIT BELOW **11 ************************************/12 13#ifndef ASIC_REG_PDMA0_QM_REGS_H_14#define ASIC_REG_PDMA0_QM_REGS_H_15 16/*17 *****************************************18 * PDMA0_QM19 * (Prototype: QMAN)20 *****************************************21 */22 23#define mmPDMA0_QM_GLBL_CFG0 0x4C8A00024 25#define mmPDMA0_QM_GLBL_CFG1 0x4C8A00426 27#define mmPDMA0_QM_GLBL_CFG2 0x4C8A00828 29#define mmPDMA0_QM_GLBL_ERR_CFG 0x4C8A00C30 31#define mmPDMA0_QM_GLBL_ERR_CFG1 0x4C8A01032 33#define mmPDMA0_QM_GLBL_ERR_ARC_HALT_EN 0x4C8A01434 35#define mmPDMA0_QM_GLBL_AXCACHE 0x4C8A01836 37#define mmPDMA0_QM_GLBL_STS0 0x4C8A01C38 39#define mmPDMA0_QM_GLBL_STS1 0x4C8A02040 41#define mmPDMA0_QM_GLBL_ERR_STS_0 0x4C8A02442 43#define mmPDMA0_QM_GLBL_ERR_STS_1 0x4C8A02844 45#define mmPDMA0_QM_GLBL_ERR_STS_2 0x4C8A02C46 47#define mmPDMA0_QM_GLBL_ERR_STS_3 0x4C8A03048 49#define mmPDMA0_QM_GLBL_ERR_STS_4 0x4C8A03450 51#define mmPDMA0_QM_GLBL_ERR_MSG_EN_0 0x4C8A03852 53#define mmPDMA0_QM_GLBL_ERR_MSG_EN_1 0x4C8A03C54 55#define mmPDMA0_QM_GLBL_ERR_MSG_EN_2 0x4C8A04056 57#define mmPDMA0_QM_GLBL_ERR_MSG_EN_3 0x4C8A04458 59#define mmPDMA0_QM_GLBL_ERR_MSG_EN_4 0x4C8A04860 61#define mmPDMA0_QM_GLBL_PROT 0x4C8A04C62 63#define mmPDMA0_QM_PQ_BASE_LO_0 0x4C8A05064 65#define mmPDMA0_QM_PQ_BASE_LO_1 0x4C8A05466 67#define mmPDMA0_QM_PQ_BASE_LO_2 0x4C8A05868 69#define mmPDMA0_QM_PQ_BASE_LO_3 0x4C8A05C70 71#define mmPDMA0_QM_PQ_BASE_HI_0 0x4C8A06072 73#define mmPDMA0_QM_PQ_BASE_HI_1 0x4C8A06474 75#define mmPDMA0_QM_PQ_BASE_HI_2 0x4C8A06876 77#define mmPDMA0_QM_PQ_BASE_HI_3 0x4C8A06C78 79#define mmPDMA0_QM_PQ_SIZE_0 0x4C8A07080 81#define mmPDMA0_QM_PQ_SIZE_1 0x4C8A07482 83#define mmPDMA0_QM_PQ_SIZE_2 0x4C8A07884 85#define mmPDMA0_QM_PQ_SIZE_3 0x4C8A07C86 87#define mmPDMA0_QM_PQ_PI_0 0x4C8A08088 89#define mmPDMA0_QM_PQ_PI_1 0x4C8A08490 91#define mmPDMA0_QM_PQ_PI_2 0x4C8A08892 93#define mmPDMA0_QM_PQ_PI_3 0x4C8A08C94 95#define mmPDMA0_QM_PQ_CI_0 0x4C8A09096 97#define mmPDMA0_QM_PQ_CI_1 0x4C8A09498 99#define mmPDMA0_QM_PQ_CI_2 0x4C8A098100 101#define mmPDMA0_QM_PQ_CI_3 0x4C8A09C102 103#define mmPDMA0_QM_PQ_CFG0_0 0x4C8A0A0104 105#define mmPDMA0_QM_PQ_CFG0_1 0x4C8A0A4106 107#define mmPDMA0_QM_PQ_CFG0_2 0x4C8A0A8108 109#define mmPDMA0_QM_PQ_CFG0_3 0x4C8A0AC110 111#define mmPDMA0_QM_PQ_CFG1_0 0x4C8A0B0112 113#define mmPDMA0_QM_PQ_CFG1_1 0x4C8A0B4114 115#define mmPDMA0_QM_PQ_CFG1_2 0x4C8A0B8116 117#define mmPDMA0_QM_PQ_CFG1_3 0x4C8A0BC118 119#define mmPDMA0_QM_PQ_STS0_0 0x4C8A0C0120 121#define mmPDMA0_QM_PQ_STS0_1 0x4C8A0C4122 123#define mmPDMA0_QM_PQ_STS0_2 0x4C8A0C8124 125#define mmPDMA0_QM_PQ_STS0_3 0x4C8A0CC126 127#define mmPDMA0_QM_PQ_STS1_0 0x4C8A0D0128 129#define mmPDMA0_QM_PQ_STS1_1 0x4C8A0D4130 131#define mmPDMA0_QM_PQ_STS1_2 0x4C8A0D8132 133#define mmPDMA0_QM_PQ_STS1_3 0x4C8A0DC134 135#define mmPDMA0_QM_CQ_CFG0_0 0x4C8A0E0136 137#define mmPDMA0_QM_CQ_CFG0_1 0x4C8A0E4138 139#define mmPDMA0_QM_CQ_CFG0_2 0x4C8A0E8140 141#define mmPDMA0_QM_CQ_CFG0_3 0x4C8A0EC142 143#define mmPDMA0_QM_CQ_CFG0_4 0x4C8A0F0144 145#define mmPDMA0_QM_CQ_STS0_0 0x4C8A0F4146 147#define mmPDMA0_QM_CQ_STS0_1 0x4C8A0F8148 149#define mmPDMA0_QM_CQ_STS0_2 0x4C8A0FC150 151#define mmPDMA0_QM_CQ_STS0_3 0x4C8A100152 153#define mmPDMA0_QM_CQ_STS0_4 0x4C8A104154 155#define mmPDMA0_QM_CQ_CFG1_0 0x4C8A108156 157#define mmPDMA0_QM_CQ_CFG1_1 0x4C8A10C158 159#define mmPDMA0_QM_CQ_CFG1_2 0x4C8A110160 161#define mmPDMA0_QM_CQ_CFG1_3 0x4C8A114162 163#define mmPDMA0_QM_CQ_CFG1_4 0x4C8A118164 165#define mmPDMA0_QM_CQ_STS1_0 0x4C8A11C166 167#define mmPDMA0_QM_CQ_STS1_1 0x4C8A120168 169#define mmPDMA0_QM_CQ_STS1_2 0x4C8A124170 171#define mmPDMA0_QM_CQ_STS1_3 0x4C8A128172 173#define mmPDMA0_QM_CQ_STS1_4 0x4C8A12C174 175#define mmPDMA0_QM_CQ_PTR_LO_0 0x4C8A150176 177#define mmPDMA0_QM_CQ_PTR_HI_0 0x4C8A154178 179#define mmPDMA0_QM_CQ_TSIZE_0 0x4C8A158180 181#define mmPDMA0_QM_CQ_CTL_0 0x4C8A15C182 183#define mmPDMA0_QM_CQ_PTR_LO_1 0x4C8A160184 185#define mmPDMA0_QM_CQ_PTR_HI_1 0x4C8A164186 187#define mmPDMA0_QM_CQ_TSIZE_1 0x4C8A168188 189#define mmPDMA0_QM_CQ_CTL_1 0x4C8A16C190 191#define mmPDMA0_QM_CQ_PTR_LO_2 0x4C8A170192 193#define mmPDMA0_QM_CQ_PTR_HI_2 0x4C8A174194 195#define mmPDMA0_QM_CQ_TSIZE_2 0x4C8A178196 197#define mmPDMA0_QM_CQ_CTL_2 0x4C8A17C198 199#define mmPDMA0_QM_CQ_PTR_LO_3 0x4C8A180200 201#define mmPDMA0_QM_CQ_PTR_HI_3 0x4C8A184202 203#define mmPDMA0_QM_CQ_TSIZE_3 0x4C8A188204 205#define mmPDMA0_QM_CQ_CTL_3 0x4C8A18C206 207#define mmPDMA0_QM_CQ_PTR_LO_4 0x4C8A190208 209#define mmPDMA0_QM_CQ_PTR_HI_4 0x4C8A194210 211#define mmPDMA0_QM_CQ_TSIZE_4 0x4C8A198212 213#define mmPDMA0_QM_CQ_CTL_4 0x4C8A19C214 215#define mmPDMA0_QM_CQ_TSIZE_STS_0 0x4C8A1A0216 217#define mmPDMA0_QM_CQ_TSIZE_STS_1 0x4C8A1A4218 219#define mmPDMA0_QM_CQ_TSIZE_STS_2 0x4C8A1A8220 221#define mmPDMA0_QM_CQ_TSIZE_STS_3 0x4C8A1AC222 223#define mmPDMA0_QM_CQ_TSIZE_STS_4 0x4C8A1B0224 225#define mmPDMA0_QM_CQ_PTR_LO_STS_0 0x4C8A1B4226 227#define mmPDMA0_QM_CQ_PTR_LO_STS_1 0x4C8A1B8228 229#define mmPDMA0_QM_CQ_PTR_LO_STS_2 0x4C8A1BC230 231#define mmPDMA0_QM_CQ_PTR_LO_STS_3 0x4C8A1C0232 233#define mmPDMA0_QM_CQ_PTR_LO_STS_4 0x4C8A1C4234 235#define mmPDMA0_QM_CQ_PTR_HI_STS_0 0x4C8A1C8236 237#define mmPDMA0_QM_CQ_PTR_HI_STS_1 0x4C8A1CC238 239#define mmPDMA0_QM_CQ_PTR_HI_STS_2 0x4C8A1D0240 241#define mmPDMA0_QM_CQ_PTR_HI_STS_3 0x4C8A1D4242 243#define mmPDMA0_QM_CQ_PTR_HI_STS_4 0x4C8A1D8244 245#define mmPDMA0_QM_CQ_IFIFO_STS_0 0x4C8A1DC246 247#define mmPDMA0_QM_CQ_IFIFO_STS_1 0x4C8A1E0248 249#define mmPDMA0_QM_CQ_IFIFO_STS_2 0x4C8A1E4250 251#define mmPDMA0_QM_CQ_IFIFO_STS_3 0x4C8A1E8252 253#define mmPDMA0_QM_CQ_IFIFO_STS_4 0x4C8A1EC254 255#define mmPDMA0_QM_CP_MSG_BASE0_ADDR_LO_0 0x4C8A1F0256 257#define mmPDMA0_QM_CP_MSG_BASE0_ADDR_LO_1 0x4C8A1F4258 259#define mmPDMA0_QM_CP_MSG_BASE0_ADDR_LO_2 0x4C8A1F8260 261#define mmPDMA0_QM_CP_MSG_BASE0_ADDR_LO_3 0x4C8A1FC262 263#define mmPDMA0_QM_CP_MSG_BASE0_ADDR_LO_4 0x4C8A200264 265#define mmPDMA0_QM_CP_MSG_BASE0_ADDR_HI_0 0x4C8A204266 267#define mmPDMA0_QM_CP_MSG_BASE0_ADDR_HI_1 0x4C8A208268 269#define mmPDMA0_QM_CP_MSG_BASE0_ADDR_HI_2 0x4C8A20C270 271#define mmPDMA0_QM_CP_MSG_BASE0_ADDR_HI_3 0x4C8A210272 273#define mmPDMA0_QM_CP_MSG_BASE0_ADDR_HI_4 0x4C8A214274 275#define mmPDMA0_QM_CP_MSG_BASE1_ADDR_LO_0 0x4C8A218276 277#define mmPDMA0_QM_CP_MSG_BASE1_ADDR_LO_1 0x4C8A21C278 279#define mmPDMA0_QM_CP_MSG_BASE1_ADDR_LO_2 0x4C8A220280 281#define mmPDMA0_QM_CP_MSG_BASE1_ADDR_LO_3 0x4C8A224282 283#define mmPDMA0_QM_CP_MSG_BASE1_ADDR_LO_4 0x4C8A228284 285#define mmPDMA0_QM_CP_MSG_BASE1_ADDR_HI_0 0x4C8A22C286 287#define mmPDMA0_QM_CP_MSG_BASE1_ADDR_HI_1 0x4C8A230288 289#define mmPDMA0_QM_CP_MSG_BASE1_ADDR_HI_2 0x4C8A234290 291#define mmPDMA0_QM_CP_MSG_BASE1_ADDR_HI_3 0x4C8A238292 293#define mmPDMA0_QM_CP_MSG_BASE1_ADDR_HI_4 0x4C8A23C294 295#define mmPDMA0_QM_CP_MSG_BASE2_ADDR_LO_0 0x4C8A240296 297#define mmPDMA0_QM_CP_MSG_BASE2_ADDR_LO_1 0x4C8A244298 299#define mmPDMA0_QM_CP_MSG_BASE2_ADDR_LO_2 0x4C8A248300 301#define mmPDMA0_QM_CP_MSG_BASE2_ADDR_LO_3 0x4C8A24C302 303#define mmPDMA0_QM_CP_MSG_BASE2_ADDR_LO_4 0x4C8A250304 305#define mmPDMA0_QM_CP_MSG_BASE2_ADDR_HI_0 0x4C8A254306 307#define mmPDMA0_QM_CP_MSG_BASE2_ADDR_HI_1 0x4C8A258308 309#define mmPDMA0_QM_CP_MSG_BASE2_ADDR_HI_2 0x4C8A25C310 311#define mmPDMA0_QM_CP_MSG_BASE2_ADDR_HI_3 0x4C8A260312 313#define mmPDMA0_QM_CP_MSG_BASE2_ADDR_HI_4 0x4C8A264314 315#define mmPDMA0_QM_CP_MSG_BASE3_ADDR_LO_0 0x4C8A268316 317#define mmPDMA0_QM_CP_MSG_BASE3_ADDR_LO_1 0x4C8A26C318 319#define mmPDMA0_QM_CP_MSG_BASE3_ADDR_LO_2 0x4C8A270320 321#define mmPDMA0_QM_CP_MSG_BASE3_ADDR_LO_3 0x4C8A274322 323#define mmPDMA0_QM_CP_MSG_BASE3_ADDR_LO_4 0x4C8A278324 325#define mmPDMA0_QM_CP_MSG_BASE3_ADDR_HI_0 0x4C8A27C326 327#define mmPDMA0_QM_CP_MSG_BASE3_ADDR_HI_1 0x4C8A280328 329#define mmPDMA0_QM_CP_MSG_BASE3_ADDR_HI_2 0x4C8A284330 331#define mmPDMA0_QM_CP_MSG_BASE3_ADDR_HI_3 0x4C8A288332 333#define mmPDMA0_QM_CP_MSG_BASE3_ADDR_HI_4 0x4C8A28C334 335#define mmPDMA0_QM_CP_FENCE0_RDATA_0 0x4C8A290336 337#define mmPDMA0_QM_CP_FENCE0_RDATA_1 0x4C8A294338 339#define mmPDMA0_QM_CP_FENCE0_RDATA_2 0x4C8A298340 341#define mmPDMA0_QM_CP_FENCE0_RDATA_3 0x4C8A29C342 343#define mmPDMA0_QM_CP_FENCE0_RDATA_4 0x4C8A2A0344 345#define mmPDMA0_QM_CP_FENCE1_RDATA_0 0x4C8A2A4346 347#define mmPDMA0_QM_CP_FENCE1_RDATA_1 0x4C8A2A8348 349#define mmPDMA0_QM_CP_FENCE1_RDATA_2 0x4C8A2AC350 351#define mmPDMA0_QM_CP_FENCE1_RDATA_3 0x4C8A2B0352 353#define mmPDMA0_QM_CP_FENCE1_RDATA_4 0x4C8A2B4354 355#define mmPDMA0_QM_CP_FENCE2_RDATA_0 0x4C8A2B8356 357#define mmPDMA0_QM_CP_FENCE2_RDATA_1 0x4C8A2BC358 359#define mmPDMA0_QM_CP_FENCE2_RDATA_2 0x4C8A2C0360 361#define mmPDMA0_QM_CP_FENCE2_RDATA_3 0x4C8A2C4362 363#define mmPDMA0_QM_CP_FENCE2_RDATA_4 0x4C8A2C8364 365#define mmPDMA0_QM_CP_FENCE3_RDATA_0 0x4C8A2CC366 367#define mmPDMA0_QM_CP_FENCE3_RDATA_1 0x4C8A2D0368 369#define mmPDMA0_QM_CP_FENCE3_RDATA_2 0x4C8A2D4370 371#define mmPDMA0_QM_CP_FENCE3_RDATA_3 0x4C8A2D8372 373#define mmPDMA0_QM_CP_FENCE3_RDATA_4 0x4C8A2DC374 375#define mmPDMA0_QM_CP_FENCE0_CNT_0 0x4C8A2E0376 377#define mmPDMA0_QM_CP_FENCE0_CNT_1 0x4C8A2E4378 379#define mmPDMA0_QM_CP_FENCE0_CNT_2 0x4C8A2E8380 381#define mmPDMA0_QM_CP_FENCE0_CNT_3 0x4C8A2EC382 383#define mmPDMA0_QM_CP_FENCE0_CNT_4 0x4C8A2F0384 385#define mmPDMA0_QM_CP_FENCE1_CNT_0 0x4C8A2F4386 387#define mmPDMA0_QM_CP_FENCE1_CNT_1 0x4C8A2F8388 389#define mmPDMA0_QM_CP_FENCE1_CNT_2 0x4C8A2FC390 391#define mmPDMA0_QM_CP_FENCE1_CNT_3 0x4C8A300392 393#define mmPDMA0_QM_CP_FENCE1_CNT_4 0x4C8A304394 395#define mmPDMA0_QM_CP_FENCE2_CNT_0 0x4C8A308396 397#define mmPDMA0_QM_CP_FENCE2_CNT_1 0x4C8A30C398 399#define mmPDMA0_QM_CP_FENCE2_CNT_2 0x4C8A310400 401#define mmPDMA0_QM_CP_FENCE2_CNT_3 0x4C8A314402 403#define mmPDMA0_QM_CP_FENCE2_CNT_4 0x4C8A318404 405#define mmPDMA0_QM_CP_FENCE3_CNT_0 0x4C8A31C406 407#define mmPDMA0_QM_CP_FENCE3_CNT_1 0x4C8A320408 409#define mmPDMA0_QM_CP_FENCE3_CNT_2 0x4C8A324410 411#define mmPDMA0_QM_CP_FENCE3_CNT_3 0x4C8A328412 413#define mmPDMA0_QM_CP_FENCE3_CNT_4 0x4C8A32C414 415#define mmPDMA0_QM_CP_BARRIER_CFG 0x4C8A330416 417#define mmPDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET 0x4C8A334418 419#define mmPDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET 0x4C8A338420 421#define mmPDMA0_QM_CP_LDMA_TSIZE_OFFSET 0x4C8A33C422 423#define mmPDMA0_QM_CP_CQ_PTR_LO_OFFSET_0 0x4C8A340424 425#define mmPDMA0_QM_CP_CQ_PTR_LO_OFFSET_1 0x4C8A344426 427#define mmPDMA0_QM_CP_CQ_PTR_LO_OFFSET_2 0x4C8A348428 429#define mmPDMA0_QM_CP_CQ_PTR_LO_OFFSET_3 0x4C8A34C430 431#define mmPDMA0_QM_CP_CQ_PTR_LO_OFFSET_4 0x4C8A350432 433#define mmPDMA0_QM_CP_STS_0 0x4C8A368434 435#define mmPDMA0_QM_CP_STS_1 0x4C8A36C436 437#define mmPDMA0_QM_CP_STS_2 0x4C8A370438 439#define mmPDMA0_QM_CP_STS_3 0x4C8A374440 441#define mmPDMA0_QM_CP_STS_4 0x4C8A378442 443#define mmPDMA0_QM_CP_CURRENT_INST_LO_0 0x4C8A37C444 445#define mmPDMA0_QM_CP_CURRENT_INST_LO_1 0x4C8A380446 447#define mmPDMA0_QM_CP_CURRENT_INST_LO_2 0x4C8A384448 449#define mmPDMA0_QM_CP_CURRENT_INST_LO_3 0x4C8A388450 451#define mmPDMA0_QM_CP_CURRENT_INST_LO_4 0x4C8A38C452 453#define mmPDMA0_QM_CP_CURRENT_INST_HI_0 0x4C8A390454 455#define mmPDMA0_QM_CP_CURRENT_INST_HI_1 0x4C8A394456 457#define mmPDMA0_QM_CP_CURRENT_INST_HI_2 0x4C8A398458 459#define mmPDMA0_QM_CP_CURRENT_INST_HI_3 0x4C8A39C460 461#define mmPDMA0_QM_CP_CURRENT_INST_HI_4 0x4C8A3A0462 463#define mmPDMA0_QM_CP_PRED_0 0x4C8A3A4464 465#define mmPDMA0_QM_CP_PRED_1 0x4C8A3A8466 467#define mmPDMA0_QM_CP_PRED_2 0x4C8A3AC468 469#define mmPDMA0_QM_CP_PRED_3 0x4C8A3B0470 471#define mmPDMA0_QM_CP_PRED_4 0x4C8A3B4472 473#define mmPDMA0_QM_CP_PRED_UPEN_0 0x4C8A3B8474 475#define mmPDMA0_QM_CP_PRED_UPEN_1 0x4C8A3BC476 477#define mmPDMA0_QM_CP_PRED_UPEN_2 0x4C8A3C0478 479#define mmPDMA0_QM_CP_PRED_UPEN_3 0x4C8A3C4480 481#define mmPDMA0_QM_CP_PRED_UPEN_4 0x4C8A3C8482 483#define mmPDMA0_QM_CP_DBG_0_0 0x4C8A3CC484 485#define mmPDMA0_QM_CP_DBG_0_1 0x4C8A3D0486 487#define mmPDMA0_QM_CP_DBG_0_2 0x4C8A3D4488 489#define mmPDMA0_QM_CP_DBG_0_3 0x4C8A3D8490 491#define mmPDMA0_QM_CP_DBG_0_4 0x4C8A3DC492 493#define mmPDMA0_QM_CP_CPDMA_UP_CRED_0 0x4C8A3E0494 495#define mmPDMA0_QM_CP_CPDMA_UP_CRED_1 0x4C8A3E4496 497#define mmPDMA0_QM_CP_CPDMA_UP_CRED_2 0x4C8A3E8498 499#define mmPDMA0_QM_CP_CPDMA_UP_CRED_3 0x4C8A3EC500 501#define mmPDMA0_QM_CP_CPDMA_UP_CRED_4 0x4C8A3F0502 503#define mmPDMA0_QM_CP_IN_DATA_LO_0 0x4C8A3F4504 505#define mmPDMA0_QM_CP_IN_DATA_LO_1 0x4C8A3F8506 507#define mmPDMA0_QM_CP_IN_DATA_LO_2 0x4C8A3FC508 509#define mmPDMA0_QM_CP_IN_DATA_LO_3 0x4C8A400510 511#define mmPDMA0_QM_CP_IN_DATA_LO_4 0x4C8A404512 513#define mmPDMA0_QM_CP_IN_DATA_HI_0 0x4C8A408514 515#define mmPDMA0_QM_CP_IN_DATA_HI_1 0x4C8A40C516 517#define mmPDMA0_QM_CP_IN_DATA_HI_2 0x4C8A410518 519#define mmPDMA0_QM_CP_IN_DATA_HI_3 0x4C8A414520 521#define mmPDMA0_QM_CP_IN_DATA_HI_4 0x4C8A418522 523#define mmPDMA0_QM_PQC_HBW_BASE_LO_0 0x4C8A41C524 525#define mmPDMA0_QM_PQC_HBW_BASE_LO_1 0x4C8A420526 527#define mmPDMA0_QM_PQC_HBW_BASE_LO_2 0x4C8A424528 529#define mmPDMA0_QM_PQC_HBW_BASE_LO_3 0x4C8A428530 531#define mmPDMA0_QM_PQC_HBW_BASE_HI_0 0x4C8A42C532 533#define mmPDMA0_QM_PQC_HBW_BASE_HI_1 0x4C8A430534 535#define mmPDMA0_QM_PQC_HBW_BASE_HI_2 0x4C8A434536 537#define mmPDMA0_QM_PQC_HBW_BASE_HI_3 0x4C8A438538 539#define mmPDMA0_QM_PQC_SIZE_0 0x4C8A43C540 541#define mmPDMA0_QM_PQC_SIZE_1 0x4C8A440542 543#define mmPDMA0_QM_PQC_SIZE_2 0x4C8A444544 545#define mmPDMA0_QM_PQC_SIZE_3 0x4C8A448546 547#define mmPDMA0_QM_PQC_PI_0 0x4C8A44C548 549#define mmPDMA0_QM_PQC_PI_1 0x4C8A450550 551#define mmPDMA0_QM_PQC_PI_2 0x4C8A454552 553#define mmPDMA0_QM_PQC_PI_3 0x4C8A458554 555#define mmPDMA0_QM_PQC_LBW_WDATA_0 0x4C8A45C556 557#define mmPDMA0_QM_PQC_LBW_WDATA_1 0x4C8A460558 559#define mmPDMA0_QM_PQC_LBW_WDATA_2 0x4C8A464560 561#define mmPDMA0_QM_PQC_LBW_WDATA_3 0x4C8A468562 563#define mmPDMA0_QM_PQC_LBW_BASE_LO_0 0x4C8A46C564 565#define mmPDMA0_QM_PQC_LBW_BASE_LO_1 0x4C8A470566 567#define mmPDMA0_QM_PQC_LBW_BASE_LO_2 0x4C8A474568 569#define mmPDMA0_QM_PQC_LBW_BASE_LO_3 0x4C8A478570 571#define mmPDMA0_QM_PQC_LBW_BASE_HI_0 0x4C8A47C572 573#define mmPDMA0_QM_PQC_LBW_BASE_HI_1 0x4C8A480574 575#define mmPDMA0_QM_PQC_LBW_BASE_HI_2 0x4C8A484576 577#define mmPDMA0_QM_PQC_LBW_BASE_HI_3 0x4C8A488578 579#define mmPDMA0_QM_PQC_CFG 0x4C8A48C580 581#define mmPDMA0_QM_PQC_SECURE_PUSH_IND 0x4C8A490582 583#define mmPDMA0_QM_ARB_MASK 0x4C8A4A0584 585#define mmPDMA0_QM_ARB_CFG_0 0x4C8A4A4586 587#define mmPDMA0_QM_ARB_CHOICE_Q_PUSH 0x4C8A4A8588 589#define mmPDMA0_QM_ARB_WRR_WEIGHT_0 0x4C8A4AC590 591#define mmPDMA0_QM_ARB_WRR_WEIGHT_1 0x4C8A4B0592 593#define mmPDMA0_QM_ARB_WRR_WEIGHT_2 0x4C8A4B4594 595#define mmPDMA0_QM_ARB_WRR_WEIGHT_3 0x4C8A4B8596 597#define mmPDMA0_QM_ARB_CFG_1 0x4C8A4BC598 599#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_0 0x4C8A4C0600 601#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_1 0x4C8A4C4602 603#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_2 0x4C8A4C8604 605#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_3 0x4C8A4CC606 607#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_4 0x4C8A4D0608 609#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_5 0x4C8A4D4610 611#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_6 0x4C8A4D8612 613#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_7 0x4C8A4DC614 615#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_8 0x4C8A4E0616 617#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_9 0x4C8A4E4618 619#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_10 0x4C8A4E8620 621#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_11 0x4C8A4EC622 623#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_12 0x4C8A4F0624 625#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_13 0x4C8A4F4626 627#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_14 0x4C8A4F8628 629#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_15 0x4C8A4FC630 631#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_16 0x4C8A500632 633#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_17 0x4C8A504634 635#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_18 0x4C8A508636 637#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_19 0x4C8A50C638 639#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_20 0x4C8A510640 641#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_21 0x4C8A514642 643#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_22 0x4C8A518644 645#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_23 0x4C8A51C646 647#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_24 0x4C8A520648 649#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_25 0x4C8A524650 651#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_26 0x4C8A528652 653#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_27 0x4C8A52C654 655#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_28 0x4C8A530656 657#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_29 0x4C8A534658 659#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_30 0x4C8A538660 661#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_31 0x4C8A53C662 663#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_32 0x4C8A540664 665#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_33 0x4C8A544666 667#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_34 0x4C8A548668 669#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_35 0x4C8A54C670 671#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_36 0x4C8A550672 673#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_37 0x4C8A554674 675#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_38 0x4C8A558676 677#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_39 0x4C8A55C678 679#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_40 0x4C8A560680 681#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_41 0x4C8A564682 683#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_42 0x4C8A568684 685#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_43 0x4C8A56C686 687#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_44 0x4C8A570688 689#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_45 0x4C8A574690 691#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_46 0x4C8A578692 693#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_47 0x4C8A57C694 695#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_48 0x4C8A580696 697#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_49 0x4C8A584698 699#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_50 0x4C8A588700 701#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_51 0x4C8A58C702 703#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_52 0x4C8A590704 705#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_53 0x4C8A594706 707#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_54 0x4C8A598708 709#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_55 0x4C8A59C710 711#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_56 0x4C8A5A0712 713#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_57 0x4C8A5A4714 715#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_58 0x4C8A5A8716 717#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_59 0x4C8A5AC718 719#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_60 0x4C8A5B0720 721#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_61 0x4C8A5B4722 723#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_62 0x4C8A5B8724 725#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_63 0x4C8A5BC726 727#define mmPDMA0_QM_ARB_MST_CRED_INC 0x4C8A5E0728 729#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_0 0x4C8A5E4730 731#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_1 0x4C8A5E8732 733#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_2 0x4C8A5EC734 735#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_3 0x4C8A5F0736 737#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_4 0x4C8A5F4738 739#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_5 0x4C8A5F8740 741#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_6 0x4C8A5FC742 743#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_7 0x4C8A600744 745#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_8 0x4C8A604746 747#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_9 0x4C8A608748 749#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_10 0x4C8A60C750 751#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_11 0x4C8A610752 753#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_12 0x4C8A614754 755#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_13 0x4C8A618756 757#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_14 0x4C8A61C758 759#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_15 0x4C8A620760 761#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_16 0x4C8A624762 763#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_17 0x4C8A628764 765#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_18 0x4C8A62C766 767#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_19 0x4C8A630768 769#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_20 0x4C8A634770 771#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_21 0x4C8A638772 773#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_22 0x4C8A63C774 775#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_23 0x4C8A640776 777#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_24 0x4C8A644778 779#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_25 0x4C8A648780 781#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_26 0x4C8A64C782 783#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_27 0x4C8A650784 785#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_28 0x4C8A654786 787#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_29 0x4C8A658788 789#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_30 0x4C8A65C790 791#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_31 0x4C8A660792 793#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_32 0x4C8A664794 795#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_33 0x4C8A668796 797#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_34 0x4C8A66C798 799#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_35 0x4C8A670800 801#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_36 0x4C8A674802 803#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_37 0x4C8A678804 805#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_38 0x4C8A67C806 807#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_39 0x4C8A680808 809#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_40 0x4C8A684810 811#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_41 0x4C8A688812 813#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_42 0x4C8A68C814 815#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_43 0x4C8A690816 817#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_44 0x4C8A694818 819#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_45 0x4C8A698820 821#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_46 0x4C8A69C822 823#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_47 0x4C8A6A0824 825#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_48 0x4C8A6A4826 827#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_49 0x4C8A6A8828 829#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_50 0x4C8A6AC830 831#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_51 0x4C8A6B0832 833#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_52 0x4C8A6B4834 835#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_53 0x4C8A6B8836 837#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_54 0x4C8A6BC838 839#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_55 0x4C8A6C0840 841#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_56 0x4C8A6C4842 843#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_57 0x4C8A6C8844 845#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_58 0x4C8A6CC846 847#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_59 0x4C8A6D0848 849#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_60 0x4C8A6D4850 851#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_61 0x4C8A6D8852 853#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_62 0x4C8A6DC854 855#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_63 0x4C8A6E0856 857#define mmPDMA0_QM_ARB_SLV_MASTER_INC_CRED_OFST 0x4C8A704858 859#define mmPDMA0_QM_ARB_MST_SLAVE_EN 0x4C8A708860 861#define mmPDMA0_QM_ARB_MST_SLAVE_EN_1 0x4C8A70C862 863#define mmPDMA0_QM_ARB_SLV_CHOICE_WDT 0x4C8A710864 865#define mmPDMA0_QM_ARB_SLV_ID 0x4C8A714866 867#define mmPDMA0_QM_ARB_MST_QUIET_PER 0x4C8A718868 869#define mmPDMA0_QM_ARB_MSG_MAX_INFLIGHT 0x4C8A744870 871#define mmPDMA0_QM_ARB_BASE_LO 0x4C8A754872 873#define mmPDMA0_QM_ARB_BASE_HI 0x4C8A758874 875#define mmPDMA0_QM_ARB_STATE_STS 0x4C8A780876 877#define mmPDMA0_QM_ARB_CHOICE_FULLNESS_STS 0x4C8A784878 879#define mmPDMA0_QM_ARB_MSG_STS 0x4C8A788880 881#define mmPDMA0_QM_ARB_SLV_CHOICE_Q_HEAD 0x4C8A78C882 883#define mmPDMA0_QM_ARB_ERR_CAUSE 0x4C8A79C884 885#define mmPDMA0_QM_ARB_ERR_MSG_EN 0x4C8A7A0886 887#define mmPDMA0_QM_ARB_ERR_STS_DRP 0x4C8A7A8888 889#define mmPDMA0_QM_ARB_MST_CRED_STS 0x4C8A7B0890 891#define mmPDMA0_QM_ARB_MST_CRED_STS_1 0x4C8A7B4892 893#define mmPDMA0_QM_CSMR_STRICT_PRIO_CFG 0x4C8A7FC894 895#define mmPDMA0_QM_ARC_CQ_CFG0 0x4C8A800896 897#define mmPDMA0_QM_ARC_CQ_CFG1 0x4C8A804898 899#define mmPDMA0_QM_ARC_CQ_PTR_LO 0x4C8A808900 901#define mmPDMA0_QM_ARC_CQ_PTR_HI 0x4C8A80C902 903#define mmPDMA0_QM_ARC_CQ_TSIZE 0x4C8A810904 905#define mmPDMA0_QM_ARC_CQ_CTL 0x4C8A814906 907#define mmPDMA0_QM_ARC_CQ_IFIFO_STS 0x4C8A81C908 909#define mmPDMA0_QM_ARC_CQ_STS0 0x4C8A820910 911#define mmPDMA0_QM_ARC_CQ_STS1 0x4C8A824912 913#define mmPDMA0_QM_ARC_CQ_TSIZE_STS 0x4C8A828914 915#define mmPDMA0_QM_ARC_CQ_PTR_LO_STS 0x4C8A82C916 917#define mmPDMA0_QM_ARC_CQ_PTR_HI_STS 0x4C8A830918 919#define mmPDMA0_QM_CP_WR_ARC_ADDR_HI 0x4C8A834920 921#define mmPDMA0_QM_CP_WR_ARC_ADDR_LO 0x4C8A838922 923#define mmPDMA0_QM_ARC_CQ_IFIFO_MSG_BASE_HI 0x4C8A83C924 925#define mmPDMA0_QM_ARC_CQ_IFIFO_MSG_BASE_LO 0x4C8A840926 927#define mmPDMA0_QM_ARC_CQ_CTL_MSG_BASE_HI 0x4C8A844928 929#define mmPDMA0_QM_ARC_CQ_CTL_MSG_BASE_LO 0x4C8A848930 931#define mmPDMA0_QM_CQ_IFIFO_MSG_BASE_HI 0x4C8A84C932 933#define mmPDMA0_QM_CQ_IFIFO_MSG_BASE_LO 0x4C8A850934 935#define mmPDMA0_QM_CQ_CTL_MSG_BASE_HI 0x4C8A854936 937#define mmPDMA0_QM_CQ_CTL_MSG_BASE_LO 0x4C8A858938 939#define mmPDMA0_QM_ADDR_OVRD 0x4C8A85C940 941#define mmPDMA0_QM_CQ_IFIFO_CI_0 0x4C8A860942 943#define mmPDMA0_QM_CQ_IFIFO_CI_1 0x4C8A864944 945#define mmPDMA0_QM_CQ_IFIFO_CI_2 0x4C8A868946 947#define mmPDMA0_QM_CQ_IFIFO_CI_3 0x4C8A86C948 949#define mmPDMA0_QM_CQ_IFIFO_CI_4 0x4C8A870950 951#define mmPDMA0_QM_ARC_CQ_IFIFO_CI 0x4C8A874952 953#define mmPDMA0_QM_CQ_CTL_CI_0 0x4C8A878954 955#define mmPDMA0_QM_CQ_CTL_CI_1 0x4C8A87C956 957#define mmPDMA0_QM_CQ_CTL_CI_2 0x4C8A880958 959#define mmPDMA0_QM_CQ_CTL_CI_3 0x4C8A884960 961#define mmPDMA0_QM_CQ_CTL_CI_4 0x4C8A888962 963#define mmPDMA0_QM_ARC_CQ_CTL_CI 0x4C8A88C964 965#define mmPDMA0_QM_CP_CFG 0x4C8A890966 967#define mmPDMA0_QM_CP_EXT_SWITCH 0x4C8A894968 969#define mmPDMA0_QM_CP_SWITCH_WD_SET 0x4C8A898970 971#define mmPDMA0_QM_CP_SWITCH_WD 0x4C8A89C972 973#define mmPDMA0_QM_ARC_LB_ADDR_BASE_LO 0x4C8A8A4974 975#define mmPDMA0_QM_ARC_LB_ADDR_BASE_HI 0x4C8A8A8976 977#define mmPDMA0_QM_ENGINE_BASE_ADDR_HI 0x4C8A8AC978 979#define mmPDMA0_QM_ENGINE_BASE_ADDR_LO 0x4C8A8B0980 981#define mmPDMA0_QM_ENGINE_ADDR_RANGE_SIZE 0x4C8A8B4982 983#define mmPDMA0_QM_QM_ARC_AUX_BASE_ADDR_HI 0x4C8A8B8984 985#define mmPDMA0_QM_QM_ARC_AUX_BASE_ADDR_LO 0x4C8A8BC986 987#define mmPDMA0_QM_QM_BASE_ADDR_HI 0x4C8A8C0988 989#define mmPDMA0_QM_QM_BASE_ADDR_LO 0x4C8A8C4990 991#define mmPDMA0_QM_ARC_PQC_SECURE_PUSH_IND 0x4C8A8C8992 993#define mmPDMA0_QM_PQC_STS_0_0 0x4C8A8D0994 995#define mmPDMA0_QM_PQC_STS_0_1 0x4C8A8D4996 997#define mmPDMA0_QM_PQC_STS_0_2 0x4C8A8D8998 999#define mmPDMA0_QM_PQC_STS_0_3 0x4C8A8DC1000 1001#define mmPDMA0_QM_PQC_STS_1_0 0x4C8A8E01002 1003#define mmPDMA0_QM_PQC_STS_1_1 0x4C8A8E41004 1005#define mmPDMA0_QM_PQC_STS_1_2 0x4C8A8E81006 1007#define mmPDMA0_QM_PQC_STS_1_3 0x4C8A8EC1008 1009#define mmPDMA0_QM_SEI_STATUS 0x4C8A8F01010 1011#define mmPDMA0_QM_SEI_MASK 0x4C8A8F41012 1013#define mmPDMA0_QM_GLBL_ERR_ADDR_LO 0x4C8AD001014 1015#define mmPDMA0_QM_GLBL_ERR_ADDR_HI 0x4C8AD041016 1017#define mmPDMA0_QM_GLBL_ERR_WDATA 0x4C8AD081018 1019#define mmPDMA0_QM_L2H_MASK_LO 0x4C8AD141020 1021#define mmPDMA0_QM_L2H_MASK_HI 0x4C8AD181022 1023#define mmPDMA0_QM_L2H_CMPR_LO 0x4C8AD1C1024 1025#define mmPDMA0_QM_L2H_CMPR_HI 0x4C8AD201026 1027#define mmPDMA0_QM_LOCAL_RANGE_BASE 0x4C8AD241028 1029#define mmPDMA0_QM_LOCAL_RANGE_SIZE 0x4C8AD281030 1031#define mmPDMA0_QM_HBW_RD_RATE_LIM_CFG_1 0x4C8AD301032 1033#define mmPDMA0_QM_LBW_WR_RATE_LIM_CFG_0 0x4C8AD341034 1035#define mmPDMA0_QM_LBW_WR_RATE_LIM_CFG_1 0x4C8AD381036 1037#define mmPDMA0_QM_HBW_RD_RATE_LIM_CFG_0 0x4C8AD3C1038 1039#define mmPDMA0_QM_IND_GW_APB_CFG 0x4C8AD401040 1041#define mmPDMA0_QM_IND_GW_APB_WDATA 0x4C8AD441042 1043#define mmPDMA0_QM_IND_GW_APB_RDATA 0x4C8AD481044 1045#define mmPDMA0_QM_IND_GW_APB_STATUS 0x4C8AD4C1046 1047#define mmPDMA0_QM_PERF_CNT_FREE_LO 0x4C8AD601048 1049#define mmPDMA0_QM_PERF_CNT_FREE_HI 0x4C8AD641050 1051#define mmPDMA0_QM_PERF_CNT_IDLE_LO 0x4C8AD681052 1053#define mmPDMA0_QM_PERF_CNT_IDLE_HI 0x4C8AD6C1054 1055#define mmPDMA0_QM_PERF_CNT_CFG 0x4C8AD701056 1057#endif /* ASIC_REG_PDMA0_QM_REGS_H_ */1058