136 lines · c
1/* SPDX-License-Identifier: GPL-2.02 *3 * Copyright 2016-2020 HabanaLabs, Ltd.4 * All Rights Reserved.5 *6 */7 8/************************************9 ** This is an auto-generated file **10 ** DO NOT EDIT BELOW **11 ************************************/12 13#ifndef ASIC_REG_PMMU_PIF_REGS_H_14#define ASIC_REG_PMMU_PIF_REGS_H_15 16/*17 *****************************************18 * PMMU_PIF19 * (Prototype: PIF)20 *****************************************21 */22 23#define mmPMMU_PIF_WR_CORE_CREDITS_THRESHOLD 0x4D0300024 25#define mmPMMU_PIF_RD_CORE_CREDITS_THRESHOLD 0x4D0300426 27#define mmPMMU_PIF_CORE_CREDITS_THRESHOLD 0x4D0300828 29#define mmPMMU_PIF_CORE_SEPARATION_DISABLE 0x4D0300C30 31#define mmPMMU_PIF_DISABLE_E2E_CREDITS 0x4D0301032 33#define mmPMMU_PIF_RATE_LIMITER_ENABLE 0x4D0301434 35#define mmPMMU_PIF_RATE_LIMITER_TOKEN_RESET 0x4D0301836 37#define mmPMMU_PIF_RATE_LIMITER_SATURATION 0x4D0301C38 39#define mmPMMU_PIF_RATE_LIMITER_TIMEOUT_LSB 0x4D0302040 41#define mmPMMU_PIF_RATE_LIMITER_TIMEOUT_MSB 0x4D0302442 43#define mmPMMU_PIF_ARB_TYPE 0x4D0302844 45#define mmPMMU_PIF_CLOCK_GATE_CONFIG 0x4D0302C46 47#define mmPMMU_PIF_CLOCK_GATE_ACTIVE 0x4D0303048 49#define mmPMMU_PIF_SPI_INTERRUPT_CAUSE 0x4D0303450 51#define mmPMMU_PIF_SPI_INTERRUPT_CAUSE_MASK 0x4D0303852 53#define mmPMMU_PIF_SPI_INTERRUPT_REG 0x4D0303C54 55#define mmPMMU_PIF_SPI_INTERRUPT_MASK 0x4D0304056 57#define mmPMMU_PIF_SEI_INTERRUPT_CAUSE 0x4D0304458 59#define mmPMMU_PIF_SEI_INTERRUPT_CAUSE_MASK 0x4D0304860 61#define mmPMMU_PIF_SEI_INTERRUPT_REG 0x4D0304C62 63#define mmPMMU_PIF_SEI_INTERRUPT_MASK 0x4D0305064 65#define mmPMMU_PIF_DEBUG_BUFFER_CNT_CTRL 0x4D0305466 67#define mmPMMU_PIF_DEBUG_WR_BUF_CNT 0x4D0305868 69#define mmPMMU_PIF_DEBUG_RD_BUF_CNT 0x4D0305C70 71#define mmPMMU_PIF_DEBUG_WR_CORE_BUF_CNT 0x4D0306072 73#define mmPMMU_PIF_DEBUG_RD_CORE_BUF_CNT 0x4D0307074 75#define mmPMMU_PIF_DEBUG_WR_BUF_FULL 0x4D0308076 77#define mmPMMU_PIF_DEBUG_RD_BUF_FULL 0x4D0308478 79#define mmPMMU_PIF_E2E_ROUTING_CFG 0x4D0309080 81#define mmPMMU_PIF_E2E_ROUTING_CFG2 0x4D0309482 83#define mmPMMU_PIF_SPI_INTERRUPT_CLEAR 0x4D0310084 85#define mmPMMU_PIF_SEI_INTERRUPT_CLEAR 0x4D0310486 87#define mmPMMU_PIF_BASE_ADDR_PMMU 0x4D0320088 89#define mmPMMU_PIF_ADDR_MASK_PMMU 0x4D0320490 91#define mmPMMU_PIF_BASE_ADDR_PCI0 0x4D0320892 93#define mmPMMU_PIF_ADDR_MASK_PCI0 0x4D0320C94 95#define mmPMMU_PIF_BASE_ADDR_PCI2 0x4D0321096 97#define mmPMMU_PIF_ADDR_MASK_PCI1 0x4D0321498 99#define mmPMMU_PIF_BASE_ADDR_PCI1 0x4D03218100 101#define mmPMMU_PIF_ADDR_MASK_PCI2 0x4D0321C102 103#define mmPMMU_PIF_BASE_ADDR_TPC 0x4D03220104 105#define mmPMMU_PIF_ADDR_MASK_TPC 0x4D03224106 107#define mmPMMU_PIF_BASE_ADDR_DEC0 0x4D03228108 109#define mmPMMU_PIF_ADDR_MASK_DEC0 0x4D0322C110 111#define mmPMMU_PIF_BASE_ADDR_DEC1 0x4D03230112 113#define mmPMMU_PIF_ADDR_MASK_DEC1 0x4D03234114 115#define mmPMMU_PIF_PMMU_DBG_BASE_ADDR 0x4D03300116 117#define mmPMMU_PIF_PMMU_DBG_ADDR_MASK 0x4D03304118 119#define mmPMMU_PIF_PCI_DBG_BASE_ADDR 0x4D03308120 121#define mmPMMU_PIF_PCI_DBG_ADDR_MASK 0x4D0330C122 123#define mmPMMU_PIF_DEC0_DBG_BASE_ADDR 0x4D03310124 125#define mmPMMU_PIF_DEC0_DBG_ADDR_MASK 0x4D03314126 127#define mmPMMU_PIF_DEC1_DBG_BASE_ADDR 0x4D03318128 129#define mmPMMU_PIF_DEC1_DBG_ADDR_MASK 0x4D0331C130 131#define mmPMMU_PIF_TPC_DBG_BASE_ADDR 0x4D03320132 133#define mmPMMU_PIF_TPC_DBG_ADDR_MASK 0x4D03324134 135#endif /* ASIC_REG_PMMU_PIF_REGS_H_ */136