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1/* SPDX-License-Identifier: GPL-2.02 *3 * Copyright 2016-2020 HabanaLabs, Ltd.4 * All Rights Reserved.5 *6 */7 8/************************************9 ** This is an auto-generated file **10 ** DO NOT EDIT BELOW **11 ************************************/12 13#ifndef ASIC_REG_ROT0_MASKS_H_14#define ASIC_REG_ROT0_MASKS_H_15 16/*17 *****************************************18 * ROT019 * (Prototype: ROTATOR)20 *****************************************21 */22 23/* ROT0_KMD_MODE */24#define ROT0_KMD_MODE_EN_SHIFT 025#define ROT0_KMD_MODE_EN_MASK 0x126 27/* ROT0_CPL_QUEUE_EN */28#define ROT0_CPL_QUEUE_EN_Q_EN_SHIFT 029#define ROT0_CPL_QUEUE_EN_Q_EN_MASK 0x130 31/* ROT0_CPL_QUEUE_ADDR_L */32#define ROT0_CPL_QUEUE_ADDR_L_VAL_SHIFT 033#define ROT0_CPL_QUEUE_ADDR_L_VAL_MASK 0xFFFFFFFF34 35/* ROT0_CPL_QUEUE_ADDR_H */36#define ROT0_CPL_QUEUE_ADDR_H_VAL_SHIFT 037#define ROT0_CPL_QUEUE_ADDR_H_VAL_MASK 0xFFFFFFFF38 39/* ROT0_CPL_QUEUE_DATA */40#define ROT0_CPL_QUEUE_DATA_VAL_SHIFT 041#define ROT0_CPL_QUEUE_DATA_VAL_MASK 0xFFFFFFFF42 43/* ROT0_CPL_QUEUE_AWUSER */44#define ROT0_CPL_QUEUE_AWUSER_VAL_SHIFT 045#define ROT0_CPL_QUEUE_AWUSER_VAL_MASK 0xFFFFFFFF46 47/* ROT0_CPL_QUEUE_AXI */48#define ROT0_CPL_QUEUE_AXI_CACHE_SHIFT 049#define ROT0_CPL_QUEUE_AXI_CACHE_MASK 0xF50#define ROT0_CPL_QUEUE_AXI_PROT_SHIFT 451#define ROT0_CPL_QUEUE_AXI_PROT_MASK 0x7052 53/* ROT0_CPL_MSG_THRESHOLD */54#define ROT0_CPL_MSG_THRESHOLD_VAL_SHIFT 055#define ROT0_CPL_MSG_THRESHOLD_VAL_MASK 0x3F56 57/* ROT0_CPL_MSG_AXI */58#define ROT0_CPL_MSG_AXI_CACHE_SHIFT 059#define ROT0_CPL_MSG_AXI_CACHE_MASK 0xF60#define ROT0_CPL_MSG_AXI_PROT_SHIFT 461#define ROT0_CPL_MSG_AXI_PROT_MASK 0x7062 63/* ROT0_AXI_WB */64#define ROT0_AXI_WB_CACHE_SHIFT 065#define ROT0_AXI_WB_CACHE_MASK 0xF66#define ROT0_AXI_WB_PROT_SHIFT 467#define ROT0_AXI_WB_PROT_MASK 0x7068 69/* ROT0_ERR_CFG */70#define ROT0_ERR_CFG_STOP_ON_ERR_SHIFT 071#define ROT0_ERR_CFG_STOP_ON_ERR_MASK 0x172 73/* ROT0_ERR_STATUS */74#define ROT0_ERR_STATUS_ROT_HBW_RD_SHIFT 075#define ROT0_ERR_STATUS_ROT_HBW_RD_MASK 0x176#define ROT0_ERR_STATUS_ROT_HBW_WR_SHIFT 177#define ROT0_ERR_STATUS_ROT_HBW_WR_MASK 0x278#define ROT0_ERR_STATUS_QMAN_HBW_RD_SHIFT 279#define ROT0_ERR_STATUS_QMAN_HBW_RD_MASK 0x480#define ROT0_ERR_STATUS_QMAN_HBW_WR_SHIFT 381#define ROT0_ERR_STATUS_QMAN_HBW_WR_MASK 0x882#define ROT0_ERR_STATUS_ROT_LBW_WR_SHIFT 483#define ROT0_ERR_STATUS_ROT_LBW_WR_MASK 0x1084 85/* ROT0_WBC_MAX_OUTSTANDING */86#define ROT0_WBC_MAX_OUTSTANDING_VAL_SHIFT 087#define ROT0_WBC_MAX_OUTSTANDING_VAL_MASK 0xFFFF88 89/* ROT0_WBC_RL */90#define ROT0_WBC_RL_SATURATION_SHIFT 091#define ROT0_WBC_RL_SATURATION_MASK 0xFF92#define ROT0_WBC_RL_TIMEOUT_SHIFT 893#define ROT0_WBC_RL_TIMEOUT_MASK 0xFF0094#define ROT0_WBC_RL_RST_TOKEN_SHIFT 1695#define ROT0_WBC_RL_RST_TOKEN_MASK 0xFF000096#define ROT0_WBC_RL_RATE_LIMITER_EN_SHIFT 2497#define ROT0_WBC_RL_RATE_LIMITER_EN_MASK 0x100000098 99/* ROT0_WBC_INFLIGHTS */100#define ROT0_WBC_INFLIGHTS_VAL_SHIFT 0101#define ROT0_WBC_INFLIGHTS_VAL_MASK 0xFFFF102 103/* ROT0_WBC_INFO */104#define ROT0_WBC_INFO_EMPTY_SHIFT 0105#define ROT0_WBC_INFO_EMPTY_MASK 0x1106#define ROT0_WBC_INFO_AXI_IDLE_SHIFT 1107#define ROT0_WBC_INFO_AXI_IDLE_MASK 0x2108 109/* ROT0_WBC_MON */110#define ROT0_WBC_MON_CNT_SHIFT 0111#define ROT0_WBC_MON_CNT_MASK 0x1112#define ROT0_WBC_MON_TS_SHIFT 8113#define ROT0_WBC_MON_TS_MASK 0x300114#define ROT0_WBC_MON_CONTEXT_ID_SHIFT 16115#define ROT0_WBC_MON_CONTEXT_ID_MASK 0xFFFF0000116 117/* ROT0_RSB_CAM_MAX_SIZE */118#define ROT0_RSB_CAM_MAX_SIZE_DATA_SHIFT 0119#define ROT0_RSB_CAM_MAX_SIZE_DATA_MASK 0xFFFF120#define ROT0_RSB_CAM_MAX_SIZE_MD_SHIFT 16121#define ROT0_RSB_CAM_MAX_SIZE_MD_MASK 0xFFFF0000122 123/* ROT0_RSB_CFG */124#define ROT0_RSB_CFG_CACHE_DISABLE_SHIFT 0125#define ROT0_RSB_CFG_CACHE_DISABLE_MASK 0x1126#define ROT0_RSB_CFG_ENABLE_CGATE_SHIFT 1127#define ROT0_RSB_CFG_ENABLE_CGATE_MASK 0x2128 129/* ROT0_RSB_MAX_OS */130#define ROT0_RSB_MAX_OS_VAL_SHIFT 0131#define ROT0_RSB_MAX_OS_VAL_MASK 0xFFFF132 133/* ROT0_RSB_RL */134#define ROT0_RSB_RL_SATURATION_SHIFT 0135#define ROT0_RSB_RL_SATURATION_MASK 0xFF136#define ROT0_RSB_RL_TIMEOUT_SHIFT 8137#define ROT0_RSB_RL_TIMEOUT_MASK 0xFF00138#define ROT0_RSB_RL_RST_TOKEN_SHIFT 16139#define ROT0_RSB_RL_RST_TOKEN_MASK 0xFF0000140#define ROT0_RSB_RL_RATE_LIMITER_EN_SHIFT 24141#define ROT0_RSB_RL_RATE_LIMITER_EN_MASK 0x1000000142 143/* ROT0_RSB_INFLIGHTS */144#define ROT0_RSB_INFLIGHTS_VAL_SHIFT 0145#define ROT0_RSB_INFLIGHTS_VAL_MASK 0xFFFFFFFF146 147/* ROT0_RSB_OCCUPANCY */148#define ROT0_RSB_OCCUPANCY_VAL_SHIFT 0149#define ROT0_RSB_OCCUPANCY_VAL_MASK 0xFFFFFFFF150 151/* ROT0_RSB_INFO */152#define ROT0_RSB_INFO_EMPTY_SHIFT 0153#define ROT0_RSB_INFO_EMPTY_MASK 0x1154#define ROT0_RSB_INFO_AXI_IDLE_SHIFT 1155#define ROT0_RSB_INFO_AXI_IDLE_MASK 0x2156 157/* ROT0_RSB_MON */158#define ROT0_RSB_MON_CNT_SHIFT 0159#define ROT0_RSB_MON_CNT_MASK 0x1FFF160#define ROT0_RSB_MON_TS_SHIFT 16161#define ROT0_RSB_MON_TS_MASK 0x30000162 163/* ROT0_RSB_MON_CONTEXT_ID */164#define ROT0_RSB_MON_CONTEXT_ID_VAL_SHIFT 0165#define ROT0_RSB_MON_CONTEXT_ID_VAL_MASK 0xFFFFFFFF166 167/* ROT0_MSS_HALT */168#define ROT0_MSS_HALT_VAL_SHIFT 0169#define ROT0_MSS_HALT_VAL_MASK 0x7170 171/* ROT0_MSS_SEI_STATUS */172#define ROT0_MSS_SEI_STATUS_I0_SHIFT 0173#define ROT0_MSS_SEI_STATUS_I0_MASK 0x1174#define ROT0_MSS_SEI_STATUS_I1_SHIFT 1175#define ROT0_MSS_SEI_STATUS_I1_MASK 0x2176#define ROT0_MSS_SEI_STATUS_I2_SHIFT 2177#define ROT0_MSS_SEI_STATUS_I2_MASK 0x4178#define ROT0_MSS_SEI_STATUS_I3_SHIFT 3179#define ROT0_MSS_SEI_STATUS_I3_MASK 0x8180#define ROT0_MSS_SEI_STATUS_I4_SHIFT 4181#define ROT0_MSS_SEI_STATUS_I4_MASK 0x10182#define ROT0_MSS_SEI_STATUS_I5_SHIFT 5183#define ROT0_MSS_SEI_STATUS_I5_MASK 0x20184#define ROT0_MSS_SEI_STATUS_I6_SHIFT 6185#define ROT0_MSS_SEI_STATUS_I6_MASK 0x40186#define ROT0_MSS_SEI_STATUS_I7_SHIFT 7187#define ROT0_MSS_SEI_STATUS_I7_MASK 0x80188#define ROT0_MSS_SEI_STATUS_I8_SHIFT 8189#define ROT0_MSS_SEI_STATUS_I8_MASK 0x100190#define ROT0_MSS_SEI_STATUS_I9_SHIFT 9191#define ROT0_MSS_SEI_STATUS_I9_MASK 0x200192#define ROT0_MSS_SEI_STATUS_I10_SHIFT 10193#define ROT0_MSS_SEI_STATUS_I10_MASK 0x400194#define ROT0_MSS_SEI_STATUS_I11_SHIFT 11195#define ROT0_MSS_SEI_STATUS_I11_MASK 0x800196#define ROT0_MSS_SEI_STATUS_I12_SHIFT 12197#define ROT0_MSS_SEI_STATUS_I12_MASK 0x1000198#define ROT0_MSS_SEI_STATUS_I13_SHIFT 13199#define ROT0_MSS_SEI_STATUS_I13_MASK 0x2000200#define ROT0_MSS_SEI_STATUS_I14_SHIFT 14201#define ROT0_MSS_SEI_STATUS_I14_MASK 0x4000202#define ROT0_MSS_SEI_STATUS_I15_SHIFT 15203#define ROT0_MSS_SEI_STATUS_I15_MASK 0x8000204#define ROT0_MSS_SEI_STATUS_I16_SHIFT 16205#define ROT0_MSS_SEI_STATUS_I16_MASK 0x10000206#define ROT0_MSS_SEI_STATUS_I17_SHIFT 17207#define ROT0_MSS_SEI_STATUS_I17_MASK 0x20000208#define ROT0_MSS_SEI_STATUS_I18_SHIFT 18209#define ROT0_MSS_SEI_STATUS_I18_MASK 0x40000210#define ROT0_MSS_SEI_STATUS_I19_SHIFT 19211#define ROT0_MSS_SEI_STATUS_I19_MASK 0x80000212#define ROT0_MSS_SEI_STATUS_I20_SHIFT 20213#define ROT0_MSS_SEI_STATUS_I20_MASK 0x100000214#define ROT0_MSS_SEI_STATUS_I21_SHIFT 21215#define ROT0_MSS_SEI_STATUS_I21_MASK 0x200000216 217/* ROT0_MSS_SEI_MASK */218#define ROT0_MSS_SEI_MASK_VAL_SHIFT 0219#define ROT0_MSS_SEI_MASK_VAL_MASK 0x3FFFFF220 221/* ROT0_MSS_SPI_STATUS */222#define ROT0_MSS_SPI_STATUS_I0_SHIFT 0223#define ROT0_MSS_SPI_STATUS_I0_MASK 0x1224#define ROT0_MSS_SPI_STATUS_I1_SHIFT 1225#define ROT0_MSS_SPI_STATUS_I1_MASK 0x2226#define ROT0_MSS_SPI_STATUS_I2_SHIFT 2227#define ROT0_MSS_SPI_STATUS_I2_MASK 0x4228#define ROT0_MSS_SPI_STATUS_I3_SHIFT 3229#define ROT0_MSS_SPI_STATUS_I3_MASK 0x8230#define ROT0_MSS_SPI_STATUS_I4_SHIFT 4231#define ROT0_MSS_SPI_STATUS_I4_MASK 0x10232#define ROT0_MSS_SPI_STATUS_I5_SHIFT 5233#define ROT0_MSS_SPI_STATUS_I5_MASK 0x20234#define ROT0_MSS_SPI_STATUS_I6_SHIFT 6235#define ROT0_MSS_SPI_STATUS_I6_MASK 0x40236#define ROT0_MSS_SPI_STATUS_I7_SHIFT 7237#define ROT0_MSS_SPI_STATUS_I7_MASK 0x80238 239/* ROT0_MSS_SPI_MASK */240#define ROT0_MSS_SPI_MASK_VAL_SHIFT 0241#define ROT0_MSS_SPI_MASK_VAL_MASK 0xFF242 243/* ROT0_DISABLE_PAD_CALC */244#define ROT0_DISABLE_PAD_CALC_VAL_SHIFT 0245#define ROT0_DISABLE_PAD_CALC_VAL_MASK 0x3246 247/* ROT0_QMAN_CFG */248#define ROT0_QMAN_CFG_FORCE_STOP_SHIFT 0249#define ROT0_QMAN_CFG_FORCE_STOP_MASK 0x1250 251/* ROT0_CLK_EN */252#define ROT0_CLK_EN_LBW_CFG_DIS_SHIFT 0253#define ROT0_CLK_EN_LBW_CFG_DIS_MASK 0x1254#define ROT0_CLK_EN_DBG_CFG_DIS_SHIFT 4255#define ROT0_CLK_EN_DBG_CFG_DIS_MASK 0x10256#define ROT0_CLK_EN_SB_EMPTY_MASK_SHIFT 5257#define ROT0_CLK_EN_SB_EMPTY_MASK_MASK 0x20258 259/* ROT0_MRSB_CAM_MAX_SIZE */260#define ROT0_MRSB_CAM_MAX_SIZE_DATA_SHIFT 0261#define ROT0_MRSB_CAM_MAX_SIZE_DATA_MASK 0xFFFF262#define ROT0_MRSB_CAM_MAX_SIZE_MD_SHIFT 16263#define ROT0_MRSB_CAM_MAX_SIZE_MD_MASK 0xFFFF0000264 265/* ROT0_MRSB_CFG */266#define ROT0_MRSB_CFG_CACHE_DISABLE_SHIFT 0267#define ROT0_MRSB_CFG_CACHE_DISABLE_MASK 0x1268#define ROT0_MRSB_CFG_ENABLE_CGATE_SHIFT 1269#define ROT0_MRSB_CFG_ENABLE_CGATE_MASK 0x2270 271/* ROT0_MRSB_MAX_OS */272#define ROT0_MRSB_MAX_OS_VAL_SHIFT 0273#define ROT0_MRSB_MAX_OS_VAL_MASK 0xFFFF274 275/* ROT0_MRSB_RL */276#define ROT0_MRSB_RL_SATURATION_SHIFT 0277#define ROT0_MRSB_RL_SATURATION_MASK 0xFF278#define ROT0_MRSB_RL_TIMEOUT_SHIFT 8279#define ROT0_MRSB_RL_TIMEOUT_MASK 0xFF00280#define ROT0_MRSB_RL_RST_TOKEN_SHIFT 16281#define ROT0_MRSB_RL_RST_TOKEN_MASK 0xFF0000282#define ROT0_MRSB_RL_RATE_LIMITER_EN_SHIFT 24283#define ROT0_MRSB_RL_RATE_LIMITER_EN_MASK 0x1000000284 285/* ROT0_MRSB_INFLIGHTS */286#define ROT0_MRSB_INFLIGHTS_VAL_SHIFT 0287#define ROT0_MRSB_INFLIGHTS_VAL_MASK 0xFFFFFFFF288 289/* ROT0_MRSB_OCCUPANCY */290#define ROT0_MRSB_OCCUPANCY_VAL_SHIFT 0291#define ROT0_MRSB_OCCUPANCY_VAL_MASK 0xFFFFFFFF292 293/* ROT0_MRSB_INFO */294#define ROT0_MRSB_INFO_EMPTY_SHIFT 0295#define ROT0_MRSB_INFO_EMPTY_MASK 0x1296#define ROT0_MRSB_INFO_AXI_IDLE_SHIFT 1297#define ROT0_MRSB_INFO_AXI_IDLE_MASK 0x2298 299/* ROT0_MRSB_MON */300#define ROT0_MRSB_MON_CNT_SHIFT 0301#define ROT0_MRSB_MON_CNT_MASK 0x1FFF302#define ROT0_MRSB_MON_TS_SHIFT 16303#define ROT0_MRSB_MON_TS_MASK 0x30000304 305/* ROT0_MRSB_MON_CONTEXT_ID */306#define ROT0_MRSB_MON_CONTEXT_ID_VAL_SHIFT 0307#define ROT0_MRSB_MON_CONTEXT_ID_VAL_MASK 0xFFFFFFFF308 309/* ROT0_MSS_STS */310#define ROT0_MSS_STS_IS_HALT_SHIFT 0311#define ROT0_MSS_STS_IS_HALT_MASK 0x1312 313#endif /* ASIC_REG_ROT0_MASKS_H_ */314