126 lines · c
1/* SPDX-License-Identifier: GPL-2.02 *3 * Copyright 2020-2022 HabanaLabs, Ltd.4 * All Rights Reserved.5 *6 */7 8#ifndef GAUDI2_H9#define GAUDI2_H10 11#define SRAM_CFG_BAR_ID 012#define MSIX_BAR_ID 213#define DRAM_BAR_ID 414 15/* Refers to CFG_REGION_SIZE, BAR0_RSRVD_SIZE and SRAM_SIZE */16#define CFG_BAR_SIZE 0x10000000ull /* 256MB */17 18#define MSIX_BAR_SIZE 0x4000ull /* 16KB */19 20#define CFG_BASE 0x1000007FF8000000ull21#define CFG_SIZE 0x8000000ull /* 96MB CFG + 32MB DBG*/22#define CFG_REGION_SIZE 0xC000000ull /* 192MB */23 24#define STM_FLASH_BASE_ADDR 0x1000007FF4000000ull /* Not 256MB aligned */25#define STM_FLASH_ALIGNED_OFF 0x4000000ull /* 256 MB alignment */26#define STM_FLASH_SIZE 0x2000000ull /* 32MB */27 28#define SPI_FLASH_BASE_ADDR 0x1000007FF6000000ull29#define SPI_FLASH_SIZE 0x1000000ull /* 16MB */30 31#define SCRATCHPAD_SRAM_ADDR 0x1000007FF7FE0000ull32#define SCRATCHPAD_SRAM_SIZE 0x10000ull /* 64KB */33 34#define PCIE_FW_SRAM_ADDR 0x1000007FF7FF0000ull35#define PCIE_FW_SRAM_SIZE 0x8000 /* 32KB */36 37#define BAR0_RSRVD_BASE_ADDR 0x1000FFFFFC000000ull38#define BAR0_RSRVD_SIZE 0x1000000ull /* 16MB */39 40#define SRAM_BASE_ADDR 0x1000FFFFFD000000ull41#define SRAM_SIZE 0x3000000ull /* 48MB */42 43#define DRAM_PHYS_BASE 0x1001000000000000ull44 45/* every hint address is masked accordingly */46#define DRAM_VA_HINT_MASK 0xFFFFFFFFFFFFull /* 48bit mask */47 48#define HOST_PHYS_BASE_0 0x0000000000000000ull49#define HOST_PHYS_SIZE_0 0x0100000000000000ull /* 64PB (56 bits) */50 51#define HOST_PHYS_BASE_1 0xFF00000000000000ull52#define HOST_PHYS_SIZE_1 0x0100000000000000ull /* 64PB (56 bits) */53 54#define RESERVED_VA_RANGE_FOR_ARC_ON_HBM_START 0x1001500000000000ull55#define RESERVED_VA_RANGE_FOR_ARC_ON_HBM_END 0x10016FFFFFFFFFFFull56 57#define RESERVED_VA_FOR_VIRTUAL_MSIX_DOORBELL_START 0xFFF077FFFFFF0000ull58#define RESERVED_VA_FOR_VIRTUAL_MSIX_DOORBELL_END 0xFFF077FFFFFFFFFFull59 60#define RESERVED_VA_RANGE_FOR_ARC_ON_HOST_START 0xFFF0780000000000ull61#define RESERVED_VA_RANGE_FOR_ARC_ON_HOST_END 0xFFF07FFFFFFFFFFFull62 63#define RESERVED_VA_RANGE_FOR_ARC_ON_HOST_HPAGE_START 0xFFF0F80000000000ull64#define RESERVED_VA_RANGE_FOR_ARC_ON_HOST_HPAGE_END 0xFFF0FFFFFFFFFFFFull65 66#define RESERVED_MSIX_UNEXPECTED_USER_ERROR_INTERRUPT 12767 68#define GAUDI2_MSIX_ENTRIES 12869 70#define QMAN_PQ_ENTRY_SIZE 16 /* Bytes */71 72#define MAX_ASID 273 74#define NUM_ARC_CPUS 6975 76/* Every ARC cpu in the system contains a single DCCM block77 * except MME and Scheduler ARCs which contain 2 DCCM blocks78 */79#define ARC_DCCM_BLOCK_SIZE 0x800080 81#define NUM_OF_DCORES 482#define NUM_OF_SFT 483#define NUM_OF_PSOC_ARC 284#define NUM_OF_SCHEDULER_ARC 685 86#define NUM_OF_PQ_PER_QMAN 487#define NUM_OF_CQ_PER_QMAN 588#define NUM_OF_CP_PER_QMAN 589#define NUM_OF_EDMA_PER_DCORE 290#define NUM_OF_HIF_PER_DCORE 491#define NUM_OF_PDMA 292#define NUM_OF_TPC_PER_DCORE 693#define NUM_DCORE0_TPC 794#define NUM_DCORE1_TPC NUM_OF_TPC_PER_DCORE95#define NUM_DCORE2_TPC NUM_OF_TPC_PER_DCORE96#define NUM_DCORE3_TPC NUM_OF_TPC_PER_DCORE97#define NUM_OF_DEC_PER_DCORE 298#define NUM_OF_ROT 299#define NUM_OF_HMMU_PER_DCORE 4100#define NUM_OF_MME_PER_DCORE 1101#define NUM_OF_MME_SBTE_PER_DCORE 5102#define NUM_OF_MME_WB_PER_DCORE 2103#define NUM_OF_RTR_PER_DCORE 8104#define NUM_OF_VDEC_PER_DCORE 2105#define NUM_OF_IF_RTR_PER_SFT 3106#define NUM_OF_PCIE_VDEC 2107#define NUM_OF_ARC_FARMS_ARC 4108#define NUM_OF_XBAR 4109 110#define TPC_NUM_OF_KERNEL_TENSORS 16111#define TPC_NUM_OF_QM_TENSORS 16112 113#define MME_NUM_OF_LFSR_SEEDS 256114 115#define NIC_NUMBER_OF_MACROS 12116 117#define NIC_NUMBER_OF_QM_PER_MACRO 2118 119#define NIC_NUMBER_OF_ENGINES (NIC_NUMBER_OF_MACROS * 2)120 121#define NIC_MAX_NUMBER_OF_PORTS (NIC_NUMBER_OF_ENGINES * 2)122 123#define DEVICE_CACHE_LINE_SIZE 128124 125#endif /* GAUDI2_H */126