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1/* SPDX-License-Identifier: GPL-2.02 *3 * Copyright 2019-2021 HabanaLabs, Ltd.4 * All Rights Reserved.5 *6 */7 8#ifndef GAUDI2_FW_IF_H9#define GAUDI2_FW_IF_H10 11#define GAUDI2_EVENT_QUEUE_MSIX_IDX 012 13#define UBOOT_FW_OFFSET 0x100000 /* 1MB in SRAM */14#define LINUX_FW_OFFSET 0x800000 /* 8BM in DDR */15 16#define GAUDI2_PLL_FREQ_LOW 200000000 /* 200 MHz */17 18#define GAUDI2_SP_SRAM_BASE_ADDR 0x27FE000019#define GAUDI2_MAILBOX_BASE_ADDR 0x27FE180020 21#define GAUDI2_NUM_MME 422 23#define NUM_OF_GPIOS_PER_PORT 1624#define GAUDI2_WD_GPIO (62 % NUM_OF_GPIOS_PER_PORT)25 26#define GAUDI2_ARCPID_TX_MB_SIZE 0x100027#define GAUDI2_ARCPID_RX_MB_SIZE 0x40028#define GAUDI2_ARM_TX_MB_SIZE 0x40029#define GAUDI2_ARM_RX_MB_SIZE 0x180030 31#define GAUDI2_DCCM_BASE_ADDR 0x2702000032 33#define GAUDI2_ARM_TX_MB_ADDR GAUDI2_MAILBOX_BASE_ADDR34 35#define GAUDI2_ARM_RX_MB_ADDR (GAUDI2_ARM_TX_MB_ADDR + \36 GAUDI2_ARM_TX_MB_SIZE)37 38#define GAUDI2_ARCPID_TX_MB_ADDR (GAUDI2_ARM_RX_MB_ADDR + GAUDI2_ARM_RX_MB_SIZE)39 40#define GAUDI2_ARCPID_RX_MB_ADDR (GAUDI2_ARCPID_TX_MB_ADDR + GAUDI2_ARCPID_TX_MB_SIZE)41 42#define GAUDI2_ARM_TX_MB_OFFSET (GAUDI2_ARM_TX_MB_ADDR - \43 GAUDI2_SP_SRAM_BASE_ADDR)44 45#define GAUDI2_ARM_RX_MB_OFFSET (GAUDI2_ARM_RX_MB_ADDR - \46 GAUDI2_SP_SRAM_BASE_ADDR)47 48#define POWER_MODE_LEVELS { \49 150000, /* 00 */ \50 250000, /* 01 */ \51 400000, /* 10 */ \52 /* 11: Normal mode */ \53}54 55enum gaudi2_fw_status {56 GAUDI2_PID_STATUS_UP = 0x1, /* PID on ARC0 is up */57 GAUDI2_ARM_STATUS_UP = 0x2, /* ARM Linux Boot complete */58 GAUDI2_MGMT_STATUS_UP = 0x3, /* ARC1 Mgmt is up */59 GAUDI2_STATUS_LAST = 0xFF60};61 62enum gaudi2_rst_src {63 HL_COLD_RST = 1,64 HL_MANUAL_RST = 2,65 HL_PRSTN_RST = 4,66 HL_SOFT_RST = 8,67 HL_WD_RST = 16,68 HL_FW_ALL_RST = 32,69 HL_SW_ALL_RST = 64,70 HL_FLR_RST = 128,71 HL_ECC_DERR_RST = 25672};73 74struct gaudi2_redundancy_ctx {75 __le32 redundant_hbm;76 __le32 redundant_edma;77 __le32 redundant_tpc;78 __le32 redundant_vdec;79 __le64 hbm_mask;80 __le64 edma_mask;81 __le64 tpc_mask;82 __le64 vdec_mask;83 __le64 mme_mask;84 __le64 nic_mask;85 __le64 rtr_mask;86 __le64 hmmu_hif_iso;87 __le64 xbar_edge_iso;88 __le64 hmmu_hif_mask;89 __le64 xbar_edge_mask;90 __u8 mme_pe_iso[GAUDI2_NUM_MME];91 __le32 full_hbm_mode; /* true on full (non binning hbm)*/92} __packed;93 94#endif /* GAUDI2_FW_IF_H */95