70 lines · c
1/* SPDX-License-Identifier: GPL-2.02 *3 * Copyright 2020 HabanaLabs, Ltd.4 * All Rights Reserved.5 *6 */7 8#ifndef GAUDI2_REG_MAP_H_9#define GAUDI2_REG_MAP_H_10 11/*12 * PSOC scratch-pad registers13 */14#define mmHW_STATE mmCPU_IF_KMD_HW_DIRTY_STATUS15#define mmPID_STATUS_REG mmPSOC_GLOBAL_CONF_SCRATCHPAD_116#define mmARM_STATUS_REG mmPSOC_GLOBAL_CONF_SCRATCHPAD_217#define mmGIC_TPC_QM_IRQ_CTRL_POLL_REG mmPSOC_GLOBAL_CONF_SCRATCHPAD_318#define mmGIC_MME_QM_IRQ_CTRL_POLL_REG mmPSOC_GLOBAL_CONF_SCRATCHPAD_419#define mmGIC_DMA_QM_IRQ_CTRL_POLL_REG mmPSOC_GLOBAL_CONF_SCRATCHPAD_520#define mmGIC_ROT_QM_IRQ_CTRL_POLL_REG mmPSOC_GLOBAL_CONF_SCRATCHPAD_621#define mmGIC_NIC_QM_IRQ_CTRL_POLL_REG mmPSOC_GLOBAL_CONF_SCRATCHPAD_722#define mmGIC_DMA_CR_IRQ_CTRL_POLL_REG mmPSOC_GLOBAL_CONF_SCRATCHPAD_823#define mmGIC_HOST_PI_UPD_IRQ_POLL_REG mmPSOC_GLOBAL_CONF_SCRATCHPAD_924#define mmGIC_HOST_HALT_IRQ_POLL_REG mmPSOC_GLOBAL_CONF_SCRATCHPAD_1025#define mmGIC_HOST_INTS_IRQ_POLL_REG mmPSOC_GLOBAL_CONF_SCRATCHPAD_1126#define mmGIC_HOST_SOFT_RST_IRQ_POLL_REG mmPSOC_GLOBAL_CONF_SCRATCHPAD_1227#define mmCPU_RST_STATUS_TO_HOST mmPSOC_GLOBAL_CONF_SCRATCHPAD_1428/*29 * Single scratchpad register used for all ARCs to notify dccm queue full event to FW.30 * So a new event would overwrite any unhandled previous event. In other words, incase31 * of multiple events before previous ones are handled, last one would be considered.32 */33#define mmENGINE_ARC_IRQ_CTRL_POLL_REG mmPSOC_GLOBAL_CONF_SCRATCHPAD_1534#define mmPID_CFG_REG mmPSOC_GLOBAL_CONF_SCRATCHPAD_1835#define mmGIC_RAZWI_STATUS_REG mmPSOC_GLOBAL_CONF_SCRATCHPAD_1936#define mmCPU_BOOT_DEV_STS0 mmPSOC_GLOBAL_CONF_SCRATCHPAD_2037#define mmCPU_BOOT_DEV_STS1 mmPSOC_GLOBAL_CONF_SCRATCHPAD_2138#define mmCPU_CMD_STATUS_TO_HOST mmPSOC_GLOBAL_CONF_SCRATCHPAD_2339#define mmCPU_BOOT_ERR0 mmPSOC_GLOBAL_CONF_SCRATCHPAD_2440#define mmCPU_BOOT_ERR1 mmPSOC_GLOBAL_CONF_SCRATCHPAD_2541#define mmUPD_STS mmPSOC_GLOBAL_CONF_SCRATCHPAD_2642#define mmUPD_CMD mmPSOC_GLOBAL_CONF_SCRATCHPAD_2743#define mmPPBOOT_VER_OFFSET mmPSOC_GLOBAL_CONF_SCRATCHPAD_2844#define mmRDWR_TEST mmPSOC_GLOBAL_CONF_SCRATCHPAD_3045#define mmBTL_ID mmPSOC_GLOBAL_CONF_SCRATCHPAD_3146#define mmRST_SRC mmPSOC_GLOBAL_CONF_COLD_RST_FLOPS_047#define mmCOLD_RST_DATA mmPSOC_GLOBAL_CONF_COLD_RST_FLOPS_248#define mmUPD_PENDING_STS mmPSOC_GLOBAL_CONF_COLD_RST_FLOPS_349#define mmPID_CMD_REQ_REG mmPSOC_PID_PID_CMD_050#define mmPID_CMD_REQ_REG_HI mmPSOC_PID_PID_CMD_151#define mmPID_CMD_RSP_REG mmPSOC_PID_PID_CMD_252#define mmPID_CMD_RSP_REG_HI mmPSOC_PID_PID_CMD_353#define mmPID_CMD_TELEMETRY_REG_0 mmPSOC_PID_PID_CMD_454#define mmPID_CMD_TELEMETRY_REG_0_HI mmPSOC_PID_PID_CMD_555#define mmPID_CMD_TELEMETRY_REG_1 mmPSOC_PID_PID_CMD_656#define mmPID_CMD_TELEMETRY_REG_1_HI mmPSOC_PID_PID_CMD_757#define mmWD_GPIO_OUTSET_REG mmPSOC_GPIO3_OUTENSET58#define mmWD_GPIO_DATAOUT_REG mmPSOC_GPIO3_DATAOUT59#define mmSTM_PROFILER_SPE_REG mmPSOC_STM_STMSPER60 61/* Registers below are used to pass the boot_if data between ARM and ARC1 */62#define mmARM_MSG_BOOT_ERR_SET mmCPU_IF_SPECIAL_GLBL_SPARE_063#define mmARM_MSG_BOOT_ERR_CLR mmCPU_IF_SPECIAL_GLBL_SPARE_164#define mmARM_MSG_BOOT_DEV_STS_SET mmCPU_IF_SPECIAL_GLBL_SPARE_265#define mmARM_MSG_BOOT_DEV_STS_CLR mmCPU_IF_SPECIAL_GLBL_SPARE_366#define mmMGMT_MSG_BOOT_ERR mmCPU_MSTR_IF_SPECIAL_GLBL_SPARE_067#define mmMGMT_MSG_BOOT_DEV_STS mmCPU_MSTR_IF_SPECIAL_GLBL_SPARE_168 69#endif /* GAUDI2_REG_MAP_H_ */70