279 lines · c
1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * Copyright (C) 2020-2024 Intel Corporation4 */5 6#ifndef __IVPU_DRV_H__7#define __IVPU_DRV_H__8 9#include <drm/drm_device.h>10#include <drm/drm_drv.h>11#include <drm/drm_managed.h>12#include <drm/drm_mm.h>13#include <drm/drm_print.h>14 15#include <linux/pci.h>16#include <linux/xarray.h>17#include <uapi/drm/ivpu_accel.h>18 19#include "ivpu_mmu_context.h"20#include "ivpu_ipc.h"21 22#define DRIVER_NAME "intel_vpu"23#define DRIVER_DESC "Driver for Intel NPU (Neural Processing Unit)"24#define DRIVER_DATE "20230117"25 26#define PCI_DEVICE_ID_MTL 0x7d1d27#define PCI_DEVICE_ID_ARL 0xad1d28#define PCI_DEVICE_ID_LNL 0x643e29 30#define IVPU_HW_IP_37XX 3731#define IVPU_HW_IP_40XX 4032#define IVPU_HW_IP_50XX 5033#define IVPU_HW_IP_60XX 6034 35#define IVPU_HW_IP_REV_LNL_B0 436 37#define IVPU_HW_BTRS_MTL 138#define IVPU_HW_BTRS_LNL 239 40#define IVPU_GLOBAL_CONTEXT_MMU_SSID 041/* SSID 1 is used by the VPU to represent reserved context */42#define IVPU_RESERVED_CONTEXT_MMU_SSID 143#define IVPU_USER_CONTEXT_MIN_SSID 244#define IVPU_USER_CONTEXT_MAX_SSID (IVPU_USER_CONTEXT_MIN_SSID + 63)45 46#define IVPU_MIN_DB 147#define IVPU_MAX_DB 25548 49#define IVPU_NUM_ENGINES 250#define IVPU_NUM_PRIORITIES 451#define IVPU_NUM_CMDQS_PER_CTX (IVPU_NUM_ENGINES * IVPU_NUM_PRIORITIES)52 53#define IVPU_CMDQ_INDEX(engine, priority) ((engine) * IVPU_NUM_PRIORITIES + (priority))54 55#define IVPU_PLATFORM_SILICON 056#define IVPU_PLATFORM_SIMICS 257#define IVPU_PLATFORM_FPGA 358#define IVPU_PLATFORM_INVALID 859 60#define IVPU_DBG_REG BIT(0)61#define IVPU_DBG_IRQ BIT(1)62#define IVPU_DBG_MMU BIT(2)63#define IVPU_DBG_FILE BIT(3)64#define IVPU_DBG_MISC BIT(4)65#define IVPU_DBG_FW_BOOT BIT(5)66#define IVPU_DBG_PM BIT(6)67#define IVPU_DBG_IPC BIT(7)68#define IVPU_DBG_BO BIT(8)69#define IVPU_DBG_JOB BIT(9)70#define IVPU_DBG_JSM BIT(10)71#define IVPU_DBG_KREF BIT(11)72#define IVPU_DBG_RPM BIT(12)73#define IVPU_DBG_MMU_MAP BIT(13)74 75#define ivpu_err(vdev, fmt, ...) \76 drm_err(&(vdev)->drm, "%s(): " fmt, __func__, ##__VA_ARGS__)77 78#define ivpu_err_ratelimited(vdev, fmt, ...) \79 drm_err_ratelimited(&(vdev)->drm, "%s(): " fmt, __func__, ##__VA_ARGS__)80 81#define ivpu_warn(vdev, fmt, ...) \82 drm_warn(&(vdev)->drm, "%s(): " fmt, __func__, ##__VA_ARGS__)83 84#define ivpu_warn_ratelimited(vdev, fmt, ...) \85 drm_err_ratelimited(&(vdev)->drm, "%s(): " fmt, __func__, ##__VA_ARGS__)86 87#define ivpu_info(vdev, fmt, ...) drm_info(&(vdev)->drm, fmt, ##__VA_ARGS__)88 89#define ivpu_dbg(vdev, type, fmt, args...) do { \90 if (unlikely(IVPU_DBG_##type & ivpu_dbg_mask)) \91 dev_dbg((vdev)->drm.dev, "[%s] " fmt, #type, ##args); \92} while (0)93 94#define IVPU_WA(wa_name) (vdev->wa.wa_name)95 96#define IVPU_PRINT_WA(wa_name) do { \97 if (IVPU_WA(wa_name)) \98 ivpu_dbg(vdev, MISC, "Using WA: " #wa_name "\n"); \99} while (0)100 101struct ivpu_wa_table {102 bool punit_disabled;103 bool clear_runtime_mem;104 bool interrupt_clear_with_0;105 bool disable_clock_relinquish;106 bool disable_d0i3_msg;107 bool wp0_during_power_up;108};109 110struct ivpu_hw_info;111struct ivpu_mmu_info;112struct ivpu_fw_info;113struct ivpu_ipc_info;114struct ivpu_pm_info;115 116struct ivpu_device {117 struct drm_device drm;118 void __iomem *regb;119 void __iomem *regv;120 u32 platform;121 u32 irq;122 123 struct ivpu_wa_table wa;124 struct ivpu_hw_info *hw;125 struct ivpu_mmu_info *mmu;126 struct ivpu_fw_info *fw;127 struct ivpu_ipc_info *ipc;128 struct ivpu_pm_info *pm;129 130 struct ivpu_mmu_context gctx;131 struct ivpu_mmu_context rctx;132 struct mutex context_list_lock; /* Protects user context addition/removal */133 struct xarray context_xa;134 struct xa_limit context_xa_limit;135 136 struct xarray db_xa;137 138 struct mutex bo_list_lock; /* Protects bo_list */139 struct list_head bo_list;140 141 struct xarray submitted_jobs_xa;142 struct ivpu_ipc_consumer job_done_consumer;143 144 atomic64_t unique_id_counter;145 146 ktime_t busy_start_ts;147 ktime_t busy_time;148 149 struct {150 int boot;151 int jsm;152 int tdr;153 int autosuspend;154 int d0i3_entry_msg;155 } timeout;156};157 158/*159 * file_priv has its own refcount (ref) that allows user space to close the fd160 * without blocking even if VPU is still processing some jobs.161 */162struct ivpu_file_priv {163 struct kref ref;164 struct ivpu_device *vdev;165 struct mutex lock; /* Protects cmdq */166 struct ivpu_cmdq *cmdq[IVPU_NUM_CMDQS_PER_CTX];167 struct ivpu_mmu_context ctx;168 struct mutex ms_lock; /* Protects ms_instance_list, ms_info_bo */169 struct list_head ms_instance_list;170 struct ivpu_bo *ms_info_bo;171 bool has_mmu_faults;172 bool bound;173 bool aborted;174};175 176extern int ivpu_dbg_mask;177extern u8 ivpu_pll_min_ratio;178extern u8 ivpu_pll_max_ratio;179extern int ivpu_sched_mode;180extern bool ivpu_disable_mmu_cont_pages;181extern bool ivpu_force_snoop;182 183#define IVPU_TEST_MODE_FW_TEST BIT(0)184#define IVPU_TEST_MODE_NULL_HW BIT(1)185#define IVPU_TEST_MODE_NULL_SUBMISSION BIT(2)186#define IVPU_TEST_MODE_D0I3_MSG_DISABLE BIT(4)187#define IVPU_TEST_MODE_D0I3_MSG_ENABLE BIT(5)188#define IVPU_TEST_MODE_PREEMPTION_DISABLE BIT(6)189#define IVPU_TEST_MODE_HWS_EXTRA_EVENTS BIT(7)190#define IVPU_TEST_MODE_DISABLE_TIMEOUTS BIT(8)191extern int ivpu_test_mode;192 193struct ivpu_file_priv *ivpu_file_priv_get(struct ivpu_file_priv *file_priv);194void ivpu_file_priv_put(struct ivpu_file_priv **link);195 196int ivpu_boot(struct ivpu_device *vdev);197int ivpu_shutdown(struct ivpu_device *vdev);198void ivpu_prepare_for_reset(struct ivpu_device *vdev);199 200static inline u8 ivpu_revision(struct ivpu_device *vdev)201{202 return to_pci_dev(vdev->drm.dev)->revision;203}204 205static inline u16 ivpu_device_id(struct ivpu_device *vdev)206{207 return to_pci_dev(vdev->drm.dev)->device;208}209 210static inline int ivpu_hw_ip_gen(struct ivpu_device *vdev)211{212 switch (ivpu_device_id(vdev)) {213 case PCI_DEVICE_ID_MTL:214 case PCI_DEVICE_ID_ARL:215 return IVPU_HW_IP_37XX;216 case PCI_DEVICE_ID_LNL:217 return IVPU_HW_IP_40XX;218 default:219 dump_stack();220 ivpu_err(vdev, "Unknown NPU IP generation\n");221 return 0;222 }223}224 225static inline int ivpu_hw_btrs_gen(struct ivpu_device *vdev)226{227 switch (ivpu_device_id(vdev)) {228 case PCI_DEVICE_ID_MTL:229 case PCI_DEVICE_ID_ARL:230 return IVPU_HW_BTRS_MTL;231 case PCI_DEVICE_ID_LNL:232 return IVPU_HW_BTRS_LNL;233 default:234 dump_stack();235 ivpu_err(vdev, "Unknown buttress generation\n");236 return 0;237 }238}239 240static inline struct ivpu_device *to_ivpu_device(struct drm_device *dev)241{242 return container_of(dev, struct ivpu_device, drm);243}244 245static inline u32 ivpu_get_context_count(struct ivpu_device *vdev)246{247 struct xa_limit ctx_limit = vdev->context_xa_limit;248 249 return (ctx_limit.max - ctx_limit.min + 1);250}251 252static inline u32 ivpu_get_platform(struct ivpu_device *vdev)253{254 WARN_ON_ONCE(vdev->platform == IVPU_PLATFORM_INVALID);255 return vdev->platform;256}257 258static inline bool ivpu_is_silicon(struct ivpu_device *vdev)259{260 return ivpu_get_platform(vdev) == IVPU_PLATFORM_SILICON;261}262 263static inline bool ivpu_is_simics(struct ivpu_device *vdev)264{265 return ivpu_get_platform(vdev) == IVPU_PLATFORM_SIMICS;266}267 268static inline bool ivpu_is_fpga(struct ivpu_device *vdev)269{270 return ivpu_get_platform(vdev) == IVPU_PLATFORM_FPGA;271}272 273static inline bool ivpu_is_force_snoop_enabled(struct ivpu_device *vdev)274{275 return ivpu_force_snoop;276}277 278#endif /* __IVPU_DRV_H__ */279