454 lines · c
1/* SPDX-License-Identifier: MIT */2/*3 * Copyright (c) 2020-2023, Intel Corporation.4 */5 6#ifndef VPU_BOOT_API_H7#define VPU_BOOT_API_H8 9/*10 * =========== FW API version information beginning ================11 * The bellow values will be used to construct the version info this way:12 * fw_bin_header->api_version[VPU_BOOT_API_VER_ID] = (VPU_BOOT_API_VER_MAJOR << 16) |13 * VPU_BOOT_API_VER_MINOR;14 * VPU_BOOT_API_VER_PATCH will be ignored. KMD and compatibility is not affected if this changes15 * This information is collected by using vpuip_2/application/vpuFirmware/make_std_fw_image.py16 * If a header is missing this info we ignore the header, if a header is missing or contains17 * partial info a build error will be generated.18 */19 20/*21 * Major version changes that break backward compatibility.22 * Major version must start from 1 and can only be incremented.23 */24#define VPU_BOOT_API_VER_MAJOR 325 26/*27 * Minor version changes when API backward compatibility is preserved.28 * Resets to 0 if Major version is incremented.29 */30#define VPU_BOOT_API_VER_MINOR 2431 32/*33 * API header changed (field names, documentation, formatting) but API itself has not been changed34 */35#define VPU_BOOT_API_VER_PATCH 036 37/*38 * Index in the API version table39 * Must be unique for each API40 */41#define VPU_BOOT_API_VER_INDEX 042/* ------------ FW API version information end ---------------------*/43 44#pragma pack(push, 4)45 46/*47 * Firmware image header format48 */49#define VPU_FW_HEADER_SIZE 409650#define VPU_FW_HEADER_VERSION 0x151#define VPU_FW_VERSION_SIZE 3252#define VPU_FW_API_VER_NUM 1653 54struct vpu_firmware_header {55 u32 header_version;56 u32 image_format;57 u64 image_load_address;58 u32 image_size;59 u64 entry_point;60 u8 vpu_version[VPU_FW_VERSION_SIZE];61 u32 compression_type;62 u64 firmware_version_load_address;63 u32 firmware_version_size;64 u64 boot_params_load_address;65 u32 api_version[VPU_FW_API_VER_NUM];66 /* Size of memory require for firmware execution */67 u32 runtime_size;68 u32 shave_nn_fw_size;69 /*70 * Size of primary preemption buffer, assuming a 2-job submission queue.71 * NOTE: host driver is expected to adapt size accordingly to actual72 * submission queue size and device capabilities.73 */74 u32 preemption_buffer_1_size;75 /*76 * Size of secondary preemption buffer, assuming a 2-job submission queue.77 * NOTE: host driver is expected to adapt size accordingly to actual78 * submission queue size and device capabilities.79 */80 u32 preemption_buffer_2_size;81 /* Space reserved for future preemption-related fields. */82 u32 preemption_reserved[6];83 /* FW image read only section start address, 4KB aligned */84 u64 ro_section_start_address;85 /* FW image read only section size, 4KB aligned */86 u32 ro_section_size;87 u32 reserved;88};89 90/*91 * Firmware boot parameters format92 */93 94#define VPU_BOOT_PLL_COUNT 395#define VPU_BOOT_PLL_OUT_COUNT 496 97/** Values for boot_type field */98#define VPU_BOOT_TYPE_COLDBOOT 099#define VPU_BOOT_TYPE_WARMBOOT 1100 101/** Value for magic filed */102#define VPU_BOOT_PARAMS_MAGIC 0x10000103 104/** VPU scheduling mode. By default, OS scheduling is used. */105#define VPU_SCHEDULING_MODE_OS 0106#define VPU_SCHEDULING_MODE_HW 1107 108enum VPU_BOOT_L2_CACHE_CFG_TYPE {109 VPU_BOOT_L2_CACHE_CFG_UPA = 0,110 VPU_BOOT_L2_CACHE_CFG_NN = 1,111 VPU_BOOT_L2_CACHE_CFG_NUM = 2112};113 114/** VPU MCA ECC signalling mode. By default, no signalling is used */115enum VPU_BOOT_MCA_ECC_SIGNAL_TYPE {116 VPU_BOOT_MCA_ECC_NONE = 0,117 VPU_BOOT_MCA_ECC_CORR = 1,118 VPU_BOOT_MCA_ECC_FATAL = 2,119 VPU_BOOT_MCA_ECC_BOTH = 3120};121 122/**123 * Logging destinations.124 *125 * Logging output can be directed to different logging destinations. This enum126 * defines the list of logging destinations supported by the VPU firmware (NOTE:127 * a specific VPU FW binary may support only a subset of such output128 * destinations, depending on the target platform and compile options).129 */130enum vpu_trace_destination {131 VPU_TRACE_DESTINATION_PIPEPRINT = 0x1,132 VPU_TRACE_DESTINATION_VERBOSE_TRACING = 0x2,133 VPU_TRACE_DESTINATION_NORTH_PEAK = 0x4,134};135 136/*137 * Processor bit shifts (for loggable HW components).138 */139#define VPU_TRACE_PROC_BIT_ARM 0140#define VPU_TRACE_PROC_BIT_LRT 1141#define VPU_TRACE_PROC_BIT_LNN 2142#define VPU_TRACE_PROC_BIT_SHV_0 3143#define VPU_TRACE_PROC_BIT_SHV_1 4144#define VPU_TRACE_PROC_BIT_SHV_2 5145#define VPU_TRACE_PROC_BIT_SHV_3 6146#define VPU_TRACE_PROC_BIT_SHV_4 7147#define VPU_TRACE_PROC_BIT_SHV_5 8148#define VPU_TRACE_PROC_BIT_SHV_6 9149#define VPU_TRACE_PROC_BIT_SHV_7 10150#define VPU_TRACE_PROC_BIT_SHV_8 11151#define VPU_TRACE_PROC_BIT_SHV_9 12152#define VPU_TRACE_PROC_BIT_SHV_10 13153#define VPU_TRACE_PROC_BIT_SHV_11 14154#define VPU_TRACE_PROC_BIT_SHV_12 15155#define VPU_TRACE_PROC_BIT_SHV_13 16156#define VPU_TRACE_PROC_BIT_SHV_14 17157#define VPU_TRACE_PROC_BIT_SHV_15 18158#define VPU_TRACE_PROC_BIT_ACT_SHV_0 19159#define VPU_TRACE_PROC_BIT_ACT_SHV_1 20160#define VPU_TRACE_PROC_BIT_ACT_SHV_2 21161#define VPU_TRACE_PROC_BIT_ACT_SHV_3 22162#define VPU_TRACE_PROC_NO_OF_HW_DEVS 23163 164/* VPU 30xx HW component IDs are sequential, so define first and last IDs. */165#define VPU_TRACE_PROC_BIT_30XX_FIRST VPU_TRACE_PROC_BIT_LRT166#define VPU_TRACE_PROC_BIT_30XX_LAST VPU_TRACE_PROC_BIT_SHV_15167#define VPU_TRACE_PROC_BIT_KMB_FIRST VPU_TRACE_PROC_BIT_30XX_FIRST168#define VPU_TRACE_PROC_BIT_KMB_LAST VPU_TRACE_PROC_BIT_30XX_LAST169 170struct vpu_boot_l2_cache_config {171 u8 use;172 u8 cfg;173};174 175struct vpu_warm_boot_section {176 u32 src;177 u32 dst;178 u32 size;179 u32 core_id;180 u32 is_clear_op;181};182 183/*184 * When HW scheduling mode is enabled, a present period is defined.185 * It will be used by VPU to swap between normal and focus priorities186 * to prevent starving of normal priority band (when implemented).187 * Host must provide a valid value at boot time in188 * `vpu_focus_present_timer_ms`. If the value provided by the host is not within the189 * defined range a default value will be used. Here we define the min. and max.190 * allowed values and the and default value of the present period. Units are milliseconds.191 */192#define VPU_PRESENT_CALL_PERIOD_MS_DEFAULT 50193#define VPU_PRESENT_CALL_PERIOD_MS_MIN 16194#define VPU_PRESENT_CALL_PERIOD_MS_MAX 10000195 196/**197 * Macros to enable various power profiles within the NPU.198 * To be defined as part of 32 bit mask.199 */200#define POWER_PROFILE_SURVIVABILITY 0x1201 202struct vpu_boot_params {203 u32 magic;204 u32 vpu_id;205 u32 vpu_count;206 u32 pad0[5];207 /* Clock frequencies: 0x20 - 0xFF */208 u32 frequency;209 u32 pll[VPU_BOOT_PLL_COUNT][VPU_BOOT_PLL_OUT_COUNT];210 u32 perf_clk_frequency;211 u32 pad1[42];212 /* Memory regions: 0x100 - 0x1FF */213 u64 ipc_header_area_start;214 u32 ipc_header_area_size;215 u64 shared_region_base;216 u32 shared_region_size;217 u64 ipc_payload_area_start;218 u32 ipc_payload_area_size;219 u64 global_aliased_pio_base;220 u32 global_aliased_pio_size;221 u32 autoconfig;222 struct vpu_boot_l2_cache_config cache_defaults[VPU_BOOT_L2_CACHE_CFG_NUM];223 u64 global_memory_allocator_base;224 u32 global_memory_allocator_size;225 /**226 * ShaveNN FW section VPU base address227 * On VPU2.7 HW this address must be within 2GB range starting from L2C_PAGE_TABLE base228 */229 u64 shave_nn_fw_base;230 u64 save_restore_ret_address; /* stores the address of FW's restore entry point */231 u32 pad2[43];232 /* IRQ re-direct numbers: 0x200 - 0x2FF */233 s32 watchdog_irq_mss;234 s32 watchdog_irq_nce;235 /* ARM -> VPU doorbell interrupt. ARM is notifying VPU of async command or compute job. */236 u32 host_to_vpu_irq;237 /* VPU -> ARM job done interrupt. VPU is notifying ARM of compute job completion. */238 u32 job_done_irq;239 /* VPU -> ARM IRQ line to use to request MMU update. */240 u32 mmu_update_request_irq;241 /* ARM -> VPU IRQ line to use to notify of MMU update completion. */242 u32 mmu_update_done_irq;243 /* ARM -> VPU IRQ line to use to request power level change. */244 u32 set_power_level_irq;245 /* VPU -> ARM IRQ line to use to notify of power level change completion. */246 u32 set_power_level_done_irq;247 /* VPU -> ARM IRQ line to use to notify of VPU idle state change */248 u32 set_vpu_idle_update_irq;249 /* VPU -> ARM IRQ line to use to request counter reset. */250 u32 metric_query_event_irq;251 /* ARM -> VPU IRQ line to use to notify of counter reset completion. */252 u32 metric_query_event_done_irq;253 /* VPU -> ARM IRQ line to use to notify of preemption completion. */254 u32 preemption_done_irq;255 /* Padding. */256 u32 pad3[52];257 /* Silicon information: 0x300 - 0x3FF */258 u32 host_version_id;259 u32 si_stepping;260 u64 device_id;261 u64 feature_exclusion;262 u64 sku;263 /** PLL ratio for minimum clock frequency */264 u32 min_freq_pll_ratio;265 /** PLL ratio for maximum clock frequency */266 u32 max_freq_pll_ratio;267 /**268 * Initial log level threshold (messages with log level severity less than269 * the threshold will not be logged); applies to every enabled logging270 * destination and loggable HW component. See 'mvLog_t' enum for acceptable271 * values.272 * TODO: EISW-33556: Move log level definition (mvLog_t) to this file.273 */274 u32 default_trace_level;275 u32 boot_type;276 u64 punit_telemetry_sram_base;277 u64 punit_telemetry_sram_size;278 u32 vpu_telemetry_enable;279 u64 crit_tracing_buff_addr;280 u32 crit_tracing_buff_size;281 u64 verbose_tracing_buff_addr;282 u32 verbose_tracing_buff_size;283 u64 verbose_tracing_sw_component_mask; /* TO BE REMOVED */284 /**285 * Mask of destinations to which logging messages are delivered; bitwise OR286 * of values defined in vpu_trace_destination enum.287 */288 u32 trace_destination_mask;289 /**290 * Mask of hardware components for which logging is enabled; bitwise OR of291 * bits defined by the VPU_TRACE_PROC_BIT_* macros.292 */293 u64 trace_hw_component_mask;294 /** Mask of trace message formats supported by the driver */295 u64 tracing_buff_message_format_mask;296 u64 trace_reserved_1[2];297 /**298 * Period at which the VPU reads the temp sensor values into MMIO, on299 * platforms where that is necessary (in ms). 0 to disable reads.300 */301 u32 temp_sensor_period_ms;302 /** PLL ratio for efficient clock frequency */303 u32 pn_freq_pll_ratio;304 /** DVFS Mode: Default: 0, Max Performance: 1, On Demand: 2, Power Save: 3 */305 u32 dvfs_mode;306 /**307 * Depending on DVFS Mode:308 * On-demand: Default if 0.309 * Bit 0-7 - uint8_t: Highest residency percent310 * Bit 8-15 - uint8_t: High residency percent311 * Bit 16-23 - uint8_t: Low residency percent312 * Bit 24-31 - uint8_t: Lowest residency percent313 * Bit 32-35 - unsigned 4b: PLL Ratio increase amount on highest residency314 * Bit 36-39 - unsigned 4b: PLL Ratio increase amount on high residency315 * Bit 40-43 - unsigned 4b: PLL Ratio decrease amount on low residency316 * Bit 44-47 - unsigned 4b: PLL Ratio decrease amount on lowest frequency317 * Bit 48-55 - uint8_t: Period (ms) for residency decisions318 * Bit 56-63 - uint8_t: Averaging windows (as multiples of period. Max: 30 decimal)319 * Power Save/Max Performance: Unused320 */321 u64 dvfs_param;322 /**323 * D0i3 delayed entry324 * Bit0: Disable CPU state save on D0i2 entry flow.325 * 0: Every D0i2 entry saves state. Save state IPC message ignored.326 * 1: IPC message required to save state on D0i3 entry flow.327 */328 u32 d0i3_delayed_entry;329 /* Time spent by VPU in D0i3 state */330 u64 d0i3_residency_time_us;331 /* Value of VPU perf counter at the time of entering D0i3 state . */332 u64 d0i3_entry_vpu_ts;333 /*334 * The system time of the host operating system in microseconds.335 * E.g the number of microseconds since 1st of January 1970, or whatever date the336 * host operating system uses to maintain system time.337 * This value will be used to track system time on the VPU.338 * The KMD is required to update this value on every VPU reset.339 */340 u64 system_time_us;341 u32 pad4[2];342 /*343 * The delta between device monotonic time and the current value of the344 * HW timestamp register, in ticks. Written by the firmware during boot.345 * Can be used by the KMD to calculate device time.346 */347 u64 device_time_delta_ticks;348 u32 pad7[14];349 /* Warm boot information: 0x400 - 0x43F */350 u32 warm_boot_sections_count;351 u32 warm_boot_start_address_reference;352 u32 warm_boot_section_info_address_offset;353 u32 pad5[13];354 /* Power States transitions timestamps: 0x440 - 0x46F*/355 struct {356 /* VPU_IDLE -> VPU_ACTIVE transition initiated timestamp */357 u64 vpu_active_state_requested;358 /* VPU_IDLE -> VPU_ACTIVE transition completed timestamp */359 u64 vpu_active_state_achieved;360 /* VPU_ACTIVE -> VPU_IDLE transition initiated timestamp */361 u64 vpu_idle_state_requested;362 /* VPU_ACTIVE -> VPU_IDLE transition completed timestamp */363 u64 vpu_idle_state_achieved;364 /* VPU_IDLE -> VPU_STANDBY transition initiated timestamp */365 u64 vpu_standby_state_requested;366 /* VPU_IDLE -> VPU_STANDBY transition completed timestamp */367 u64 vpu_standby_state_achieved;368 } power_states_timestamps;369 /* VPU scheduling mode. Values defined by VPU_SCHEDULING_MODE_* macros. */370 u32 vpu_scheduling_mode;371 /* Present call period in milliseconds. */372 u32 vpu_focus_present_timer_ms;373 /* VPU ECC Signaling */374 u32 vpu_uses_ecc_mca_signal;375 /* Values defined by POWER_PROFILE* macros */376 u32 power_profile;377 /* Microsecond value for DCT active cycle */378 u32 dct_active_us;379 /* Microsecond value for DCT inactive cycle */380 u32 dct_inactive_us;381 /* Unused/reserved: 0x488 - 0xFFF */382 u32 pad6[734];383};384 385/*386 * Magic numbers set between host and vpu to detect corruptio of tracing init387 */388 389#define VPU_TRACING_BUFFER_CANARY (0xCAFECAFE)390 391/* Tracing buffer message format definitions */392#define VPU_TRACING_FORMAT_STRING 0393#define VPU_TRACING_FORMAT_MIPI 2394/*395 * Header of the tracing buffer.396 * The below defined header will be stored at the beginning of397 * each allocated tracing buffer, followed by a series of 256b398 * of ASCII trace message entries.399 */400struct vpu_tracing_buffer_header {401 /**402 * Magic number set by host to detect corruption403 * @see VPU_TRACING_BUFFER_CANARY404 */405 u32 host_canary_start;406 /* offset from start of buffer for trace entries */407 u32 read_index;408 u32 pad_to_cache_line_size_0[14];409 /* End of first cache line */410 411 /**412 * Magic number set by host to detect corruption413 * @see VPU_TRACING_BUFFER_CANARY414 */415 u32 vpu_canary_start;416 /* offset from start of buffer from write start */417 u32 write_index;418 /* counter for buffer wrapping */419 u32 wrap_count;420 /* legacy field - do not use */421 u32 reserved_0;422 /**423 * Size of the log buffer include this header (@header_size) and space424 * reserved for all messages. If @alignment` is greater that 0 the @Size425 * must be multiple of @Alignment.426 */427 u32 size;428 /* Header version */429 u16 header_version;430 /* Header size */431 u16 header_size;432 /*433 * Format of the messages in the trace buffer434 * 0 - null terminated string435 * 1 - size + null terminated string436 * 2 - MIPI-SysT encoding437 */438 u32 format;439 /*440 * Message alignment441 * 0 - messages are place 1 after another442 * n - every message starts and multiple on offset443 */444 u32 alignment; /* 64, 128, 256 */445 /* Name of the logging entity, i.e "LRT", "LNN", "SHV0", etc */446 char name[16];447 u32 pad_to_cache_line_size_1[4];448 /* End of second cache line */449};450 451#pragma pack(pop)452 453#endif454