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1// SPDX-License-Identifier: GPL-2.0-only2/*3 * pata_artop.c - ARTOP ATA controller driver4 *5 * (C) 2006 Red Hat6 * (C) 2007,2011 Bartlomiej Zolnierkiewicz7 *8 * Based in part on drivers/ide/pci/aec62xx.c9 * Copyright (C) 1999-2002 Andre Hedrick <andre@linux-ide.org>10 * 865/865R fixes for Macintosh card version from a patch to the old11 * driver by Thibaut VARENE <varenet@parisc-linux.org>12 * When setting the PCI latency we must set 0x80 or higher for burst13 * performance Alessandro Zummo <alessandro.zummo@towertech.it>14 *15 * TODO16 * Investigate no_dsc on 850R17 * Clock detect18 */19 20#include <linux/kernel.h>21#include <linux/module.h>22#include <linux/pci.h>23#include <linux/blkdev.h>24#include <linux/delay.h>25#include <linux/device.h>26#include <scsi/scsi_host.h>27#include <linux/libata.h>28#include <linux/ata.h>29 30#define DRV_NAME "pata_artop"31#define DRV_VERSION "0.4.8"32 33/*34 * The ARTOP has 33 Mhz and "over clocked" timing tables. Until we35 * get PCI bus speed functionality we leave this as 0. Its a variable36 * for when we get the functionality and also for folks wanting to37 * test stuff.38 */39 40static int clock = 0;41 42/**43 * artop62x0_pre_reset - probe begin44 * @link: link45 * @deadline: deadline jiffies for the operation46 *47 * Nothing complicated needed here.48 */49 50static int artop62x0_pre_reset(struct ata_link *link, unsigned long deadline)51{52 static const struct pci_bits artop_enable_bits[] = {53 { 0x4AU, 1U, 0x02UL, 0x02UL }, /* port 0 */54 { 0x4AU, 1U, 0x04UL, 0x04UL }, /* port 1 */55 };56 57 struct ata_port *ap = link->ap;58 struct pci_dev *pdev = to_pci_dev(ap->host->dev);59 60 /* Odd numbered device ids are the units with enable bits. */61 if ((pdev->device & 1) &&62 !pci_test_config_bits(pdev, &artop_enable_bits[ap->port_no]))63 return -ENOENT;64 65 return ata_sff_prereset(link, deadline);66}67 68/**69 * artop6260_cable_detect - identify cable type70 * @ap: Port71 *72 * Identify the cable type for the ARTOP interface in question73 */74 75static int artop6260_cable_detect(struct ata_port *ap)76{77 struct pci_dev *pdev = to_pci_dev(ap->host->dev);78 u8 tmp;79 pci_read_config_byte(pdev, 0x49, &tmp);80 if (tmp & (1 << ap->port_no))81 return ATA_CBL_PATA40;82 return ATA_CBL_PATA80;83}84 85/**86 * artop6210_load_piomode - Load a set of PATA PIO timings87 * @ap: Port whose timings we are configuring88 * @adev: Device89 * @pio: PIO mode90 *91 * Set PIO mode for device, in host controller PCI config space. This92 * is used both to set PIO timings in PIO mode and also to set the93 * matching PIO clocking for UDMA, as well as the MWDMA timings.94 *95 * LOCKING:96 * None (inherited from caller).97 */98 99static void artop6210_load_piomode(struct ata_port *ap, struct ata_device *adev, unsigned int pio)100{101 struct pci_dev *pdev = to_pci_dev(ap->host->dev);102 int dn = adev->devno + 2 * ap->port_no;103 static const u16 timing[2][5] = {104 { 0x0000, 0x000A, 0x0008, 0x0303, 0x0301 },105 { 0x0700, 0x070A, 0x0708, 0x0403, 0x0401 }106 107 };108 /* Load the PIO timing active/recovery bits */109 pci_write_config_word(pdev, 0x40 + 2 * dn, timing[clock][pio]);110}111 112/**113 * artop6210_set_piomode - Initialize host controller PATA PIO timings114 * @ap: Port whose timings we are configuring115 * @adev: Device we are configuring116 *117 * Set PIO mode for device, in host controller PCI config space. For118 * ARTOP we must also clear the UDMA bits if we are not doing UDMA. In119 * the event UDMA is used the later call to set_dmamode will set the120 * bits as required.121 *122 * LOCKING:123 * None (inherited from caller).124 */125 126static void artop6210_set_piomode(struct ata_port *ap, struct ata_device *adev)127{128 struct pci_dev *pdev = to_pci_dev(ap->host->dev);129 int dn = adev->devno + 2 * ap->port_no;130 u8 ultra;131 132 artop6210_load_piomode(ap, adev, adev->pio_mode - XFER_PIO_0);133 134 /* Clear the UDMA mode bits (set_dmamode will redo this if needed) */135 pci_read_config_byte(pdev, 0x54, &ultra);136 ultra &= ~(3 << (2 * dn));137 pci_write_config_byte(pdev, 0x54, ultra);138}139 140/**141 * artop6260_load_piomode - Initialize host controller PATA PIO timings142 * @ap: Port whose timings we are configuring143 * @adev: Device we are configuring144 * @pio: PIO mode145 *146 * Set PIO mode for device, in host controller PCI config space. The147 * ARTOP6260 and relatives store the timing data differently.148 *149 * LOCKING:150 * None (inherited from caller).151 */152 153static void artop6260_load_piomode (struct ata_port *ap, struct ata_device *adev, unsigned int pio)154{155 struct pci_dev *pdev = to_pci_dev(ap->host->dev);156 int dn = adev->devno + 2 * ap->port_no;157 static const u8 timing[2][5] = {158 { 0x00, 0x0A, 0x08, 0x33, 0x31 },159 { 0x70, 0x7A, 0x78, 0x43, 0x41 }160 161 };162 /* Load the PIO timing active/recovery bits */163 pci_write_config_byte(pdev, 0x40 + dn, timing[clock][pio]);164}165 166/**167 * artop6260_set_piomode - Initialize host controller PATA PIO timings168 * @ap: Port whose timings we are configuring169 * @adev: Device we are configuring170 *171 * Set PIO mode for device, in host controller PCI config space. For172 * ARTOP we must also clear the UDMA bits if we are not doing UDMA. In173 * the event UDMA is used the later call to set_dmamode will set the174 * bits as required.175 *176 * LOCKING:177 * None (inherited from caller).178 */179 180static void artop6260_set_piomode(struct ata_port *ap, struct ata_device *adev)181{182 struct pci_dev *pdev = to_pci_dev(ap->host->dev);183 u8 ultra;184 185 artop6260_load_piomode(ap, adev, adev->pio_mode - XFER_PIO_0);186 187 /* Clear the UDMA mode bits (set_dmamode will redo this if needed) */188 pci_read_config_byte(pdev, 0x44 + ap->port_no, &ultra);189 ultra &= ~(7 << (4 * adev->devno)); /* One nibble per drive */190 pci_write_config_byte(pdev, 0x44 + ap->port_no, ultra);191}192 193/**194 * artop6210_set_dmamode - Initialize host controller PATA PIO timings195 * @ap: Port whose timings we are configuring196 * @adev: Device whose timings we are configuring197 *198 * Set DMA mode for device, in host controller PCI config space.199 *200 * LOCKING:201 * None (inherited from caller).202 */203 204static void artop6210_set_dmamode (struct ata_port *ap, struct ata_device *adev)205{206 unsigned int pio;207 struct pci_dev *pdev = to_pci_dev(ap->host->dev);208 int dn = adev->devno + 2 * ap->port_no;209 u8 ultra;210 211 if (adev->dma_mode == XFER_MW_DMA_0)212 pio = 1;213 else214 pio = 4;215 216 /* Load the PIO timing active/recovery bits */217 artop6210_load_piomode(ap, adev, pio);218 219 pci_read_config_byte(pdev, 0x54, &ultra);220 ultra &= ~(3 << (2 * dn));221 222 /* Add ultra DMA bits if in UDMA mode */223 if (adev->dma_mode >= XFER_UDMA_0) {224 u8 mode = (adev->dma_mode - XFER_UDMA_0) + 1 - clock;225 if (mode == 0)226 mode = 1;227 ultra |= (mode << (2 * dn));228 }229 pci_write_config_byte(pdev, 0x54, ultra);230}231 232/**233 * artop6260_set_dmamode - Initialize host controller PATA PIO timings234 * @ap: Port whose timings we are configuring235 * @adev: Device we are configuring236 *237 * Set DMA mode for device, in host controller PCI config space. The238 * ARTOP6260 and relatives store the timing data differently.239 *240 * LOCKING:241 * None (inherited from caller).242 */243 244static void artop6260_set_dmamode (struct ata_port *ap, struct ata_device *adev)245{246 unsigned int pio;247 struct pci_dev *pdev = to_pci_dev(ap->host->dev);248 u8 ultra;249 250 if (adev->dma_mode == XFER_MW_DMA_0)251 pio = 1;252 else253 pio = 4;254 255 /* Load the PIO timing active/recovery bits */256 artop6260_load_piomode(ap, adev, pio);257 258 /* Add ultra DMA bits if in UDMA mode */259 pci_read_config_byte(pdev, 0x44 + ap->port_no, &ultra);260 ultra &= ~(7 << (4 * adev->devno)); /* One nibble per drive */261 if (adev->dma_mode >= XFER_UDMA_0) {262 u8 mode = adev->dma_mode - XFER_UDMA_0 + 1 - clock;263 if (mode == 0)264 mode = 1;265 ultra |= (mode << (4 * adev->devno));266 }267 pci_write_config_byte(pdev, 0x44 + ap->port_no, ultra);268}269 270/**271 * artop6210_qc_defer - implement serialization272 * @qc: command273 *274 * Issue commands per host on this chip.275 */276 277static int artop6210_qc_defer(struct ata_queued_cmd *qc)278{279 struct ata_host *host = qc->ap->host;280 struct ata_port *alt = host->ports[1 ^ qc->ap->port_no];281 int rc;282 283 /* First apply the usual rules */284 rc = ata_std_qc_defer(qc);285 if (rc != 0)286 return rc;287 288 /* Now apply serialization rules. Only allow a command if the289 other channel state machine is idle */290 if (alt && alt->qc_active)291 return ATA_DEFER_PORT;292 return 0;293}294 295static const struct scsi_host_template artop_sht = {296 ATA_BMDMA_SHT(DRV_NAME),297};298 299static struct ata_port_operations artop6210_ops = {300 .inherits = &ata_bmdma_port_ops,301 .cable_detect = ata_cable_40wire,302 .set_piomode = artop6210_set_piomode,303 .set_dmamode = artop6210_set_dmamode,304 .prereset = artop62x0_pre_reset,305 .qc_defer = artop6210_qc_defer,306};307 308static struct ata_port_operations artop6260_ops = {309 .inherits = &ata_bmdma_port_ops,310 .cable_detect = artop6260_cable_detect,311 .set_piomode = artop6260_set_piomode,312 .set_dmamode = artop6260_set_dmamode,313 .prereset = artop62x0_pre_reset,314};315 316static void atp8xx_fixup(struct pci_dev *pdev)317{318 u8 reg;319 320 switch (pdev->device) {321 case 0x0005:322 /* BIOS may have left us in UDMA, clear it before libata probe */323 pci_write_config_byte(pdev, 0x54, 0);324 break;325 case 0x0008:326 case 0x0009:327 /* Mac systems come up with some registers not set as we328 will need them */329 330 /* Clear reset & test bits */331 pci_read_config_byte(pdev, 0x49, ®);332 pci_write_config_byte(pdev, 0x49, reg & ~0x30);333 334 /* PCI latency must be > 0x80 for burst mode, tweak it335 * if required.336 */337 pci_read_config_byte(pdev, PCI_LATENCY_TIMER, ®);338 if (reg <= 0x80)339 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x90);340 341 /* Enable IRQ output and burst mode */342 pci_read_config_byte(pdev, 0x4a, ®);343 pci_write_config_byte(pdev, 0x4a, (reg & ~0x01) | 0x80);344 break;345 }346}347 348/**349 * artop_init_one - Register ARTOP ATA PCI device with kernel services350 * @pdev: PCI device to register351 * @id: PCI device ID352 *353 * Called from kernel PCI layer.354 *355 * LOCKING:356 * Inherited from PCI layer (may sleep).357 *358 * RETURNS:359 * Zero on success, or -ERRNO value.360 */361 362static int artop_init_one (struct pci_dev *pdev, const struct pci_device_id *id)363{364 static const struct ata_port_info info_6210 = {365 .flags = ATA_FLAG_SLAVE_POSS,366 .pio_mask = ATA_PIO4,367 .mwdma_mask = ATA_MWDMA2,368 .udma_mask = ATA_UDMA2,369 .port_ops = &artop6210_ops,370 };371 static const struct ata_port_info info_626x = {372 .flags = ATA_FLAG_SLAVE_POSS,373 .pio_mask = ATA_PIO4,374 .mwdma_mask = ATA_MWDMA2,375 .udma_mask = ATA_UDMA4,376 .port_ops = &artop6260_ops,377 };378 static const struct ata_port_info info_628x = {379 .flags = ATA_FLAG_SLAVE_POSS,380 .pio_mask = ATA_PIO4,381 .mwdma_mask = ATA_MWDMA2,382 .udma_mask = ATA_UDMA5,383 .port_ops = &artop6260_ops,384 };385 static const struct ata_port_info info_628x_fast = {386 .flags = ATA_FLAG_SLAVE_POSS,387 .pio_mask = ATA_PIO4,388 .mwdma_mask = ATA_MWDMA2,389 .udma_mask = ATA_UDMA6,390 .port_ops = &artop6260_ops,391 };392 const struct ata_port_info *ppi[] = { NULL, NULL };393 int rc;394 395 ata_print_version_once(&pdev->dev, DRV_VERSION);396 397 rc = pcim_enable_device(pdev);398 if (rc)399 return rc;400 401 switch (id->driver_data) {402 case 0: /* 6210 variant */403 ppi[0] = &info_6210;404 break;405 case 1: /* 6260 */406 ppi[0] = &info_626x;407 break;408 case 2: /* 6280 or 6280 + fast */409 if (inb(pci_resource_start(pdev, 4)) & 0x10)410 ppi[0] = &info_628x_fast;411 else412 ppi[0] = &info_628x;413 break;414 }415 416 BUG_ON(ppi[0] == NULL);417 418 atp8xx_fixup(pdev);419 420 return ata_pci_bmdma_init_one(pdev, ppi, &artop_sht, NULL, 0);421}422 423static const struct pci_device_id artop_pci_tbl[] = {424 { PCI_VDEVICE(ARTOP, 0x0005), 0 },425 { PCI_VDEVICE(ARTOP, 0x0006), 1 },426 { PCI_VDEVICE(ARTOP, 0x0007), 1 },427 { PCI_VDEVICE(ARTOP, 0x0008), 2 },428 { PCI_VDEVICE(ARTOP, 0x0009), 2 },429 430 { } /* terminate list */431};432 433#ifdef CONFIG_PM_SLEEP434static int atp8xx_reinit_one(struct pci_dev *pdev)435{436 struct ata_host *host = pci_get_drvdata(pdev);437 int rc;438 439 rc = ata_pci_device_do_resume(pdev);440 if (rc)441 return rc;442 443 atp8xx_fixup(pdev);444 445 ata_host_resume(host);446 return 0;447}448#endif449 450static struct pci_driver artop_pci_driver = {451 .name = DRV_NAME,452 .id_table = artop_pci_tbl,453 .probe = artop_init_one,454 .remove = ata_pci_remove_one,455#ifdef CONFIG_PM_SLEEP456 .suspend = ata_pci_device_suspend,457 .resume = atp8xx_reinit_one,458#endif459};460 461module_pci_driver(artop_pci_driver);462 463MODULE_AUTHOR("Alan Cox, Bartlomiej Zolnierkiewicz");464MODULE_DESCRIPTION("SCSI low-level driver for ARTOP PATA");465MODULE_LICENSE("GPL");466MODULE_DEVICE_TABLE(pci, artop_pci_tbl);467MODULE_VERSION(DRV_VERSION);468