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1// SPDX-License-Identifier: GPL-2.0-only2/*3 * pata_efar.c - EFAR PIIX clone controller driver4 *5 * (C) 2005 Red Hat6 * (C) 2009-2010 Bartlomiej Zolnierkiewicz7 *8 * Some parts based on ata_piix.c by Jeff Garzik and others.9 *10 * The EFAR is a PIIX4 clone with UDMA66 support. Unlike the later11 * Intel ICH controllers the EFAR widened the UDMA mode register bits12 * and doesn't require the funky clock selection.13 */14 15#include <linux/kernel.h>16#include <linux/module.h>17#include <linux/pci.h>18#include <linux/blkdev.h>19#include <linux/delay.h>20#include <linux/device.h>21#include <scsi/scsi_host.h>22#include <linux/libata.h>23#include <linux/ata.h>24 25#define DRV_NAME "pata_efar"26#define DRV_VERSION "0.4.5"27 28/**29 * efar_pre_reset - Enable bits30 * @link: ATA link31 * @deadline: deadline jiffies for the operation32 *33 * Perform cable detection for the EFAR ATA interface. This is34 * different to the PIIX arrangement35 */36 37static int efar_pre_reset(struct ata_link *link, unsigned long deadline)38{39 static const struct pci_bits efar_enable_bits[] = {40 { 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */41 { 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */42 };43 struct ata_port *ap = link->ap;44 struct pci_dev *pdev = to_pci_dev(ap->host->dev);45 46 if (!pci_test_config_bits(pdev, &efar_enable_bits[ap->port_no]))47 return -ENOENT;48 49 return ata_sff_prereset(link, deadline);50}51 52/**53 * efar_cable_detect - check for 40/80 pin54 * @ap: Port55 *56 * Perform cable detection for the EFAR ATA interface. This is57 * different to the PIIX arrangement58 */59 60static int efar_cable_detect(struct ata_port *ap)61{62 struct pci_dev *pdev = to_pci_dev(ap->host->dev);63 u8 tmp;64 65 pci_read_config_byte(pdev, 0x47, &tmp);66 if (tmp & (2 >> ap->port_no))67 return ATA_CBL_PATA40;68 return ATA_CBL_PATA80;69}70 71static DEFINE_SPINLOCK(efar_lock);72 73/**74 * efar_set_piomode - Initialize host controller PATA PIO timings75 * @ap: Port whose timings we are configuring76 * @adev: Device to program77 *78 * Set PIO mode for device, in host controller PCI config space.79 *80 * LOCKING:81 * None (inherited from caller).82 */83 84static void efar_set_piomode (struct ata_port *ap, struct ata_device *adev)85{86 unsigned int pio = adev->pio_mode - XFER_PIO_0;87 struct pci_dev *dev = to_pci_dev(ap->host->dev);88 unsigned int master_port = ap->port_no ? 0x42 : 0x40;89 unsigned long flags;90 u16 master_data;91 u8 udma_enable;92 int control = 0;93 94 /*95 * See Intel Document 298600-004 for the timing programing rules96 * for PIIX/ICH. The EFAR is a clone so very similar97 */98 99 static const /* ISP RTC */100 u8 timings[][2] = { { 0, 0 },101 { 0, 0 },102 { 1, 0 },103 { 2, 1 },104 { 2, 3 }, };105 106 if (pio > 1)107 control |= 1; /* TIME */108 if (ata_pio_need_iordy(adev)) /* PIO 3/4 require IORDY */109 control |= 2; /* IE */110 /* Intel specifies that the prefetch/posting is for disk only */111 if (adev->class == ATA_DEV_ATA)112 control |= 4; /* PPE */113 114 spin_lock_irqsave(&efar_lock, flags);115 116 pci_read_config_word(dev, master_port, &master_data);117 118 /* Set PPE, IE, and TIME as appropriate */119 if (adev->devno == 0) {120 master_data &= 0xCCF0;121 master_data |= control;122 master_data |= (timings[pio][0] << 12) |123 (timings[pio][1] << 8);124 } else {125 int shift = 4 * ap->port_no;126 u8 slave_data;127 128 master_data &= 0xFF0F;129 master_data |= (control << 4);130 131 /* Slave timing in separate register */132 pci_read_config_byte(dev, 0x44, &slave_data);133 slave_data &= ap->port_no ? 0x0F : 0xF0;134 slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << shift;135 pci_write_config_byte(dev, 0x44, slave_data);136 }137 138 master_data |= 0x4000; /* Ensure SITRE is set */139 pci_write_config_word(dev, master_port, master_data);140 141 pci_read_config_byte(dev, 0x48, &udma_enable);142 udma_enable &= ~(1 << (2 * ap->port_no + adev->devno));143 pci_write_config_byte(dev, 0x48, udma_enable);144 spin_unlock_irqrestore(&efar_lock, flags);145}146 147/**148 * efar_set_dmamode - Initialize host controller PATA DMA timings149 * @ap: Port whose timings we are configuring150 * @adev: Device to program151 *152 * Set UDMA/MWDMA mode for device, in host controller PCI config space.153 *154 * LOCKING:155 * None (inherited from caller).156 */157 158static void efar_set_dmamode (struct ata_port *ap, struct ata_device *adev)159{160 struct pci_dev *dev = to_pci_dev(ap->host->dev);161 u8 master_port = ap->port_no ? 0x42 : 0x40;162 u16 master_data;163 u8 speed = adev->dma_mode;164 int devid = adev->devno + 2 * ap->port_no;165 unsigned long flags;166 u8 udma_enable;167 168 static const /* ISP RTC */169 u8 timings[][2] = { { 0, 0 },170 { 0, 0 },171 { 1, 0 },172 { 2, 1 },173 { 2, 3 }, };174 175 spin_lock_irqsave(&efar_lock, flags);176 177 pci_read_config_word(dev, master_port, &master_data);178 pci_read_config_byte(dev, 0x48, &udma_enable);179 180 if (speed >= XFER_UDMA_0) {181 unsigned int udma = adev->dma_mode - XFER_UDMA_0;182 u16 udma_timing;183 184 udma_enable |= (1 << devid);185 186 /* Load the UDMA mode number */187 pci_read_config_word(dev, 0x4A, &udma_timing);188 udma_timing &= ~(7 << (4 * devid));189 udma_timing |= udma << (4 * devid);190 pci_write_config_word(dev, 0x4A, udma_timing);191 } else {192 /*193 * MWDMA is driven by the PIO timings. We must also enable194 * IORDY unconditionally along with TIME1. PPE has already195 * been set when the PIO timing was set.196 */197 unsigned int mwdma = adev->dma_mode - XFER_MW_DMA_0;198 unsigned int control;199 u8 slave_data;200 const unsigned int needed_pio[3] = {201 XFER_PIO_0, XFER_PIO_3, XFER_PIO_4202 };203 int pio = needed_pio[mwdma] - XFER_PIO_0;204 205 control = 3; /* IORDY|TIME1 */206 207 /* If the drive MWDMA is faster than it can do PIO then208 we must force PIO into PIO0 */209 210 if (adev->pio_mode < needed_pio[mwdma])211 /* Enable DMA timing only */212 control |= 8; /* PIO cycles in PIO0 */213 214 if (adev->devno) { /* Slave */215 master_data &= 0xFF4F; /* Mask out IORDY|TIME1|DMAONLY */216 master_data |= control << 4;217 pci_read_config_byte(dev, 0x44, &slave_data);218 slave_data &= ap->port_no ? 0x0F : 0xF0;219 /* Load the matching timing */220 slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << (ap->port_no ? 4 : 0);221 pci_write_config_byte(dev, 0x44, slave_data);222 } else { /* Master */223 master_data &= 0xCCF4; /* Mask out IORDY|TIME1|DMAONLY224 and master timing bits */225 master_data |= control;226 master_data |=227 (timings[pio][0] << 12) |228 (timings[pio][1] << 8);229 }230 udma_enable &= ~(1 << devid);231 pci_write_config_word(dev, master_port, master_data);232 }233 pci_write_config_byte(dev, 0x48, udma_enable);234 spin_unlock_irqrestore(&efar_lock, flags);235}236 237static const struct scsi_host_template efar_sht = {238 ATA_BMDMA_SHT(DRV_NAME),239};240 241static struct ata_port_operations efar_ops = {242 .inherits = &ata_bmdma_port_ops,243 .cable_detect = efar_cable_detect,244 .set_piomode = efar_set_piomode,245 .set_dmamode = efar_set_dmamode,246 .prereset = efar_pre_reset,247};248 249 250/**251 * efar_init_one - Register EFAR ATA PCI device with kernel services252 * @pdev: PCI device to register253 * @ent: Entry in efar_pci_tbl matching with @pdev254 *255 * Called from kernel PCI layer.256 *257 * LOCKING:258 * Inherited from PCI layer (may sleep).259 *260 * RETURNS:261 * Zero on success, or -ERRNO value.262 */263 264static int efar_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)265{266 static const struct ata_port_info info = {267 .flags = ATA_FLAG_SLAVE_POSS,268 .pio_mask = ATA_PIO4,269 .mwdma_mask = ATA_MWDMA12_ONLY,270 .udma_mask = ATA_UDMA4,271 .port_ops = &efar_ops,272 };273 const struct ata_port_info *ppi[] = { &info, &info };274 275 ata_print_version_once(&pdev->dev, DRV_VERSION);276 277 return ata_pci_bmdma_init_one(pdev, ppi, &efar_sht, NULL,278 ATA_HOST_PARALLEL_SCAN);279}280 281static const struct pci_device_id efar_pci_tbl[] = {282 { PCI_VDEVICE(EFAR, 0x9130), },283 284 { } /* terminate list */285};286 287static struct pci_driver efar_pci_driver = {288 .name = DRV_NAME,289 .id_table = efar_pci_tbl,290 .probe = efar_init_one,291 .remove = ata_pci_remove_one,292#ifdef CONFIG_PM_SLEEP293 .suspend = ata_pci_device_suspend,294 .resume = ata_pci_device_resume,295#endif296};297 298module_pci_driver(efar_pci_driver);299 300MODULE_AUTHOR("Alan Cox");301MODULE_DESCRIPTION("SCSI low-level driver for EFAR PIIX clones");302MODULE_LICENSE("GPL");303MODULE_DEVICE_TABLE(pci, efar_pci_tbl);304MODULE_VERSION(DRV_VERSION);305