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1// SPDX-License-Identifier: GPL-2.0-only2/*3 * Libata driver for the highpoint 366 and 368 UDMA66 ATA controllers.4 *5 * This driver is heavily based upon:6 *7 * linux/drivers/ide/pci/hpt366.c Version 0.36 April 25, 20038 *9 * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org>10 * Portions Copyright (C) 2001 Sun Microsystems, Inc.11 * Portions Copyright (C) 2003 Red Hat Inc12 *13 *14 * TODO15 * Look into engine reset on timeout errors. Should not be required.16 */17#include <linux/kernel.h>18#include <linux/module.h>19#include <linux/pci.h>20#include <linux/blkdev.h>21#include <linux/delay.h>22#include <scsi/scsi_host.h>23#include <linux/libata.h>24 25#define DRV_NAME "pata_hpt366"26#define DRV_VERSION "0.6.13"27 28struct hpt_clock {29 u8 xfer_mode;30 u32 timing;31};32 33/* key for bus clock timings34 * bit35 * 0:3 data_high_time. Inactive time of DIOW_/DIOR_ for PIO and MW DMA.36 * cycles = value + 137 * 4:7 data_low_time. Active time of DIOW_/DIOR_ for PIO and MW DMA.38 * cycles = value + 139 * 8:11 cmd_high_time. Inactive time of DIOW_/DIOR_ during task file40 * register access.41 * 12:15 cmd_low_time. Active time of DIOW_/DIOR_ during task file42 * register access.43 * 16:18 udma_cycle_time. Clock cycles for UDMA xfer?44 * 19:21 pre_high_time. Time to initialize 1st cycle for PIO and MW DMA xfer.45 * 22:24 cmd_pre_high_time. Time to initialize 1st PIO cycle for task file46 * register access.47 * 28 UDMA enable.48 * 29 DMA enable.49 * 30 PIO_MST enable. If set, the chip is in bus master mode during50 * PIO xfer.51 * 31 FIFO enable.52 */53 54static const struct hpt_clock hpt366_40[] = {55 { XFER_UDMA_4, 0x900fd943 },56 { XFER_UDMA_3, 0x900ad943 },57 { XFER_UDMA_2, 0x900bd943 },58 { XFER_UDMA_1, 0x9008d943 },59 { XFER_UDMA_0, 0x9008d943 },60 61 { XFER_MW_DMA_2, 0xa008d943 },62 { XFER_MW_DMA_1, 0xa010d955 },63 { XFER_MW_DMA_0, 0xa010d9fc },64 65 { XFER_PIO_4, 0xc008d963 },66 { XFER_PIO_3, 0xc010d974 },67 { XFER_PIO_2, 0xc010d997 },68 { XFER_PIO_1, 0xc010d9c7 },69 { XFER_PIO_0, 0xc018d9d9 },70 { 0, 0x0120d9d9 }71};72 73static const struct hpt_clock hpt366_33[] = {74 { XFER_UDMA_4, 0x90c9a731 },75 { XFER_UDMA_3, 0x90cfa731 },76 { XFER_UDMA_2, 0x90caa731 },77 { XFER_UDMA_1, 0x90cba731 },78 { XFER_UDMA_0, 0x90c8a731 },79 80 { XFER_MW_DMA_2, 0xa0c8a731 },81 { XFER_MW_DMA_1, 0xa0c8a732 }, /* 0xa0c8a733 */82 { XFER_MW_DMA_0, 0xa0c8a797 },83 84 { XFER_PIO_4, 0xc0c8a731 },85 { XFER_PIO_3, 0xc0c8a742 },86 { XFER_PIO_2, 0xc0d0a753 },87 { XFER_PIO_1, 0xc0d0a7a3 }, /* 0xc0d0a793 */88 { XFER_PIO_0, 0xc0d0a7aa }, /* 0xc0d0a7a7 */89 { 0, 0x0120a7a7 }90};91 92static const struct hpt_clock hpt366_25[] = {93 { XFER_UDMA_4, 0x90c98521 },94 { XFER_UDMA_3, 0x90cf8521 },95 { XFER_UDMA_2, 0x90cf8521 },96 { XFER_UDMA_1, 0x90cb8521 },97 { XFER_UDMA_0, 0x90cb8521 },98 99 { XFER_MW_DMA_2, 0xa0ca8521 },100 { XFER_MW_DMA_1, 0xa0ca8532 },101 { XFER_MW_DMA_0, 0xa0ca8575 },102 103 { XFER_PIO_4, 0xc0ca8521 },104 { XFER_PIO_3, 0xc0ca8532 },105 { XFER_PIO_2, 0xc0ca8542 },106 { XFER_PIO_1, 0xc0d08572 },107 { XFER_PIO_0, 0xc0d08585 },108 { 0, 0x01208585 }109};110 111/**112 * hpt36x_find_mode - find the hpt36x timing113 * @ap: ATA port114 * @speed: transfer mode115 *116 * Return the 32bit register programming information for this channel117 * that matches the speed provided.118 */119 120static u32 hpt36x_find_mode(struct ata_port *ap, int speed)121{122 struct hpt_clock *clocks = ap->host->private_data;123 124 while (clocks->xfer_mode) {125 if (clocks->xfer_mode == speed)126 return clocks->timing;127 clocks++;128 }129 BUG();130 return 0xffffffffU; /* silence compiler warning */131}132 133static const char * const bad_ata33[] = {134 "Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3",135 "Maxtor 90845U3", "Maxtor 90650U2",136 "Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5",137 "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2",138 "Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6",139 "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4",140 "Maxtor 90510D4",141 "Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2",142 "Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7",143 "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4",144 "Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5",145 "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2",146 NULL147};148 149static const char * const bad_ata66_4[] = {150 "IBM-DTLA-307075",151 "IBM-DTLA-307060",152 "IBM-DTLA-307045",153 "IBM-DTLA-307030",154 "IBM-DTLA-307020",155 "IBM-DTLA-307015",156 "IBM-DTLA-305040",157 "IBM-DTLA-305030",158 "IBM-DTLA-305020",159 "IC35L010AVER07-0",160 "IC35L020AVER07-0",161 "IC35L030AVER07-0",162 "IC35L040AVER07-0",163 "IC35L060AVER07-0",164 "WDC AC310200R",165 NULL166};167 168static const char * const bad_ata66_3[] = {169 "WDC AC310200R",170 NULL171};172 173static int hpt_dma_broken(const struct ata_device *dev, char *modestr,174 const char * const list[])175{176 unsigned char model_num[ATA_ID_PROD_LEN + 1];177 int i;178 179 ata_id_c_string(dev->id, model_num, ATA_ID_PROD, sizeof(model_num));180 181 i = match_string(list, -1, model_num);182 if (i >= 0) {183 ata_dev_warn(dev, "%s is not supported for %s\n", modestr, list[i]);184 return 1;185 }186 return 0;187}188 189/**190 * hpt366_filter - mode selection filter191 * @adev: ATA device192 * @mask: Current mask to manipulate and pass back193 *194 * Block UDMA on devices that cause trouble with this controller.195 */196 197static unsigned int hpt366_filter(struct ata_device *adev, unsigned int mask)198{199 if (adev->class == ATA_DEV_ATA) {200 if (hpt_dma_broken(adev, "UDMA", bad_ata33))201 mask &= ~ATA_MASK_UDMA;202 if (hpt_dma_broken(adev, "UDMA3", bad_ata66_3))203 mask &= ~(0xF8 << ATA_SHIFT_UDMA);204 if (hpt_dma_broken(adev, "UDMA4", bad_ata66_4))205 mask &= ~(0xF0 << ATA_SHIFT_UDMA);206 } else if (adev->class == ATA_DEV_ATAPI)207 mask &= ~(ATA_MASK_MWDMA | ATA_MASK_UDMA);208 209 return mask;210}211 212static int hpt36x_cable_detect(struct ata_port *ap)213{214 struct pci_dev *pdev = to_pci_dev(ap->host->dev);215 u8 ata66;216 217 /*218 * Each channel of pata_hpt366 occupies separate PCI function219 * as the primary channel and bit1 indicates the cable type.220 */221 pci_read_config_byte(pdev, 0x5A, &ata66);222 if (ata66 & 2)223 return ATA_CBL_PATA40;224 return ATA_CBL_PATA80;225}226 227static void hpt366_set_mode(struct ata_port *ap, struct ata_device *adev,228 u8 mode)229{230 struct pci_dev *pdev = to_pci_dev(ap->host->dev);231 u32 addr = 0x40 + 4 * adev->devno;232 u32 mask, reg, t;233 234 /* determine timing mask and find matching clock entry */235 if (mode < XFER_MW_DMA_0)236 mask = 0xc1f8ffff;237 else if (mode < XFER_UDMA_0)238 mask = 0x303800ff;239 else240 mask = 0x30070000;241 242 t = hpt36x_find_mode(ap, mode);243 244 /*245 * Combine new mode bits with old config bits and disable246 * on-chip PIO FIFO/buffer (and PIO MST mode as well) to avoid247 * problems handling I/O errors later.248 */249 pci_read_config_dword(pdev, addr, ®);250 reg = ((reg & ~mask) | (t & mask)) & ~0xc0000000;251 pci_write_config_dword(pdev, addr, reg);252}253 254/**255 * hpt366_set_piomode - PIO setup256 * @ap: ATA interface257 * @adev: device on the interface258 *259 * Perform PIO mode setup.260 */261 262static void hpt366_set_piomode(struct ata_port *ap, struct ata_device *adev)263{264 hpt366_set_mode(ap, adev, adev->pio_mode);265}266 267/**268 * hpt366_set_dmamode - DMA timing setup269 * @ap: ATA interface270 * @adev: Device being configured271 *272 * Set up the channel for MWDMA or UDMA modes. Much the same as with273 * PIO, load the mode number and then set MWDMA or UDMA flag.274 */275 276static void hpt366_set_dmamode(struct ata_port *ap, struct ata_device *adev)277{278 hpt366_set_mode(ap, adev, adev->dma_mode);279}280 281/**282 * hpt366_prereset - reset the hpt36x bus283 * @link: ATA link to reset284 * @deadline: deadline jiffies for the operation285 *286 * Perform the initial reset handling for the 36x series controllers.287 * Reset the hardware and state machine,288 */289 290static int hpt366_prereset(struct ata_link *link, unsigned long deadline)291{292 struct ata_port *ap = link->ap;293 struct pci_dev *pdev = to_pci_dev(ap->host->dev);294 /*295 * HPT36x chips have one channel per function and have296 * both channel enable bits located differently and visible297 * to both functions -- really stupid design decision... :-(298 * Bit 4 is for the primary channel, bit 5 for the secondary.299 */300 static const struct pci_bits hpt366_enable_bits = {301 0x50, 1, 0x30, 0x30302 };303 u8 mcr2;304 305 if (!pci_test_config_bits(pdev, &hpt366_enable_bits))306 return -ENOENT;307 308 pci_read_config_byte(pdev, 0x51, &mcr2);309 if (mcr2 & 0x80)310 pci_write_config_byte(pdev, 0x51, mcr2 & ~0x80);311 312 return ata_sff_prereset(link, deadline);313}314 315static const struct scsi_host_template hpt36x_sht = {316 ATA_BMDMA_SHT(DRV_NAME),317};318 319/*320 * Configuration for HPT366/68321 */322 323static struct ata_port_operations hpt366_port_ops = {324 .inherits = &ata_bmdma_port_ops,325 .prereset = hpt366_prereset,326 .cable_detect = hpt36x_cable_detect,327 .mode_filter = hpt366_filter,328 .set_piomode = hpt366_set_piomode,329 .set_dmamode = hpt366_set_dmamode,330};331 332/**333 * hpt36x_init_chipset - common chip setup334 * @dev: PCI device335 *336 * Perform the chip setup work that must be done at both init and337 * resume time338 */339 340static void hpt36x_init_chipset(struct pci_dev *dev)341{342 u8 mcr1;343 344 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));345 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);346 pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);347 pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);348 349 /*350 * Now we'll have to force both channels enabled if at least one351 * of them has been enabled by BIOS...352 */353 pci_read_config_byte(dev, 0x50, &mcr1);354 if (mcr1 & 0x30)355 pci_write_config_byte(dev, 0x50, mcr1 | 0x30);356}357 358/**359 * hpt36x_init_one - Initialise an HPT366/368360 * @dev: PCI device361 * @id: Entry in match table362 *363 * Initialise an HPT36x device. There are some interesting complications364 * here. Firstly the chip may report 366 and be one of several variants.365 * Secondly all the timings depend on the clock for the chip which we must366 * detect and look up367 *368 * This is the known chip mappings. It may be missing a couple of later369 * releases.370 *371 * Chip version PCI Rev Notes372 * HPT366 4 (HPT366) 0 UDMA66373 * HPT366 4 (HPT366) 1 UDMA66374 * HPT368 4 (HPT366) 2 UDMA66375 * HPT37x/30x 4 (HPT366) 3+ Other driver376 *377 */378 379static int hpt36x_init_one(struct pci_dev *dev, const struct pci_device_id *id)380{381 static const struct ata_port_info info_hpt366 = {382 .flags = ATA_FLAG_SLAVE_POSS,383 .pio_mask = ATA_PIO4,384 .mwdma_mask = ATA_MWDMA2,385 .udma_mask = ATA_UDMA4,386 .port_ops = &hpt366_port_ops387 };388 const struct ata_port_info *ppi[] = { &info_hpt366, NULL };389 390 const void *hpriv = NULL;391 u32 reg1;392 int rc;393 394 rc = pcim_enable_device(dev);395 if (rc)396 return rc;397 398 /* May be a later chip in disguise. Check */399 /* Newer chips are not in the HPT36x driver. Ignore them */400 if (dev->revision > 2)401 return -ENODEV;402 403 hpt36x_init_chipset(dev);404 405 pci_read_config_dword(dev, 0x40, ®1);406 407 /* PCI clocking determines the ATA timing values to use */408 /* info_hpt366 is safe against re-entry so we can scribble on it */409 switch ((reg1 & 0xf00) >> 8) {410 case 9:411 hpriv = &hpt366_40;412 break;413 case 5:414 hpriv = &hpt366_25;415 break;416 default:417 hpriv = &hpt366_33;418 break;419 }420 /* Now kick off ATA set up */421 return ata_pci_bmdma_init_one(dev, ppi, &hpt36x_sht, (void *)hpriv, 0);422}423 424#ifdef CONFIG_PM_SLEEP425static int hpt36x_reinit_one(struct pci_dev *dev)426{427 struct ata_host *host = pci_get_drvdata(dev);428 int rc;429 430 rc = ata_pci_device_do_resume(dev);431 if (rc)432 return rc;433 hpt36x_init_chipset(dev);434 ata_host_resume(host);435 return 0;436}437#endif438 439static const struct pci_device_id hpt36x[] = {440 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT366), },441 { },442};443 444static struct pci_driver hpt36x_pci_driver = {445 .name = DRV_NAME,446 .id_table = hpt36x,447 .probe = hpt36x_init_one,448 .remove = ata_pci_remove_one,449#ifdef CONFIG_PM_SLEEP450 .suspend = ata_pci_device_suspend,451 .resume = hpt36x_reinit_one,452#endif453};454 455module_pci_driver(hpt36x_pci_driver);456 457MODULE_AUTHOR("Alan Cox");458MODULE_DESCRIPTION("low-level driver for the Highpoint HPT366/368");459MODULE_LICENSE("GPL");460MODULE_DEVICE_TABLE(pci, hpt36x);461MODULE_VERSION(DRV_VERSION);462