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1// SPDX-License-Identifier: GPL-2.0-only2/*3 * Libata based driver for Apple "macio" family of PATA controllers4 *5 * Copyright 2008/2009 Benjamin Herrenschmidt, IBM Corp6 * <benh@kernel.crashing.org>7 *8 * Some bits and pieces from drivers/ide/ppc/pmac.c9 *10 */11 12#undef DEBUG13#undef DEBUG_DMA14 15#include <linux/kernel.h>16#include <linux/module.h>17#include <linux/init.h>18#include <linux/blkdev.h>19#include <linux/ata.h>20#include <linux/libata.h>21#include <linux/adb.h>22#include <linux/pmu.h>23#include <linux/scatterlist.h>24#include <linux/irqdomain.h>25#include <linux/of.h>26#include <linux/gfp.h>27#include <linux/pci.h>28 29#include <scsi/scsi.h>30#include <scsi/scsi_host.h>31#include <scsi/scsi_device.h>32 33#include <asm/macio.h>34#include <asm/io.h>35#include <asm/dbdma.h>36#include <asm/machdep.h>37#include <asm/pmac_feature.h>38#include <asm/mediabay.h>39 40#ifdef DEBUG_DMA41#define dev_dbgdma(dev, format, arg...) \42 dev_printk(KERN_DEBUG , dev , format , ## arg)43#else44#define dev_dbgdma(dev, format, arg...) \45 ({ if (0) dev_printk(KERN_DEBUG, dev, format, ##arg); 0; })46#endif47 48#define DRV_NAME "pata_macio"49#define DRV_VERSION "0.9"50 51/* Models of macio ATA controller */52enum {53 controller_ohare, /* OHare based */54 controller_heathrow, /* Heathrow/Paddington */55 controller_kl_ata3, /* KeyLargo ATA-3 */56 controller_kl_ata4, /* KeyLargo ATA-4 */57 controller_un_ata6, /* UniNorth2 ATA-6 */58 controller_k2_ata6, /* K2 ATA-6 */59 controller_sh_ata6, /* Shasta ATA-6 */60};61 62static const char* macio_ata_names[] = {63 "OHare ATA", /* OHare based */64 "Heathrow ATA", /* Heathrow/Paddington */65 "KeyLargo ATA-3", /* KeyLargo ATA-3 (MDMA only) */66 "KeyLargo ATA-4", /* KeyLargo ATA-4 (UDMA/66) */67 "UniNorth ATA-6", /* UniNorth2 ATA-6 (UDMA/100) */68 "K2 ATA-6", /* K2 ATA-6 (UDMA/100) */69 "Shasta ATA-6", /* Shasta ATA-6 (UDMA/133) */70};71 72/*73 * Extra registers, both 32-bit little-endian74 */75#define IDE_TIMING_CONFIG 0x20076#define IDE_INTERRUPT 0x30077 78/* Kauai (U2) ATA has different register setup */79#define IDE_KAUAI_PIO_CONFIG 0x20080#define IDE_KAUAI_ULTRA_CONFIG 0x21081#define IDE_KAUAI_POLL_CONFIG 0x22082 83/*84 * Timing configuration register definitions85 */86 87/* Number of IDE_SYSCLK_NS ticks, argument is in nanoseconds */88#define SYSCLK_TICKS(t) (((t) + IDE_SYSCLK_NS - 1) / IDE_SYSCLK_NS)89#define SYSCLK_TICKS_66(t) (((t) + IDE_SYSCLK_66_NS - 1) / IDE_SYSCLK_66_NS)90#define IDE_SYSCLK_NS 30 /* 33Mhz cell */91#define IDE_SYSCLK_66_NS 15 /* 66Mhz cell */92 93/* 133Mhz cell, found in shasta.94 * See comments about 100 Mhz Uninorth 2...95 * Note that PIO_MASK and MDMA_MASK seem to overlap, that's just96 * weird and I don't now why .. at this stage97 */98#define TR_133_PIOREG_PIO_MASK 0xff000fff99#define TR_133_PIOREG_MDMA_MASK 0x00fff800100#define TR_133_UDMAREG_UDMA_MASK 0x0003ffff101#define TR_133_UDMAREG_UDMA_EN 0x00000001102 103/* 100Mhz cell, found in Uninorth 2 and K2. It appears as a pci device104 * (106b/0033) on uninorth or K2 internal PCI bus and it's clock is105 * controlled like gem or fw. It appears to be an evolution of keylargo106 * ATA4 with a timing register extended to 2x32bits registers (one107 * for PIO & MWDMA and one for UDMA, and a similar DBDMA channel.108 * It has it's own local feature control register as well.109 *110 * After scratching my mind over the timing values, at least for PIO111 * and MDMA, I think I've figured the format of the timing register,112 * though I use pre-calculated tables for UDMA as usual...113 */114#define TR_100_PIO_ADDRSETUP_MASK 0xff000000 /* Size of field unknown */115#define TR_100_PIO_ADDRSETUP_SHIFT 24116#define TR_100_MDMA_MASK 0x00fff000117#define TR_100_MDMA_RECOVERY_MASK 0x00fc0000118#define TR_100_MDMA_RECOVERY_SHIFT 18119#define TR_100_MDMA_ACCESS_MASK 0x0003f000120#define TR_100_MDMA_ACCESS_SHIFT 12121#define TR_100_PIO_MASK 0xff000fff122#define TR_100_PIO_RECOVERY_MASK 0x00000fc0123#define TR_100_PIO_RECOVERY_SHIFT 6124#define TR_100_PIO_ACCESS_MASK 0x0000003f125#define TR_100_PIO_ACCESS_SHIFT 0126 127#define TR_100_UDMAREG_UDMA_MASK 0x0000ffff128#define TR_100_UDMAREG_UDMA_EN 0x00000001129 130 131/* 66Mhz cell, found in KeyLargo. Can do ultra mode 0 to 2 on132 * 40 connector cable and to 4 on 80 connector one.133 * Clock unit is 15ns (66Mhz)134 *135 * 3 Values can be programmed:136 * - Write data setup, which appears to match the cycle time. They137 * also call it DIOW setup.138 * - Ready to pause time (from spec)139 * - Address setup. That one is weird. I don't see where exactly140 * it fits in UDMA cycles, I got it's name from an obscure piece141 * of commented out code in Darwin. They leave it to 0, we do as142 * well, despite a comment that would lead to think it has a143 * min value of 45ns.144 * Apple also add 60ns to the write data setup (or cycle time ?) on145 * reads.146 */147#define TR_66_UDMA_MASK 0xfff00000148#define TR_66_UDMA_EN 0x00100000 /* Enable Ultra mode for DMA */149#define TR_66_PIO_ADDRSETUP_MASK 0xe0000000 /* Address setup */150#define TR_66_PIO_ADDRSETUP_SHIFT 29151#define TR_66_UDMA_RDY2PAUS_MASK 0x1e000000 /* Ready 2 pause time */152#define TR_66_UDMA_RDY2PAUS_SHIFT 25153#define TR_66_UDMA_WRDATASETUP_MASK 0x01e00000 /* Write data setup time */154#define TR_66_UDMA_WRDATASETUP_SHIFT 21155#define TR_66_MDMA_MASK 0x000ffc00156#define TR_66_MDMA_RECOVERY_MASK 0x000f8000157#define TR_66_MDMA_RECOVERY_SHIFT 15158#define TR_66_MDMA_ACCESS_MASK 0x00007c00159#define TR_66_MDMA_ACCESS_SHIFT 10160#define TR_66_PIO_MASK 0xe00003ff161#define TR_66_PIO_RECOVERY_MASK 0x000003e0162#define TR_66_PIO_RECOVERY_SHIFT 5163#define TR_66_PIO_ACCESS_MASK 0x0000001f164#define TR_66_PIO_ACCESS_SHIFT 0165 166/* 33Mhz cell, found in OHare, Heathrow (& Paddington) and KeyLargo167 * Can do pio & mdma modes, clock unit is 30ns (33Mhz)168 *169 * The access time and recovery time can be programmed. Some older170 * Darwin code base limit OHare to 150ns cycle time. I decided to do171 * the same here fore safety against broken old hardware ;)172 * The HalfTick bit, when set, adds half a clock (15ns) to the access173 * time and removes one from recovery. It's not supported on KeyLargo174 * implementation afaik. The E bit appears to be set for PIO mode 0 and175 * is used to reach long timings used in this mode.176 */177#define TR_33_MDMA_MASK 0x003ff800178#define TR_33_MDMA_RECOVERY_MASK 0x001f0000179#define TR_33_MDMA_RECOVERY_SHIFT 16180#define TR_33_MDMA_ACCESS_MASK 0x0000f800181#define TR_33_MDMA_ACCESS_SHIFT 11182#define TR_33_MDMA_HALFTICK 0x00200000183#define TR_33_PIO_MASK 0x000007ff184#define TR_33_PIO_E 0x00000400185#define TR_33_PIO_RECOVERY_MASK 0x000003e0186#define TR_33_PIO_RECOVERY_SHIFT 5187#define TR_33_PIO_ACCESS_MASK 0x0000001f188#define TR_33_PIO_ACCESS_SHIFT 0189 190/*191 * Interrupt register definitions. Only present on newer cells192 * (Keylargo and later afaik) so we don't use it.193 */194#define IDE_INTR_DMA 0x80000000195#define IDE_INTR_DEVICE 0x40000000196 197/*198 * FCR Register on Kauai. Not sure what bit 0x4 is ...199 */200#define KAUAI_FCR_UATA_MAGIC 0x00000004201#define KAUAI_FCR_UATA_RESET_N 0x00000002202#define KAUAI_FCR_UATA_ENABLE 0x00000001203 204 205/* Allow up to 256 DBDMA commands per xfer */206#define MAX_DCMDS 256207 208/* Don't let a DMA segment go all the way to 64K */209#define MAX_DBDMA_SEG 0xff00210 211#ifdef CONFIG_PAGE_SIZE_64KB212/*213 * The SCSI core requires the segment size to cover at least a page, so214 * for 64K page size kernels it must be at least 64K. However the215 * hardware can't handle 64K, so pata_macio_qc_prep() will split large216 * requests. To handle the split requests the tablesize must be halved.217 */218#define PATA_MACIO_MAX_SEGMENT_SIZE SZ_64K219#define PATA_MACIO_SG_TABLESIZE (MAX_DCMDS / 2)220#else221#define PATA_MACIO_MAX_SEGMENT_SIZE MAX_DBDMA_SEG222#define PATA_MACIO_SG_TABLESIZE MAX_DCMDS223#endif224 225/*226 * Wait 1s for disk to answer on IDE bus after a hard reset227 * of the device (via GPIO/FCR).228 *229 * Some devices seem to "pollute" the bus even after dropping230 * the BSY bit (typically some combo drives slave on the UDMA231 * bus) after a hard reset. Since we hard reset all drives on232 * KeyLargo ATA66, we have to keep that delay around. I may end233 * up not hard resetting anymore on these and keep the delay only234 * for older interfaces instead (we have to reset when coming235 * from MacOS...) --BenH.236 */237#define IDE_WAKEUP_DELAY_MS 1000238 239struct pata_macio_timing;240 241struct pata_macio_priv {242 int kind;243 int aapl_bus_id;244 int mediabay : 1;245 struct device_node *node;246 struct macio_dev *mdev;247 struct pci_dev *pdev;248 struct device *dev;249 int irq;250 u32 treg[2][2];251 void __iomem *tfregs;252 void __iomem *kauai_fcr;253 struct dbdma_cmd * dma_table_cpu;254 dma_addr_t dma_table_dma;255 struct ata_host *host;256 const struct pata_macio_timing *timings;257};258 259/* Previous variants of this driver used to calculate timings260 * for various variants of the chip and use tables for others.261 *262 * Not only was this confusing, but in addition, it isn't clear263 * whether our calculation code was correct. It didn't entirely264 * match the darwin code and whatever documentation I could find265 * on these cells266 *267 * I decided to entirely rely on a table instead for this version268 * of the driver. Also, because I don't really care about derated269 * modes and really old HW other than making it work, I'm not going270 * to calculate / snoop timing values for something else than the271 * standard modes.272 */273struct pata_macio_timing {274 int mode;275 u32 reg1; /* Bits to set in first timing reg */276 u32 reg2; /* Bits to set in second timing reg */277};278 279static const struct pata_macio_timing pata_macio_ohare_timings[] = {280 { XFER_PIO_0, 0x00000526, 0, },281 { XFER_PIO_1, 0x00000085, 0, },282 { XFER_PIO_2, 0x00000025, 0, },283 { XFER_PIO_3, 0x00000025, 0, },284 { XFER_PIO_4, 0x00000025, 0, },285 { XFER_MW_DMA_0, 0x00074000, 0, },286 { XFER_MW_DMA_1, 0x00221000, 0, },287 { XFER_MW_DMA_2, 0x00211000, 0, },288 { -1, 0, 0 }289};290 291static const struct pata_macio_timing pata_macio_heathrow_timings[] = {292 { XFER_PIO_0, 0x00000526, 0, },293 { XFER_PIO_1, 0x00000085, 0, },294 { XFER_PIO_2, 0x00000025, 0, },295 { XFER_PIO_3, 0x00000025, 0, },296 { XFER_PIO_4, 0x00000025, 0, },297 { XFER_MW_DMA_0, 0x00074000, 0, },298 { XFER_MW_DMA_1, 0x00221000, 0, },299 { XFER_MW_DMA_2, 0x00211000, 0, },300 { -1, 0, 0 }301};302 303static const struct pata_macio_timing pata_macio_kl33_timings[] = {304 { XFER_PIO_0, 0x00000526, 0, },305 { XFER_PIO_1, 0x00000085, 0, },306 { XFER_PIO_2, 0x00000025, 0, },307 { XFER_PIO_3, 0x00000025, 0, },308 { XFER_PIO_4, 0x00000025, 0, },309 { XFER_MW_DMA_0, 0x00084000, 0, },310 { XFER_MW_DMA_1, 0x00021800, 0, },311 { XFER_MW_DMA_2, 0x00011800, 0, },312 { -1, 0, 0 }313};314 315static const struct pata_macio_timing pata_macio_kl66_timings[] = {316 { XFER_PIO_0, 0x0000038c, 0, },317 { XFER_PIO_1, 0x0000020a, 0, },318 { XFER_PIO_2, 0x00000127, 0, },319 { XFER_PIO_3, 0x000000c6, 0, },320 { XFER_PIO_4, 0x00000065, 0, },321 { XFER_MW_DMA_0, 0x00084000, 0, },322 { XFER_MW_DMA_1, 0x00029800, 0, },323 { XFER_MW_DMA_2, 0x00019400, 0, },324 { XFER_UDMA_0, 0x19100000, 0, },325 { XFER_UDMA_1, 0x14d00000, 0, },326 { XFER_UDMA_2, 0x10900000, 0, },327 { XFER_UDMA_3, 0x0c700000, 0, },328 { XFER_UDMA_4, 0x0c500000, 0, },329 { -1, 0, 0 }330};331 332static const struct pata_macio_timing pata_macio_kauai_timings[] = {333 { XFER_PIO_0, 0x08000a92, 0, },334 { XFER_PIO_1, 0x0800060f, 0, },335 { XFER_PIO_2, 0x0800038b, 0, },336 { XFER_PIO_3, 0x05000249, 0, },337 { XFER_PIO_4, 0x04000148, 0, },338 { XFER_MW_DMA_0, 0x00618000, 0, },339 { XFER_MW_DMA_1, 0x00209000, 0, },340 { XFER_MW_DMA_2, 0x00148000, 0, },341 { XFER_UDMA_0, 0, 0x000070c1, },342 { XFER_UDMA_1, 0, 0x00005d81, },343 { XFER_UDMA_2, 0, 0x00004a61, },344 { XFER_UDMA_3, 0, 0x00003a51, },345 { XFER_UDMA_4, 0, 0x00002a31, },346 { XFER_UDMA_5, 0, 0x00002921, },347 { -1, 0, 0 }348};349 350static const struct pata_macio_timing pata_macio_shasta_timings[] = {351 { XFER_PIO_0, 0x0a000c97, 0, },352 { XFER_PIO_1, 0x07000712, 0, },353 { XFER_PIO_2, 0x040003cd, 0, },354 { XFER_PIO_3, 0x0500028b, 0, },355 { XFER_PIO_4, 0x0400010a, 0, },356 { XFER_MW_DMA_0, 0x00820800, 0, },357 { XFER_MW_DMA_1, 0x0028b000, 0, },358 { XFER_MW_DMA_2, 0x001ca000, 0, },359 { XFER_UDMA_0, 0, 0x00035901, },360 { XFER_UDMA_1, 0, 0x000348b1, },361 { XFER_UDMA_2, 0, 0x00033881, },362 { XFER_UDMA_3, 0, 0x00033861, },363 { XFER_UDMA_4, 0, 0x00033841, },364 { XFER_UDMA_5, 0, 0x00033031, },365 { XFER_UDMA_6, 0, 0x00033021, },366 { -1, 0, 0 }367};368 369static const struct pata_macio_timing *pata_macio_find_timing(370 struct pata_macio_priv *priv,371 int mode)372{373 int i;374 375 for (i = 0; priv->timings[i].mode > 0; i++) {376 if (priv->timings[i].mode == mode)377 return &priv->timings[i];378 }379 return NULL;380}381 382 383static void pata_macio_apply_timings(struct ata_port *ap, unsigned int device)384{385 struct pata_macio_priv *priv = ap->private_data;386 void __iomem *rbase = ap->ioaddr.cmd_addr;387 388 if (priv->kind == controller_sh_ata6 ||389 priv->kind == controller_un_ata6 ||390 priv->kind == controller_k2_ata6) {391 writel(priv->treg[device][0], rbase + IDE_KAUAI_PIO_CONFIG);392 writel(priv->treg[device][1], rbase + IDE_KAUAI_ULTRA_CONFIG);393 } else394 writel(priv->treg[device][0], rbase + IDE_TIMING_CONFIG);395}396 397static void pata_macio_dev_select(struct ata_port *ap, unsigned int device)398{399 ata_sff_dev_select(ap, device);400 401 /* Apply timings */402 pata_macio_apply_timings(ap, device);403}404 405static void pata_macio_set_timings(struct ata_port *ap,406 struct ata_device *adev)407{408 struct pata_macio_priv *priv = ap->private_data;409 const struct pata_macio_timing *t;410 411 dev_dbg(priv->dev, "Set timings: DEV=%d,PIO=0x%x (%s),DMA=0x%x (%s)\n",412 adev->devno,413 adev->pio_mode,414 ata_mode_string(ata_xfer_mode2mask(adev->pio_mode)),415 adev->dma_mode,416 ata_mode_string(ata_xfer_mode2mask(adev->dma_mode)));417 418 /* First clear timings */419 priv->treg[adev->devno][0] = priv->treg[adev->devno][1] = 0;420 421 /* Now get the PIO timings */422 t = pata_macio_find_timing(priv, adev->pio_mode);423 if (t == NULL) {424 dev_warn(priv->dev, "Invalid PIO timing requested: 0x%x\n",425 adev->pio_mode);426 t = pata_macio_find_timing(priv, XFER_PIO_0);427 }428 BUG_ON(t == NULL);429 430 /* PIO timings only ever use the first treg */431 priv->treg[adev->devno][0] |= t->reg1;432 433 /* Now get DMA timings */434 t = pata_macio_find_timing(priv, adev->dma_mode);435 if (t == NULL || (t->reg1 == 0 && t->reg2 == 0)) {436 dev_dbg(priv->dev, "DMA timing not set yet, using MW_DMA_0\n");437 t = pata_macio_find_timing(priv, XFER_MW_DMA_0);438 }439 BUG_ON(t == NULL);440 441 /* DMA timings can use both tregs */442 priv->treg[adev->devno][0] |= t->reg1;443 priv->treg[adev->devno][1] |= t->reg2;444 445 dev_dbg(priv->dev, " -> %08x %08x\n",446 priv->treg[adev->devno][0],447 priv->treg[adev->devno][1]);448 449 /* Apply to hardware */450 pata_macio_apply_timings(ap, adev->devno);451}452 453/*454 * Blast some well known "safe" values to the timing registers at init or455 * wakeup from sleep time, before we do real calculation456 */457static void pata_macio_default_timings(struct pata_macio_priv *priv)458{459 unsigned int value, value2 = 0;460 461 switch(priv->kind) {462 case controller_sh_ata6:463 value = 0x0a820c97;464 value2 = 0x00033031;465 break;466 case controller_un_ata6:467 case controller_k2_ata6:468 value = 0x08618a92;469 value2 = 0x00002921;470 break;471 case controller_kl_ata4:472 value = 0x0008438c;473 break;474 case controller_kl_ata3:475 value = 0x00084526;476 break;477 case controller_heathrow:478 case controller_ohare:479 default:480 value = 0x00074526;481 break;482 }483 priv->treg[0][0] = priv->treg[1][0] = value;484 priv->treg[0][1] = priv->treg[1][1] = value2;485}486 487static int pata_macio_cable_detect(struct ata_port *ap)488{489 struct pata_macio_priv *priv = ap->private_data;490 491 /* Get cable type from device-tree */492 if (priv->kind == controller_kl_ata4 ||493 priv->kind == controller_un_ata6 ||494 priv->kind == controller_k2_ata6 ||495 priv->kind == controller_sh_ata6) {496 const char* cable = of_get_property(priv->node, "cable-type",497 NULL);498 struct device_node *root = of_find_node_by_path("/");499 const char *model = of_get_property(root, "model", NULL);500 501 of_node_put(root);502 503 if (cable && !strncmp(cable, "80-", 3)) {504 /* Some drives fail to detect 80c cable in PowerBook505 * These machine use proprietary short IDE cable506 * anyway507 */508 if (!strncmp(model, "PowerBook", 9))509 return ATA_CBL_PATA40_SHORT;510 else511 return ATA_CBL_PATA80;512 }513 }514 515 /* G5's seem to have incorrect cable type in device-tree.516 * Let's assume they always have a 80 conductor cable, this seem to517 * be always the case unless the user mucked around518 */519 if (of_device_is_compatible(priv->node, "K2-UATA") ||520 of_device_is_compatible(priv->node, "shasta-ata"))521 return ATA_CBL_PATA80;522 523 /* Anything else is 40 connectors */524 return ATA_CBL_PATA40;525}526 527static enum ata_completion_errors pata_macio_qc_prep(struct ata_queued_cmd *qc)528{529 unsigned int write = (qc->tf.flags & ATA_TFLAG_WRITE);530 struct ata_port *ap = qc->ap;531 struct pata_macio_priv *priv = ap->private_data;532 struct scatterlist *sg;533 struct dbdma_cmd *table;534 unsigned int si, pi;535 536 dev_dbgdma(priv->dev, "%s: qc %p flags %lx, write %d dev %d\n",537 __func__, qc, qc->flags, write, qc->dev->devno);538 539 if (!(qc->flags & ATA_QCFLAG_DMAMAP))540 return AC_ERR_OK;541 542 table = (struct dbdma_cmd *) priv->dma_table_cpu;543 544 pi = 0;545 for_each_sg(qc->sg, sg, qc->n_elem, si) {546 u32 addr, sg_len, len;547 548 /* determine if physical DMA addr spans 64K boundary.549 * Note h/w doesn't support 64-bit, so we unconditionally550 * truncate dma_addr_t to u32.551 */552 addr = (u32) sg_dma_address(sg);553 sg_len = sg_dma_len(sg);554 555 while (sg_len) {556 /* table overflow should never happen */557 if (WARN_ON_ONCE(pi >= MAX_DCMDS))558 return AC_ERR_SYSTEM;559 560 len = (sg_len < MAX_DBDMA_SEG) ? sg_len : MAX_DBDMA_SEG;561 table->command = cpu_to_le16(write ? OUTPUT_MORE: INPUT_MORE);562 table->req_count = cpu_to_le16(len);563 table->phy_addr = cpu_to_le32(addr);564 table->cmd_dep = 0;565 table->xfer_status = 0;566 table->res_count = 0;567 addr += len;568 sg_len -= len;569 ++table;570 ++pi;571 }572 }573 574 /* Should never happen according to Tejun */575 if (WARN_ON_ONCE(!pi))576 return AC_ERR_SYSTEM;577 578 /* Convert the last command to an input/output */579 table--;580 table->command = cpu_to_le16(write ? OUTPUT_LAST: INPUT_LAST);581 table++;582 583 /* Add the stop command to the end of the list */584 memset(table, 0, sizeof(struct dbdma_cmd));585 table->command = cpu_to_le16(DBDMA_STOP);586 587 dev_dbgdma(priv->dev, "%s: %d DMA list entries\n", __func__, pi);588 589 return AC_ERR_OK;590}591 592 593static void pata_macio_freeze(struct ata_port *ap)594{595 struct dbdma_regs __iomem *dma_regs = ap->ioaddr.bmdma_addr;596 597 if (dma_regs) {598 unsigned int timeout = 1000000;599 600 /* Make sure DMA controller is stopped */601 writel((RUN|PAUSE|FLUSH|WAKE|DEAD) << 16, &dma_regs->control);602 while (--timeout && (readl(&dma_regs->status) & RUN))603 udelay(1);604 }605 606 ata_sff_freeze(ap);607}608 609 610static void pata_macio_bmdma_setup(struct ata_queued_cmd *qc)611{612 struct ata_port *ap = qc->ap;613 struct pata_macio_priv *priv = ap->private_data;614 struct dbdma_regs __iomem *dma_regs = ap->ioaddr.bmdma_addr;615 int dev = qc->dev->devno;616 617 dev_dbgdma(priv->dev, "%s: qc %p\n", __func__, qc);618 619 /* Make sure DMA commands updates are visible */620 writel(priv->dma_table_dma, &dma_regs->cmdptr);621 622 /* On KeyLargo 66Mhz cell, we need to add 60ns to wrDataSetup on623 * UDMA reads624 */625 if (priv->kind == controller_kl_ata4 &&626 (priv->treg[dev][0] & TR_66_UDMA_EN)) {627 void __iomem *rbase = ap->ioaddr.cmd_addr;628 u32 reg = priv->treg[dev][0];629 630 if (!(qc->tf.flags & ATA_TFLAG_WRITE))631 reg += 0x00800000;632 writel(reg, rbase + IDE_TIMING_CONFIG);633 }634 635 /* issue r/w command */636 ap->ops->sff_exec_command(ap, &qc->tf);637}638 639static void pata_macio_bmdma_start(struct ata_queued_cmd *qc)640{641 struct ata_port *ap = qc->ap;642 struct pata_macio_priv *priv = ap->private_data;643 struct dbdma_regs __iomem *dma_regs = ap->ioaddr.bmdma_addr;644 645 dev_dbgdma(priv->dev, "%s: qc %p\n", __func__, qc);646 647 writel((RUN << 16) | RUN, &dma_regs->control);648 /* Make sure it gets to the controller right now */649 (void)readl(&dma_regs->control);650}651 652static void pata_macio_bmdma_stop(struct ata_queued_cmd *qc)653{654 struct ata_port *ap = qc->ap;655 struct pata_macio_priv *priv = ap->private_data;656 struct dbdma_regs __iomem *dma_regs = ap->ioaddr.bmdma_addr;657 unsigned int timeout = 1000000;658 659 dev_dbgdma(priv->dev, "%s: qc %p\n", __func__, qc);660 661 /* Stop the DMA engine and wait for it to full halt */662 writel (((RUN|WAKE|DEAD) << 16), &dma_regs->control);663 while (--timeout && (readl(&dma_regs->status) & RUN))664 udelay(1);665}666 667static u8 pata_macio_bmdma_status(struct ata_port *ap)668{669 struct pata_macio_priv *priv = ap->private_data;670 struct dbdma_regs __iomem *dma_regs = ap->ioaddr.bmdma_addr;671 u32 dstat, rstat = ATA_DMA_INTR;672 unsigned long timeout = 0;673 674 dstat = readl(&dma_regs->status);675 676 dev_dbgdma(priv->dev, "%s: dstat=%x\n", __func__, dstat);677 678 /* We have two things to deal with here:679 *680 * - The dbdma won't stop if the command was started681 * but completed with an error without transferring all682 * datas. This happens when bad blocks are met during683 * a multi-block transfer.684 *685 * - The dbdma fifo hasn't yet finished flushing to686 * system memory when the disk interrupt occurs.687 */688 689 /* First check for errors */690 if ((dstat & (RUN|DEAD)) != RUN)691 rstat |= ATA_DMA_ERR;692 693 /* If ACTIVE is cleared, the STOP command has been hit and694 * the transfer is complete. If not, we have to flush the695 * channel.696 */697 if ((dstat & ACTIVE) == 0)698 return rstat;699 700 dev_dbgdma(priv->dev, "%s: DMA still active, flushing...\n", __func__);701 702 /* If dbdma didn't execute the STOP command yet, the703 * active bit is still set. We consider that we aren't704 * sharing interrupts (which is hopefully the case with705 * those controllers) and so we just try to flush the706 * channel for pending data in the fifo707 */708 udelay(1);709 writel((FLUSH << 16) | FLUSH, &dma_regs->control);710 for (;;) {711 udelay(1);712 dstat = readl(&dma_regs->status);713 if ((dstat & FLUSH) == 0)714 break;715 if (++timeout > 1000) {716 dev_warn(priv->dev, "timeout flushing DMA\n");717 rstat |= ATA_DMA_ERR;718 break;719 }720 }721 return rstat;722}723 724/* port_start is when we allocate the DMA command list */725static int pata_macio_port_start(struct ata_port *ap)726{727 struct pata_macio_priv *priv = ap->private_data;728 729 if (ap->ioaddr.bmdma_addr == NULL)730 return 0;731 732 /* Allocate space for the DBDMA commands.733 *734 * The +2 is +1 for the stop command and +1 to allow for735 * aligning the start address to a multiple of 16 bytes.736 */737 priv->dma_table_cpu =738 dmam_alloc_coherent(priv->dev,739 (MAX_DCMDS + 2) * sizeof(struct dbdma_cmd),740 &priv->dma_table_dma, GFP_KERNEL);741 if (priv->dma_table_cpu == NULL) {742 dev_err(priv->dev, "Unable to allocate DMA command list\n");743 ap->ioaddr.bmdma_addr = NULL;744 ap->mwdma_mask = 0;745 ap->udma_mask = 0;746 }747 return 0;748}749 750static void pata_macio_irq_clear(struct ata_port *ap)751{752 struct pata_macio_priv *priv = ap->private_data;753 754 /* Nothing to do here */755 756 dev_dbgdma(priv->dev, "%s\n", __func__);757}758 759static void pata_macio_reset_hw(struct pata_macio_priv *priv, int resume)760{761 dev_dbg(priv->dev, "Enabling & resetting... \n");762 763 if (priv->mediabay)764 return;765 766 if (priv->kind == controller_ohare && !resume) {767 /* The code below is having trouble on some ohare machines768 * (timing related ?). Until I can put my hand on one of these769 * units, I keep the old way770 */771 ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, priv->node, 0, 1);772 } else {773 int rc;774 775 /* Reset and enable controller */776 rc = ppc_md.feature_call(PMAC_FTR_IDE_RESET,777 priv->node, priv->aapl_bus_id, 1);778 ppc_md.feature_call(PMAC_FTR_IDE_ENABLE,779 priv->node, priv->aapl_bus_id, 1);780 msleep(10);781 /* Only bother waiting if there's a reset control */782 if (rc == 0) {783 ppc_md.feature_call(PMAC_FTR_IDE_RESET,784 priv->node, priv->aapl_bus_id, 0);785 msleep(IDE_WAKEUP_DELAY_MS);786 }787 }788 789 /* If resuming a PCI device, restore the config space here */790 if (priv->pdev && resume) {791 int rc;792 793 pci_restore_state(priv->pdev);794 rc = pcim_enable_device(priv->pdev);795 if (rc)796 dev_err(&priv->pdev->dev,797 "Failed to enable device after resume (%d)\n",798 rc);799 else800 pci_set_master(priv->pdev);801 }802 803 /* On Kauai, initialize the FCR. We don't perform a reset, doesn't really804 * seem necessary and speeds up the boot process805 */806 if (priv->kauai_fcr)807 writel(KAUAI_FCR_UATA_MAGIC |808 KAUAI_FCR_UATA_RESET_N |809 KAUAI_FCR_UATA_ENABLE, priv->kauai_fcr);810}811 812/* Hook the standard slave config to fixup some HW related alignment813 * restrictions814 */815static int pata_macio_device_configure(struct scsi_device *sdev,816 struct queue_limits *lim)817{818 struct ata_port *ap = ata_shost_to_port(sdev->host);819 struct pata_macio_priv *priv = ap->private_data;820 struct ata_device *dev;821 u16 cmd;822 int rc;823 824 /* First call original */825 rc = ata_scsi_device_configure(sdev, lim);826 if (rc)827 return rc;828 829 /* This is lifted from sata_nv */830 dev = &ap->link.device[sdev->id];831 832 /* OHare has issues with non cache aligned DMA on some chipsets */833 if (priv->kind == controller_ohare) {834 lim->dma_alignment = 31;835 lim->dma_pad_mask = 31;836 837 /* Tell the world about it */838 ata_dev_info(dev, "OHare alignment limits applied\n");839 return 0;840 }841 842 /* We only have issues with ATAPI */843 if (dev->class != ATA_DEV_ATAPI)844 return 0;845 846 /* Shasta and K2 seem to have "issues" with reads ... */847 if (priv->kind == controller_sh_ata6 || priv->kind == controller_k2_ata6) {848 /* Allright these are bad, apply restrictions */849 lim->dma_alignment = 15;850 lim->dma_pad_mask = 15;851 852 /* We enable MWI and hack cache line size directly here, this853 * is specific to this chipset and not normal values, we happen854 * to somewhat know what we are doing here (which is basically855 * to do the same Apple does and pray they did not get it wrong :-)856 */857 BUG_ON(!priv->pdev);858 pci_write_config_byte(priv->pdev, PCI_CACHE_LINE_SIZE, 0x08);859 pci_read_config_word(priv->pdev, PCI_COMMAND, &cmd);860 pci_write_config_word(priv->pdev, PCI_COMMAND,861 cmd | PCI_COMMAND_INVALIDATE);862 863 /* Tell the world about it */864 ata_dev_info(dev, "K2/Shasta alignment limits applied\n");865 }866 867 return 0;868}869 870#ifdef CONFIG_PM_SLEEP871static int pata_macio_do_suspend(struct pata_macio_priv *priv, pm_message_t mesg)872{873 /* First, core libata suspend to do most of the work */874 ata_host_suspend(priv->host, mesg);875 876 /* Restore to default timings */877 pata_macio_default_timings(priv);878 879 /* Mask interrupt. Not strictly necessary but old driver did880 * it and I'd rather not change that here */881 disable_irq(priv->irq);882 883 /* The media bay will handle itself just fine */884 if (priv->mediabay)885 return 0;886 887 /* Kauai has bus control FCRs directly here */888 if (priv->kauai_fcr) {889 u32 fcr = readl(priv->kauai_fcr);890 fcr &= ~(KAUAI_FCR_UATA_RESET_N | KAUAI_FCR_UATA_ENABLE);891 writel(fcr, priv->kauai_fcr);892 }893 894 /* For PCI, save state and disable DMA. No need to call895 * pci_set_power_state(), the HW doesn't do D states that896 * way, the platform code will take care of suspending the897 * ASIC properly898 */899 if (priv->pdev) {900 pci_save_state(priv->pdev);901 pci_disable_device(priv->pdev);902 }903 904 /* Disable the bus on older machines and the cell on kauai */905 ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, priv->node,906 priv->aapl_bus_id, 0);907 908 return 0;909}910 911static int pata_macio_do_resume(struct pata_macio_priv *priv)912{913 /* Reset and re-enable the HW */914 pata_macio_reset_hw(priv, 1);915 916 /* Sanitize drive timings */917 pata_macio_apply_timings(priv->host->ports[0], 0);918 919 /* We want our IRQ back ! */920 enable_irq(priv->irq);921 922 /* Let the libata core take it from there */923 ata_host_resume(priv->host);924 925 return 0;926}927#endif /* CONFIG_PM_SLEEP */928 929static const struct scsi_host_template pata_macio_sht = {930 __ATA_BASE_SHT(DRV_NAME),931 .sg_tablesize = PATA_MACIO_SG_TABLESIZE,932 /* We may not need that strict one */933 .dma_boundary = ATA_DMA_BOUNDARY,934 .max_segment_size = PATA_MACIO_MAX_SEGMENT_SIZE,935 .device_configure = pata_macio_device_configure,936 .sdev_groups = ata_common_sdev_groups,937 .can_queue = ATA_DEF_QUEUE,938 .tag_alloc_policy = BLK_TAG_ALLOC_RR,939};940 941static struct ata_port_operations pata_macio_ops = {942 .inherits = &ata_bmdma_port_ops,943 944 .freeze = pata_macio_freeze,945 .set_piomode = pata_macio_set_timings,946 .set_dmamode = pata_macio_set_timings,947 .cable_detect = pata_macio_cable_detect,948 .sff_dev_select = pata_macio_dev_select,949 .qc_prep = pata_macio_qc_prep,950 .bmdma_setup = pata_macio_bmdma_setup,951 .bmdma_start = pata_macio_bmdma_start,952 .bmdma_stop = pata_macio_bmdma_stop,953 .bmdma_status = pata_macio_bmdma_status,954 .port_start = pata_macio_port_start,955 .sff_irq_clear = pata_macio_irq_clear,956};957 958static void pata_macio_invariants(struct pata_macio_priv *priv)959{960 const int *bidp;961 962 /* Identify the type of controller */963 if (of_device_is_compatible(priv->node, "shasta-ata")) {964 priv->kind = controller_sh_ata6;965 priv->timings = pata_macio_shasta_timings;966 } else if (of_device_is_compatible(priv->node, "kauai-ata")) {967 priv->kind = controller_un_ata6;968 priv->timings = pata_macio_kauai_timings;969 } else if (of_device_is_compatible(priv->node, "K2-UATA")) {970 priv->kind = controller_k2_ata6;971 priv->timings = pata_macio_kauai_timings;972 } else if (of_device_is_compatible(priv->node, "keylargo-ata")) {973 if (of_node_name_eq(priv->node, "ata-4")) {974 priv->kind = controller_kl_ata4;975 priv->timings = pata_macio_kl66_timings;976 } else {977 priv->kind = controller_kl_ata3;978 priv->timings = pata_macio_kl33_timings;979 }980 } else if (of_device_is_compatible(priv->node, "heathrow-ata")) {981 priv->kind = controller_heathrow;982 priv->timings = pata_macio_heathrow_timings;983 } else {984 priv->kind = controller_ohare;985 priv->timings = pata_macio_ohare_timings;986 }987 988 /* XXX FIXME --- setup priv->mediabay here */989 990 /* Get Apple bus ID (for clock and ASIC control) */991 bidp = of_get_property(priv->node, "AAPL,bus-id", NULL);992 priv->aapl_bus_id = bidp ? *bidp : 0;993 994 /* Fixup missing Apple bus ID in case of media-bay */995 if (priv->mediabay && !bidp)996 priv->aapl_bus_id = 1;997}998 999static void pata_macio_setup_ios(struct ata_ioports *ioaddr,1000 void __iomem * base, void __iomem * dma)1001{1002 /* cmd_addr is the base of regs for that port */1003 ioaddr->cmd_addr = base;1004 1005 /* taskfile registers */1006 ioaddr->data_addr = base + (ATA_REG_DATA << 4);1007 ioaddr->error_addr = base + (ATA_REG_ERR << 4);1008 ioaddr->feature_addr = base + (ATA_REG_FEATURE << 4);1009 ioaddr->nsect_addr = base + (ATA_REG_NSECT << 4);1010 ioaddr->lbal_addr = base + (ATA_REG_LBAL << 4);1011 ioaddr->lbam_addr = base + (ATA_REG_LBAM << 4);1012 ioaddr->lbah_addr = base + (ATA_REG_LBAH << 4);1013 ioaddr->device_addr = base + (ATA_REG_DEVICE << 4);1014 ioaddr->status_addr = base + (ATA_REG_STATUS << 4);1015 ioaddr->command_addr = base + (ATA_REG_CMD << 4);1016 ioaddr->altstatus_addr = base + 0x160;1017 ioaddr->ctl_addr = base + 0x160;1018 ioaddr->bmdma_addr = dma;1019}1020 1021static void pmac_macio_calc_timing_masks(struct pata_macio_priv *priv,1022 struct ata_port_info *pinfo)1023{1024 int i = 0;1025 1026 pinfo->pio_mask = 0;1027 pinfo->mwdma_mask = 0;1028 pinfo->udma_mask = 0;1029 1030 while (priv->timings[i].mode > 0) {1031 unsigned int mask = 1U << (priv->timings[i].mode & 0x0f);1032 switch(priv->timings[i].mode & 0xf0) {1033 case 0x00: /* PIO */1034 pinfo->pio_mask |= (mask >> 8);1035 break;1036 case 0x20: /* MWDMA */1037 pinfo->mwdma_mask |= mask;1038 break;1039 case 0x40: /* UDMA */1040 pinfo->udma_mask |= mask;1041 break;1042 }1043 i++;1044 }1045 dev_dbg(priv->dev, "Supported masks: PIO=%x, MWDMA=%x, UDMA=%x\n",1046 pinfo->pio_mask, pinfo->mwdma_mask, pinfo->udma_mask);1047}1048 1049static int pata_macio_common_init(struct pata_macio_priv *priv,1050 resource_size_t tfregs,1051 resource_size_t dmaregs,1052 resource_size_t fcregs,1053 unsigned long irq)1054{1055 struct ata_port_info pinfo;1056 const struct ata_port_info *ppi[] = { &pinfo, NULL };1057 void __iomem *dma_regs = NULL;1058 1059 /* Fill up privates with various invariants collected from the1060 * device-tree1061 */1062 pata_macio_invariants(priv);1063 1064 /* Make sure we have sane initial timings in the cache */1065 pata_macio_default_timings(priv);1066 1067 /* Allocate libata host for 1 port */1068 memset(&pinfo, 0, sizeof(struct ata_port_info));1069 pmac_macio_calc_timing_masks(priv, &pinfo);1070 pinfo.flags = ATA_FLAG_SLAVE_POSS;1071 pinfo.port_ops = &pata_macio_ops;1072 pinfo.private_data = priv;1073 1074 priv->host = ata_host_alloc_pinfo(priv->dev, ppi, 1);1075 if (priv->host == NULL) {1076 dev_err(priv->dev, "Failed to allocate ATA port structure\n");1077 return -ENOMEM;1078 }1079 1080 /* Setup the private data in host too */1081 priv->host->private_data = priv;1082 1083 /* Map base registers */1084 priv->tfregs = devm_ioremap(priv->dev, tfregs, 0x100);1085 if (priv->tfregs == NULL) {1086 dev_err(priv->dev, "Failed to map ATA ports\n");1087 return -ENOMEM;1088 }1089 priv->host->iomap = &priv->tfregs;1090 1091 /* Map DMA regs */1092 if (dmaregs != 0) {1093 dma_regs = devm_ioremap(priv->dev, dmaregs,1094 sizeof(struct dbdma_regs));1095 if (dma_regs == NULL)1096 dev_warn(priv->dev, "Failed to map ATA DMA registers\n");1097 }1098 1099 /* If chip has local feature control, map those regs too */1100 if (fcregs != 0) {1101 priv->kauai_fcr = devm_ioremap(priv->dev, fcregs, 4);1102 if (priv->kauai_fcr == NULL) {1103 dev_err(priv->dev, "Failed to map ATA FCR register\n");1104 return -ENOMEM;1105 }1106 }1107 1108 /* Setup port data structure */1109 pata_macio_setup_ios(&priv->host->ports[0]->ioaddr,1110 priv->tfregs, dma_regs);1111 priv->host->ports[0]->private_data = priv;1112 1113 /* hard-reset the controller */1114 pata_macio_reset_hw(priv, 0);1115 pata_macio_apply_timings(priv->host->ports[0], 0);1116 1117 /* Enable bus master if necessary */1118 if (priv->pdev && dma_regs)1119 pci_set_master(priv->pdev);1120 1121 dev_info(priv->dev, "Activating pata-macio chipset %s, Apple bus ID %d\n",1122 macio_ata_names[priv->kind], priv->aapl_bus_id);1123 1124 /* Start it up */1125 priv->irq = irq;1126 return ata_host_activate(priv->host, irq, ata_bmdma_interrupt, 0,1127 &pata_macio_sht);1128}1129 1130static int pata_macio_attach(struct macio_dev *mdev,1131 const struct of_device_id *match)1132{1133 struct pata_macio_priv *priv;1134 resource_size_t tfregs, dmaregs = 0;1135 unsigned long irq;1136 int rc;1137 1138 /* Check for broken device-trees */1139 if (macio_resource_count(mdev) == 0) {1140 dev_err(&mdev->ofdev.dev,1141 "No addresses for controller\n");1142 return -ENXIO;1143 }1144 1145 /* Enable managed resources */1146 macio_enable_devres(mdev);1147 1148 /* Allocate and init private data structure */1149 priv = devm_kzalloc(&mdev->ofdev.dev,1150 sizeof(struct pata_macio_priv), GFP_KERNEL);1151 if (!priv)1152 return -ENOMEM;1153 1154 priv->node = of_node_get(mdev->ofdev.dev.of_node);1155 priv->mdev = mdev;1156 priv->dev = &mdev->ofdev.dev;1157 1158 /* Request memory resource for taskfile registers */1159 if (macio_request_resource(mdev, 0, "pata-macio")) {1160 dev_err(&mdev->ofdev.dev,1161 "Cannot obtain taskfile resource\n");1162 return -EBUSY;1163 }1164 tfregs = macio_resource_start(mdev, 0);1165 1166 /* Request resources for DMA registers if any */1167 if (macio_resource_count(mdev) >= 2) {1168 if (macio_request_resource(mdev, 1, "pata-macio-dma"))1169 dev_err(&mdev->ofdev.dev,1170 "Cannot obtain DMA resource\n");1171 else1172 dmaregs = macio_resource_start(mdev, 1);1173 }1174 1175 /*1176 * Fixup missing IRQ for some old implementations with broken1177 * device-trees.1178 *1179 * This is a bit bogus, it should be fixed in the device-tree itself,1180 * via the existing macio fixups, based on the type of interrupt1181 * controller in the machine. However, I have no test HW for this case,1182 * and this trick works well enough on those old machines...1183 */1184 if (macio_irq_count(mdev) == 0) {1185 dev_warn(&mdev->ofdev.dev,1186 "No interrupts for controller, using 13\n");1187 irq = irq_create_mapping(NULL, 13);1188 } else1189 irq = macio_irq(mdev, 0);1190 1191 /* Prevvent media bay callbacks until fully registered */1192 lock_media_bay(priv->mdev->media_bay);1193 1194 /* Get register addresses and call common initialization */1195 rc = pata_macio_common_init(priv,1196 tfregs, /* Taskfile regs */1197 dmaregs, /* DBDMA regs */1198 0, /* Feature control */1199 irq);1200 unlock_media_bay(priv->mdev->media_bay);1201 1202 return rc;1203}1204 1205static void pata_macio_detach(struct macio_dev *mdev)1206{1207 struct ata_host *host = macio_get_drvdata(mdev);1208 struct pata_macio_priv *priv = host->private_data;1209 1210 lock_media_bay(priv->mdev->media_bay);1211 1212 /* Make sure the mediabay callback doesn't try to access1213 * dead stuff1214 */1215 priv->host->private_data = NULL;1216 1217 ata_host_detach(host);1218 1219 unlock_media_bay(priv->mdev->media_bay);1220}1221 1222#ifdef CONFIG_PM_SLEEP1223static int pata_macio_suspend(struct macio_dev *mdev, pm_message_t mesg)1224{1225 struct ata_host *host = macio_get_drvdata(mdev);1226 1227 return pata_macio_do_suspend(host->private_data, mesg);1228}1229 1230static int pata_macio_resume(struct macio_dev *mdev)1231{1232 struct ata_host *host = macio_get_drvdata(mdev);1233 1234 return pata_macio_do_resume(host->private_data);1235}1236#endif /* CONFIG_PM_SLEEP */1237 1238#ifdef CONFIG_PMAC_MEDIABAY1239static void pata_macio_mb_event(struct macio_dev* mdev, int mb_state)1240{1241 struct ata_host *host = macio_get_drvdata(mdev);1242 struct ata_port *ap;1243 struct ata_eh_info *ehi;1244 struct ata_device *dev;1245 unsigned long flags;1246 1247 if (!host || !host->private_data)1248 return;1249 ap = host->ports[0];1250 spin_lock_irqsave(ap->lock, flags);1251 ehi = &ap->link.eh_info;1252 if (mb_state == MB_CD) {1253 ata_ehi_push_desc(ehi, "mediabay plug");1254 ata_ehi_hotplugged(ehi);1255 ata_port_freeze(ap);1256 } else {1257 ata_ehi_push_desc(ehi, "mediabay unplug");1258 ata_for_each_dev(dev, &ap->link, ALL)1259 dev->flags |= ATA_DFLAG_DETACH;1260 ata_port_abort(ap);1261 }1262 spin_unlock_irqrestore(ap->lock, flags);1263 1264}1265#endif /* CONFIG_PMAC_MEDIABAY */1266 1267 1268static int pata_macio_pci_attach(struct pci_dev *pdev,1269 const struct pci_device_id *id)1270{1271 struct pata_macio_priv *priv;1272 struct device_node *np;1273 resource_size_t rbase;1274 1275 /* We cannot use a MacIO controller without its OF device node */1276 np = pci_device_to_OF_node(pdev);1277 if (np == NULL) {1278 dev_err(&pdev->dev,1279 "Cannot find OF device node for controller\n");1280 return -ENODEV;1281 }1282 1283 /* Check that it can be enabled */1284 if (pcim_enable_device(pdev)) {1285 dev_err(&pdev->dev,1286 "Cannot enable controller PCI device\n");1287 return -ENXIO;1288 }1289 1290 /* Allocate and init private data structure */1291 priv = devm_kzalloc(&pdev->dev,1292 sizeof(struct pata_macio_priv), GFP_KERNEL);1293 if (!priv)1294 return -ENOMEM;1295 1296 priv->node = of_node_get(np);1297 priv->pdev = pdev;1298 priv->dev = &pdev->dev;1299 1300 /* Get MMIO regions */1301 if (pci_request_regions(pdev, "pata-macio")) {1302 dev_err(&pdev->dev,1303 "Cannot obtain PCI resources\n");1304 return -EBUSY;1305 }1306 1307 /* Get register addresses and call common initialization */1308 rbase = pci_resource_start(pdev, 0);1309 if (pata_macio_common_init(priv,1310 rbase + 0x2000, /* Taskfile regs */1311 rbase + 0x1000, /* DBDMA regs */1312 rbase, /* Feature control */1313 pdev->irq))1314 return -ENXIO;1315 1316 return 0;1317}1318 1319static void pata_macio_pci_detach(struct pci_dev *pdev)1320{1321 struct ata_host *host = pci_get_drvdata(pdev);1322 1323 ata_host_detach(host);1324}1325 1326#ifdef CONFIG_PM_SLEEP1327static int pata_macio_pci_suspend(struct pci_dev *pdev, pm_message_t mesg)1328{1329 struct ata_host *host = pci_get_drvdata(pdev);1330 1331 return pata_macio_do_suspend(host->private_data, mesg);1332}1333 1334static int pata_macio_pci_resume(struct pci_dev *pdev)1335{1336 struct ata_host *host = pci_get_drvdata(pdev);1337 1338 return pata_macio_do_resume(host->private_data);1339}1340#endif /* CONFIG_PM_SLEEP */1341 1342static const struct of_device_id pata_macio_match[] =1343{1344 { .name = "IDE", },1345 { .name = "ATA", },1346 { .type = "ide", },1347 { .type = "ata", },1348 { /* sentinel */ }1349};1350MODULE_DEVICE_TABLE(of, pata_macio_match);1351 1352static struct macio_driver pata_macio_driver =1353{1354 .driver = {1355 .name = "pata-macio",1356 .owner = THIS_MODULE,1357 .of_match_table = pata_macio_match,1358 },1359 .probe = pata_macio_attach,1360 .remove = pata_macio_detach,1361#ifdef CONFIG_PM_SLEEP1362 .suspend = pata_macio_suspend,1363 .resume = pata_macio_resume,1364#endif1365#ifdef CONFIG_PMAC_MEDIABAY1366 .mediabay_event = pata_macio_mb_event,1367#endif1368};1369 1370static const struct pci_device_id pata_macio_pci_match[] = {1371 { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_UNI_N_ATA), 0 },1372 { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_IPID_ATA100), 0 },1373 { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_K2_ATA100), 0 },1374 { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_SH_ATA), 0 },1375 { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_IPID2_ATA), 0 },1376 {},1377};1378 1379static struct pci_driver pata_macio_pci_driver = {1380 .name = "pata-pci-macio",1381 .id_table = pata_macio_pci_match,1382 .probe = pata_macio_pci_attach,1383 .remove = pata_macio_pci_detach,1384#ifdef CONFIG_PM_SLEEP1385 .suspend = pata_macio_pci_suspend,1386 .resume = pata_macio_pci_resume,1387#endif1388};1389MODULE_DEVICE_TABLE(pci, pata_macio_pci_match);1390 1391 1392static int __init pata_macio_init(void)1393{1394 int rc;1395 1396 if (!machine_is(powermac))1397 return -ENODEV;1398 1399 rc = pci_register_driver(&pata_macio_pci_driver);1400 if (rc)1401 return rc;1402 rc = macio_register_driver(&pata_macio_driver);1403 if (rc) {1404 pci_unregister_driver(&pata_macio_pci_driver);1405 return rc;1406 }1407 return 0;1408}1409 1410static void __exit pata_macio_exit(void)1411{1412 macio_unregister_driver(&pata_macio_driver);1413 pci_unregister_driver(&pata_macio_pci_driver);1414}1415 1416module_init(pata_macio_init);1417module_exit(pata_macio_exit);1418 1419MODULE_AUTHOR("Benjamin Herrenschmidt");1420MODULE_DESCRIPTION("Apple MacIO PATA driver");1421MODULE_LICENSE("GPL");1422MODULE_VERSION(DRV_VERSION);1423