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1// SPDX-License-Identifier: GPL-2.0-only2/*3 * pata_oldpiix.c - Intel PATA/SATA controllers4 *5 * (C) 2005 Red Hat6 *7 * Some parts based on ata_piix.c by Jeff Garzik and others.8 *9 * Early PIIX differs significantly from the later PIIX as it lacks10 * SITRE and the slave timing registers. This means that you have to11 * set timing per channel, or be clever. Libata tells us whenever it12 * does drive selection and we use this to reload the timings.13 *14 * Because of these behaviour differences PIIX gets its own driver module.15 */16 17#include <linux/kernel.h>18#include <linux/module.h>19#include <linux/pci.h>20#include <linux/blkdev.h>21#include <linux/delay.h>22#include <linux/device.h>23#include <scsi/scsi_host.h>24#include <linux/libata.h>25#include <linux/ata.h>26 27#define DRV_NAME "pata_oldpiix"28#define DRV_VERSION "0.5.5"29 30/**31 * oldpiix_pre_reset - probe begin32 * @link: ATA link33 * @deadline: deadline jiffies for the operation34 *35 * Set up cable type and use generic probe init36 */37 38static int oldpiix_pre_reset(struct ata_link *link, unsigned long deadline)39{40 struct ata_port *ap = link->ap;41 struct pci_dev *pdev = to_pci_dev(ap->host->dev);42 static const struct pci_bits oldpiix_enable_bits[] = {43 { 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */44 { 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */45 };46 47 if (!pci_test_config_bits(pdev, &oldpiix_enable_bits[ap->port_no]))48 return -ENOENT;49 50 return ata_sff_prereset(link, deadline);51}52 53/**54 * oldpiix_set_piomode - Initialize host controller PATA PIO timings55 * @ap: Port whose timings we are configuring56 * @adev: Device whose timings we are configuring57 *58 * Set PIO mode for device, in host controller PCI config space.59 *60 * LOCKING:61 * None (inherited from caller).62 */63 64static void oldpiix_set_piomode (struct ata_port *ap, struct ata_device *adev)65{66 unsigned int pio = adev->pio_mode - XFER_PIO_0;67 struct pci_dev *dev = to_pci_dev(ap->host->dev);68 unsigned int idetm_port= ap->port_no ? 0x42 : 0x40;69 u16 idetm_data;70 int control = 0;71 72 /*73 * See Intel Document 298600-004 for the timing programing rules74 * for PIIX/ICH. Note that the early PIIX does not have the slave75 * timing port at 0x44.76 */77 78 static const /* ISP RTC */79 u8 timings[][2] = { { 0, 0 },80 { 0, 0 },81 { 1, 0 },82 { 2, 1 },83 { 2, 3 }, };84 85 if (pio > 1)86 control |= 1; /* TIME */87 if (ata_pio_need_iordy(adev))88 control |= 2; /* IE */89 90 /* Intel specifies that the prefetch/posting is for disk only */91 if (adev->class == ATA_DEV_ATA)92 control |= 4; /* PPE */93 94 pci_read_config_word(dev, idetm_port, &idetm_data);95 96 /*97 * Set PPE, IE and TIME as appropriate.98 * Clear the other drive's timing bits.99 */100 if (adev->devno == 0) {101 idetm_data &= 0xCCE0;102 idetm_data |= control;103 } else {104 idetm_data &= 0xCC0E;105 idetm_data |= (control << 4);106 }107 idetm_data |= (timings[pio][0] << 12) |108 (timings[pio][1] << 8);109 pci_write_config_word(dev, idetm_port, idetm_data);110 111 /* Track which port is configured */112 ap->private_data = adev;113}114 115/**116 * oldpiix_set_dmamode - Initialize host controller PATA DMA timings117 * @ap: Port whose timings we are configuring118 * @adev: Device to program119 *120 * Set MWDMA mode for device, in host controller PCI config space.121 *122 * LOCKING:123 * None (inherited from caller).124 */125 126static void oldpiix_set_dmamode (struct ata_port *ap, struct ata_device *adev)127{128 struct pci_dev *dev = to_pci_dev(ap->host->dev);129 u8 idetm_port = ap->port_no ? 0x42 : 0x40;130 u16 idetm_data;131 132 static const /* ISP RTC */133 u8 timings[][2] = { { 0, 0 },134 { 0, 0 },135 { 1, 0 },136 { 2, 1 },137 { 2, 3 }, };138 139 /*140 * MWDMA is driven by the PIO timings. We must also enable141 * IORDY unconditionally along with TIME1. PPE has already142 * been set when the PIO timing was set.143 */144 145 unsigned int mwdma = adev->dma_mode - XFER_MW_DMA_0;146 unsigned int control;147 const unsigned int needed_pio[3] = {148 XFER_PIO_0, XFER_PIO_3, XFER_PIO_4149 };150 int pio = needed_pio[mwdma] - XFER_PIO_0;151 152 pci_read_config_word(dev, idetm_port, &idetm_data);153 154 control = 3; /* IORDY|TIME0 */155 /* Intel specifies that the PPE functionality is for disk only */156 if (adev->class == ATA_DEV_ATA)157 control |= 4; /* PPE enable */158 159 /* If the drive MWDMA is faster than it can do PIO then160 we must force PIO into PIO0 */161 162 if (adev->pio_mode < needed_pio[mwdma])163 /* Enable DMA timing only */164 control |= 8; /* PIO cycles in PIO0 */165 166 /* Mask out the relevant control and timing bits we will load. Also167 clear the other drive TIME register as a precaution */168 if (adev->devno == 0) {169 idetm_data &= 0xCCE0;170 idetm_data |= control;171 } else {172 idetm_data &= 0xCC0E;173 idetm_data |= (control << 4);174 }175 idetm_data |= (timings[pio][0] << 12) | (timings[pio][1] << 8);176 pci_write_config_word(dev, idetm_port, idetm_data);177 178 /* Track which port is configured */179 ap->private_data = adev;180}181 182/**183 * oldpiix_qc_issue - command issue184 * @qc: command pending185 *186 * Called when the libata layer is about to issue a command. We wrap187 * this interface so that we can load the correct ATA timings if188 * necessary. Our logic also clears TIME0/TIME1 for the other device so189 * that, even if we get this wrong, cycles to the other device will190 * be made PIO0.191 */192 193static unsigned int oldpiix_qc_issue(struct ata_queued_cmd *qc)194{195 struct ata_port *ap = qc->ap;196 struct ata_device *adev = qc->dev;197 198 if (adev != ap->private_data) {199 oldpiix_set_piomode(ap, adev);200 if (ata_dma_enabled(adev))201 oldpiix_set_dmamode(ap, adev);202 }203 return ata_bmdma_qc_issue(qc);204}205 206 207static const struct scsi_host_template oldpiix_sht = {208 ATA_BMDMA_SHT(DRV_NAME),209};210 211static struct ata_port_operations oldpiix_pata_ops = {212 .inherits = &ata_bmdma_port_ops,213 .qc_issue = oldpiix_qc_issue,214 .cable_detect = ata_cable_40wire,215 .set_piomode = oldpiix_set_piomode,216 .set_dmamode = oldpiix_set_dmamode,217 .prereset = oldpiix_pre_reset,218};219 220 221/**222 * oldpiix_init_one - Register PIIX ATA PCI device with kernel services223 * @pdev: PCI device to register224 * @ent: Entry in oldpiix_pci_tbl matching with @pdev225 *226 * Called from kernel PCI layer. We probe for combined mode (sigh),227 * and then hand over control to libata, for it to do the rest.228 *229 * LOCKING:230 * Inherited from PCI layer (may sleep).231 *232 * RETURNS:233 * Zero on success, or -ERRNO value.234 */235 236static int oldpiix_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)237{238 static const struct ata_port_info info = {239 .flags = ATA_FLAG_SLAVE_POSS,240 .pio_mask = ATA_PIO4,241 .mwdma_mask = ATA_MWDMA12_ONLY,242 .port_ops = &oldpiix_pata_ops,243 };244 const struct ata_port_info *ppi[] = { &info, NULL };245 246 ata_print_version_once(&pdev->dev, DRV_VERSION);247 248 return ata_pci_bmdma_init_one(pdev, ppi, &oldpiix_sht, NULL, 0);249}250 251static const struct pci_device_id oldpiix_pci_tbl[] = {252 { PCI_VDEVICE(INTEL, 0x1230), },253 254 { } /* terminate list */255};256 257static struct pci_driver oldpiix_pci_driver = {258 .name = DRV_NAME,259 .id_table = oldpiix_pci_tbl,260 .probe = oldpiix_init_one,261 .remove = ata_pci_remove_one,262#ifdef CONFIG_PM_SLEEP263 .suspend = ata_pci_device_suspend,264 .resume = ata_pci_device_resume,265#endif266};267 268module_pci_driver(oldpiix_pci_driver);269 270MODULE_AUTHOR("Alan Cox");271MODULE_DESCRIPTION("SCSI low-level driver for early PIIX series controllers");272MODULE_LICENSE("GPL");273MODULE_DEVICE_TABLE(pci, oldpiix_pci_tbl);274MODULE_VERSION(DRV_VERSION);275