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1/*2 * pata_sil680.c - SIL680 PATA for new ATA layer3 * (C) 2005 Red Hat Inc4 *5 * based upon6 *7 * linux/drivers/ide/pci/siimage.c Version 1.07 Nov 30, 20038 *9 * Copyright (C) 2001-2002 Andre Hedrick <andre@linux-ide.org>10 * Copyright (C) 2003 Red Hat <alan@redhat.com>11 *12 * May be copied or modified under the terms of the GNU General Public License13 *14 * Documentation publicly available.15 *16 * If you have strange problems with nVidia chipset systems please17 * see the SI support documentation and update your system BIOS18 * if necessary19 *20 * TODO21 * If we know all our devices are LBA28 (or LBA28 sized) we could use22 * the command fifo mode.23 */24 25#include <linux/kernel.h>26#include <linux/module.h>27#include <linux/pci.h>28#include <linux/blkdev.h>29#include <linux/delay.h>30#include <scsi/scsi_host.h>31#include <linux/libata.h>32 33#define DRV_NAME "pata_sil680"34#define DRV_VERSION "0.4.9"35 36#define SIL680_MMIO_BAR 537 38/**39 * sil680_selreg - return register base40 * @ap: ATA interface41 * @r: config offset42 *43 * Turn a config register offset into the right address in PCI space44 * to access the control register in question.45 *46 * Thankfully this is a configuration operation so isn't performance47 * criticial.48 */49 50static int sil680_selreg(struct ata_port *ap, int r)51{52 return 0xA0 + (ap->port_no << 4) + r;53}54 55/**56 * sil680_seldev - return register base57 * @ap: ATA interface58 * @adev: ATA device59 * @r: config offset60 *61 * Turn a config register offset into the right address in PCI space62 * to access the control register in question including accounting for63 * the unit shift.64 */65 66static int sil680_seldev(struct ata_port *ap, struct ata_device *adev, int r)67{68 return 0xA0 + (ap->port_no << 4) + r + (adev->devno << 1);69}70 71 72/**73 * sil680_cable_detect - cable detection74 * @ap: ATA port75 *76 * Perform cable detection. The SIL680 stores this in PCI config77 * space for us.78 */79 80static int sil680_cable_detect(struct ata_port *ap)81{82 struct pci_dev *pdev = to_pci_dev(ap->host->dev);83 int addr = sil680_selreg(ap, 0);84 u8 ata66;85 86 pci_read_config_byte(pdev, addr, &ata66);87 if (ata66 & 1)88 return ATA_CBL_PATA80;89 else90 return ATA_CBL_PATA40;91}92 93/**94 * sil680_set_piomode - set PIO mode data95 * @ap: ATA interface96 * @adev: ATA device97 *98 * Program the SIL680 registers for PIO mode. Note that the task speed99 * registers are shared between the devices so we must pick the lowest100 * mode for command work.101 */102 103static void sil680_set_piomode(struct ata_port *ap, struct ata_device *adev)104{105 static const u16 speed_p[5] = {106 0x328A, 0x2283, 0x1104, 0x10C3, 0x10C1107 };108 static const u16 speed_t[5] = {109 0x328A, 0x2283, 0x1281, 0x10C3, 0x10C1110 };111 112 int tfaddr = sil680_selreg(ap, 0x02);113 int addr = sil680_seldev(ap, adev, 0x04);114 int addr_mask = 0x80 + 4 * ap->port_no;115 struct pci_dev *pdev = to_pci_dev(ap->host->dev);116 int pio = adev->pio_mode - XFER_PIO_0;117 int lowest_pio = pio;118 int port_shift = 4 * adev->devno;119 u16 reg;120 u8 mode;121 122 struct ata_device *pair = ata_dev_pair(adev);123 124 if (pair != NULL && adev->pio_mode > pair->pio_mode)125 lowest_pio = pair->pio_mode - XFER_PIO_0;126 127 pci_write_config_word(pdev, addr, speed_p[pio]);128 pci_write_config_word(pdev, tfaddr, speed_t[lowest_pio]);129 130 pci_read_config_word(pdev, tfaddr-2, ®);131 pci_read_config_byte(pdev, addr_mask, &mode);132 133 reg &= ~0x0200; /* Clear IORDY */134 mode &= ~(3 << port_shift); /* Clear IORDY and DMA bits */135 136 if (ata_pio_need_iordy(adev)) {137 reg |= 0x0200; /* Enable IORDY */138 mode |= 1 << port_shift;139 }140 pci_write_config_word(pdev, tfaddr-2, reg);141 pci_write_config_byte(pdev, addr_mask, mode);142}143 144/**145 * sil680_set_dmamode - set DMA mode data146 * @ap: ATA interface147 * @adev: ATA device148 *149 * Program the MWDMA/UDMA modes for the sil680 chipset.150 *151 * The MWDMA mode values are pulled from a lookup table152 * while the chipset uses mode number for UDMA.153 */154 155static void sil680_set_dmamode(struct ata_port *ap, struct ata_device *adev)156{157 static const u8 ultra_table[2][7] = {158 { 0x0C, 0x07, 0x05, 0x04, 0x02, 0x01, 0xFF }, /* 100MHz */159 { 0x0F, 0x0B, 0x07, 0x05, 0x03, 0x02, 0x01 }, /* 133Mhz */160 };161 static const u16 dma_table[3] = { 0x2208, 0x10C2, 0x10C1 };162 163 struct pci_dev *pdev = to_pci_dev(ap->host->dev);164 int ma = sil680_seldev(ap, adev, 0x08);165 int ua = sil680_seldev(ap, adev, 0x0C);166 int addr_mask = 0x80 + 4 * ap->port_no;167 int port_shift = adev->devno * 4;168 u8 scsc, mode;169 u16 multi, ultra;170 171 pci_read_config_byte(pdev, 0x8A, &scsc);172 pci_read_config_byte(pdev, addr_mask, &mode);173 pci_read_config_word(pdev, ma, &multi);174 pci_read_config_word(pdev, ua, &ultra);175 176 /* Mask timing bits */177 ultra &= ~0x3F;178 mode &= ~(0x03 << port_shift);179 180 /* Extract scsc */181 scsc = (scsc & 0x30) ? 1 : 0;182 183 if (adev->dma_mode >= XFER_UDMA_0) {184 multi = 0x10C1;185 ultra |= ultra_table[scsc][adev->dma_mode - XFER_UDMA_0];186 mode |= (0x03 << port_shift);187 } else {188 multi = dma_table[adev->dma_mode - XFER_MW_DMA_0];189 mode |= (0x02 << port_shift);190 }191 pci_write_config_byte(pdev, addr_mask, mode);192 pci_write_config_word(pdev, ma, multi);193 pci_write_config_word(pdev, ua, ultra);194}195 196/**197 * sil680_sff_exec_command - issue ATA command to host controller198 * @ap: port to which command is being issued199 * @tf: ATA taskfile register set200 *201 * Issues ATA command, with proper synchronization with interrupt202 * handler / other threads. Use our MMIO space for PCI posting to avoid203 * a hideously slow cycle all the way to the device.204 *205 * LOCKING:206 * spin_lock_irqsave(host lock)207 */208static void sil680_sff_exec_command(struct ata_port *ap,209 const struct ata_taskfile *tf)210{211 iowrite8(tf->command, ap->ioaddr.command_addr);212 ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD);213}214 215static bool sil680_sff_irq_check(struct ata_port *ap)216{217 struct pci_dev *pdev = to_pci_dev(ap->host->dev);218 int addr = sil680_selreg(ap, 1);219 u8 val;220 221 pci_read_config_byte(pdev, addr, &val);222 223 return val & 0x08;224}225 226static const struct scsi_host_template sil680_sht = {227 ATA_BMDMA_SHT(DRV_NAME),228};229 230 231static struct ata_port_operations sil680_port_ops = {232 .inherits = &ata_bmdma32_port_ops,233 .sff_exec_command = sil680_sff_exec_command,234 .sff_irq_check = sil680_sff_irq_check,235 .cable_detect = sil680_cable_detect,236 .set_piomode = sil680_set_piomode,237 .set_dmamode = sil680_set_dmamode,238};239 240/**241 * sil680_init_chip - chip setup242 * @pdev: PCI device243 * @try_mmio: Indicates to caller whether MMIO should be attempted244 *245 * Perform all the chip setup which must be done both when the device246 * is powered up on boot and when we resume in case we resumed from RAM.247 * Returns the final clock settings.248 */249 250static u8 sil680_init_chip(struct pci_dev *pdev, int *try_mmio)251{252 u8 tmpbyte = 0;253 254 /* FIXME: double check */255 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE,256 pdev->revision ? 1 : 255);257 258 pci_write_config_byte(pdev, 0x80, 0x00);259 pci_write_config_byte(pdev, 0x84, 0x00);260 261 pci_read_config_byte(pdev, 0x8A, &tmpbyte);262 263 dev_dbg(&pdev->dev, "sil680: BA5_EN = %d clock = %02X\n",264 tmpbyte & 1, tmpbyte & 0x30);265 266 *try_mmio = 0;267#ifdef CONFIG_PPC268 if (machine_is(cell))269 *try_mmio = (tmpbyte & 1) || pci_resource_start(pdev, 5);270#endif271 272 switch (tmpbyte & 0x30) {273 case 0x00:274 /* 133 clock attempt to force it on */275 pci_write_config_byte(pdev, 0x8A, tmpbyte|0x10);276 break;277 case 0x30:278 /* if clocking is disabled */279 /* 133 clock attempt to force it on */280 pci_write_config_byte(pdev, 0x8A, tmpbyte & ~0x20);281 break;282 case 0x10:283 /* 133 already */284 break;285 case 0x20:286 /* BIOS set PCI x2 clocking */287 break;288 }289 290 pci_read_config_byte(pdev, 0x8A, &tmpbyte);291 dev_dbg(&pdev->dev, "sil680: BA5_EN = %d clock = %02X\n",292 tmpbyte & 1, tmpbyte & 0x30);293 294 pci_write_config_byte(pdev, 0xA1, 0x72);295 pci_write_config_word(pdev, 0xA2, 0x328A);296 pci_write_config_dword(pdev, 0xA4, 0x62DD62DD);297 pci_write_config_dword(pdev, 0xA8, 0x43924392);298 pci_write_config_dword(pdev, 0xAC, 0x40094009);299 pci_write_config_byte(pdev, 0xB1, 0x72);300 pci_write_config_word(pdev, 0xB2, 0x328A);301 pci_write_config_dword(pdev, 0xB4, 0x62DD62DD);302 pci_write_config_dword(pdev, 0xB8, 0x43924392);303 pci_write_config_dword(pdev, 0xBC, 0x40094009);304 305 switch (tmpbyte & 0x30) {306 case 0x00:307 dev_info(&pdev->dev, "sil680: 100MHz clock.\n");308 break;309 case 0x10:310 dev_info(&pdev->dev, "sil680: 133MHz clock.\n");311 break;312 case 0x20:313 dev_info(&pdev->dev, "sil680: Using PCI clock.\n");314 break;315 /* This last case is _NOT_ ok */316 case 0x30:317 dev_err(&pdev->dev, "sil680: Clock disabled ?\n");318 }319 return tmpbyte & 0x30;320}321 322static int sil680_init_one(struct pci_dev *pdev, const struct pci_device_id *id)323{324 static const struct ata_port_info info = {325 .flags = ATA_FLAG_SLAVE_POSS,326 .pio_mask = ATA_PIO4,327 .mwdma_mask = ATA_MWDMA2,328 .udma_mask = ATA_UDMA6,329 .port_ops = &sil680_port_ops330 };331 static const struct ata_port_info info_slow = {332 .flags = ATA_FLAG_SLAVE_POSS,333 .pio_mask = ATA_PIO4,334 .mwdma_mask = ATA_MWDMA2,335 .udma_mask = ATA_UDMA5,336 .port_ops = &sil680_port_ops337 };338 const struct ata_port_info *ppi[] = { &info, NULL };339 struct ata_host *host;340 void __iomem *mmio_base;341 int rc, try_mmio;342 343 ata_print_version_once(&pdev->dev, DRV_VERSION);344 345 rc = pcim_enable_device(pdev);346 if (rc)347 return rc;348 349 switch (sil680_init_chip(pdev, &try_mmio)) {350 case 0:351 ppi[0] = &info_slow;352 break;353 case 0x30:354 return -ENODEV;355 }356 357 if (!try_mmio)358 goto use_ioports;359 360 /* Try to acquire MMIO resources and fallback to PIO if361 * that fails362 */363 rc = pcim_iomap_regions(pdev, 1 << SIL680_MMIO_BAR, DRV_NAME);364 if (rc)365 goto use_ioports;366 367 /* Allocate host and set it up */368 host = ata_host_alloc_pinfo(&pdev->dev, ppi, 2);369 if (!host)370 return -ENOMEM;371 host->iomap = pcim_iomap_table(pdev);372 373 /* Setup DMA masks */374 rc = dma_set_mask_and_coherent(&pdev->dev, ATA_DMA_MASK);375 if (rc)376 return rc;377 pci_set_master(pdev);378 379 /* Get MMIO base and initialize port addresses */380 mmio_base = host->iomap[SIL680_MMIO_BAR];381 host->ports[0]->ioaddr.bmdma_addr = mmio_base + 0x00;382 host->ports[0]->ioaddr.cmd_addr = mmio_base + 0x80;383 host->ports[0]->ioaddr.ctl_addr = mmio_base + 0x8a;384 host->ports[0]->ioaddr.altstatus_addr = mmio_base + 0x8a;385 ata_sff_std_ports(&host->ports[0]->ioaddr);386 host->ports[1]->ioaddr.bmdma_addr = mmio_base + 0x08;387 host->ports[1]->ioaddr.cmd_addr = mmio_base + 0xc0;388 host->ports[1]->ioaddr.ctl_addr = mmio_base + 0xca;389 host->ports[1]->ioaddr.altstatus_addr = mmio_base + 0xca;390 ata_sff_std_ports(&host->ports[1]->ioaddr);391 392 /* Register & activate */393 return ata_host_activate(host, pdev->irq, ata_bmdma_interrupt,394 IRQF_SHARED, &sil680_sht);395 396use_ioports:397 return ata_pci_bmdma_init_one(pdev, ppi, &sil680_sht, NULL, 0);398}399 400#ifdef CONFIG_PM_SLEEP401static int sil680_reinit_one(struct pci_dev *pdev)402{403 struct ata_host *host = pci_get_drvdata(pdev);404 int try_mmio, rc;405 406 rc = ata_pci_device_do_resume(pdev);407 if (rc)408 return rc;409 sil680_init_chip(pdev, &try_mmio);410 ata_host_resume(host);411 return 0;412}413#endif414 415static const struct pci_device_id sil680[] = {416 { PCI_VDEVICE(CMD, PCI_DEVICE_ID_SII_680), },417 418 { },419};420 421static struct pci_driver sil680_pci_driver = {422 .name = DRV_NAME,423 .id_table = sil680,424 .probe = sil680_init_one,425 .remove = ata_pci_remove_one,426#ifdef CONFIG_PM_SLEEP427 .suspend = ata_pci_device_suspend,428 .resume = sil680_reinit_one,429#endif430};431 432module_pci_driver(sil680_pci_driver);433 434MODULE_AUTHOR("Alan Cox");435MODULE_DESCRIPTION("low-level driver for SI680 PATA");436MODULE_LICENSE("GPL");437MODULE_DEVICE_TABLE(pci, sil680);438MODULE_VERSION(DRV_VERSION);439