709 lines · c
1// SPDX-License-Identifier: GPL-2.0-only2/*3 * pata_via.c - VIA PATA for new ATA layer4 * (C) 2005-2006 Red Hat Inc5 *6 * Documentation7 * Most chipset documentation available under NDA only8 *9 * VIA version guide10 * VIA VT82C561 - early design, uses ata_generic currently11 * VIA VT82C576 - MWDMA, 33Mhz12 * VIA VT82C586 - MWDMA, 33Mhz13 * VIA VT82C586a - Added UDMA to 33Mhz14 * VIA VT82C586b - UDMA3315 * VIA VT82C596a - Nonfunctional UDMA6616 * VIA VT82C596b - Working UDMA6617 * VIA VT82C686 - Nonfunctional UDMA6618 * VIA VT82C686a - Working UDMA6619 * VIA VT82C686b - Updated to UDMA10020 * VIA VT8231 - UDMA10021 * VIA VT8233 - UDMA10022 * VIA VT8233a - UDMA13323 * VIA VT8233c - UDMA10024 * VIA VT8235 - UDMA13325 * VIA VT8237 - UDMA13326 * VIA VT8237A - UDMA13327 * VIA VT8237S - UDMA13328 * VIA VT8251 - UDMA13329 *30 * Most registers remain compatible across chips. Others start reserved31 * and acquire sensible semantics if set to 1 (eg cable detect). A few32 * exceptions exist, notably around the FIFO settings.33 *34 * One additional quirk of the VIA design is that like ALi they use few35 * PCI IDs for a lot of chips.36 *37 * Based heavily on:38 *39 * Version 3.3840 *41 * VIA IDE driver for Linux. Supported southbridges:42 *43 * vt82c576, vt82c586, vt82c586a, vt82c586b, vt82c596a, vt82c596b,44 * vt82c686, vt82c686a, vt82c686b, vt8231, vt8233, vt8233c, vt8233a,45 * vt8235, vt823746 *47 * Copyright (c) 2000-2002 Vojtech Pavlik48 *49 * Based on the work of:50 * Michel Aubry51 * Jeff Garzik52 * Andre Hedrick53 54 */55 56#include <linux/kernel.h>57#include <linux/module.h>58#include <linux/pci.h>59#include <linux/blkdev.h>60#include <linux/delay.h>61#include <linux/gfp.h>62#include <scsi/scsi_host.h>63#include <linux/libata.h>64#include <linux/dmi.h>65 66#define DRV_NAME "pata_via"67#define DRV_VERSION "0.3.4"68 69enum {70 VIA_BAD_PREQ = 0x01, /* Crashes if PREQ# till DDACK# set */71 VIA_BAD_CLK66 = 0x02, /* 66 MHz clock doesn't work correctly */72 VIA_SET_FIFO = 0x04, /* Needs to have FIFO split set */73 VIA_NO_UNMASK = 0x08, /* Doesn't work with IRQ unmasking on */74 VIA_BAD_ID = 0x10, /* Has wrong vendor ID (0x1107) */75 VIA_BAD_AST = 0x20, /* Don't touch Address Setup Timing */76 VIA_NO_ENABLES = 0x40, /* Has no enablebits */77 VIA_SATA_PATA = 0x80, /* SATA/PATA combined configuration */78};79 80enum {81 VIA_IDFLAG_SINGLE = (1 << 0), /* single channel controller) */82};83 84/*85 * VIA SouthBridge chips.86 */87 88static const struct via_isa_bridge {89 const char *name;90 u16 id;91 u8 rev_min;92 u8 rev_max;93 u8 udma_mask;94 u8 flags;95} via_isa_bridges[] = {96 { "vx855", PCI_DEVICE_ID_VIA_VX855, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST | VIA_SATA_PATA },97 { "vx800", PCI_DEVICE_ID_VIA_VX800, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST | VIA_SATA_PATA },98 { "vt8261", PCI_DEVICE_ID_VIA_8261, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },99 { "vt8237s", PCI_DEVICE_ID_VIA_8237S, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },100 { "vt8251", PCI_DEVICE_ID_VIA_8251, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },101 { "cx700", PCI_DEVICE_ID_VIA_CX700, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST | VIA_SATA_PATA },102 { "vt6410", PCI_DEVICE_ID_VIA_6410, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST | VIA_NO_ENABLES },103 { "vt6415", PCI_DEVICE_ID_VIA_6415, 0x00, 0xff, ATA_UDMA6, VIA_BAD_AST | VIA_NO_ENABLES },104 { "vt8237a", PCI_DEVICE_ID_VIA_8237A, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },105 { "vt8237", PCI_DEVICE_ID_VIA_8237, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },106 { "vt8235", PCI_DEVICE_ID_VIA_8235, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },107 { "vt8233a", PCI_DEVICE_ID_VIA_8233A, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },108 { "vt8233c", PCI_DEVICE_ID_VIA_8233C_0, 0x00, 0x2f, ATA_UDMA5, },109 { "vt8233", PCI_DEVICE_ID_VIA_8233_0, 0x00, 0x2f, ATA_UDMA5, },110 { "vt8231", PCI_DEVICE_ID_VIA_8231, 0x00, 0x2f, ATA_UDMA5, },111 { "vt82c686b", PCI_DEVICE_ID_VIA_82C686, 0x40, 0x4f, ATA_UDMA5, },112 { "vt82c686a", PCI_DEVICE_ID_VIA_82C686, 0x10, 0x2f, ATA_UDMA4, },113 { "vt82c686", PCI_DEVICE_ID_VIA_82C686, 0x00, 0x0f, ATA_UDMA2, VIA_BAD_CLK66 },114 { "vt82c596b", PCI_DEVICE_ID_VIA_82C596, 0x10, 0x2f, ATA_UDMA4, },115 { "vt82c596a", PCI_DEVICE_ID_VIA_82C596, 0x00, 0x0f, ATA_UDMA2, VIA_BAD_CLK66 },116 { "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x47, 0x4f, ATA_UDMA2, VIA_SET_FIFO },117 { "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x40, 0x46, ATA_UDMA2, VIA_SET_FIFO | VIA_BAD_PREQ },118 { "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x30, 0x3f, ATA_UDMA2, VIA_SET_FIFO },119 { "vt82c586a", PCI_DEVICE_ID_VIA_82C586_0, 0x20, 0x2f, ATA_UDMA2, VIA_SET_FIFO },120 { "vt82c586", PCI_DEVICE_ID_VIA_82C586_0, 0x00, 0x0f, 0x00, VIA_SET_FIFO },121 { "vt82c576", PCI_DEVICE_ID_VIA_82C576, 0x00, 0x2f, 0x00, VIA_SET_FIFO | VIA_NO_UNMASK },122 { "vt82c576", PCI_DEVICE_ID_VIA_82C576, 0x00, 0x2f, 0x00, VIA_SET_FIFO | VIA_NO_UNMASK | VIA_BAD_ID },123 { "vtxxxx", PCI_DEVICE_ID_VIA_ANON, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },124 { NULL }125};126 127static const struct dmi_system_id no_atapi_dma_dmi_table[] = {128 {129 .ident = "AVERATEC 3200",130 .matches = {131 DMI_MATCH(DMI_BOARD_VENDOR, "AVERATEC"),132 DMI_MATCH(DMI_BOARD_NAME, "3200"),133 },134 },135 { }136};137 138struct via_port {139 u8 cached_device;140};141 142/*143 * Cable special cases144 */145 146static const struct dmi_system_id cable_dmi_table[] = {147 {148 .ident = "Acer Ferrari 3400",149 .matches = {150 DMI_MATCH(DMI_BOARD_VENDOR, "Acer,Inc."),151 DMI_MATCH(DMI_BOARD_NAME, "Ferrari 3400"),152 },153 },154 { }155};156 157static int via_cable_override(struct pci_dev *pdev)158{159 /* Systems by DMI */160 if (dmi_check_system(cable_dmi_table))161 return 1;162 /* Arima W730-K8/Targa Visionary 811/... */163 if (pdev->subsystem_vendor == 0x161F && pdev->subsystem_device == 0x2032)164 return 1;165 return 0;166}167 168 169/**170 * via_cable_detect - cable detection171 * @ap: ATA port172 *173 * Perform cable detection. Actually for the VIA case the BIOS174 * already did this for us. We read the values provided by the175 * BIOS. If you are using an 8235 in a non-PC configuration you176 * may need to update this code.177 *178 * Hotplug also impacts on this.179 */180 181static int via_cable_detect(struct ata_port *ap) {182 const struct via_isa_bridge *config = ap->host->private_data;183 struct pci_dev *pdev = to_pci_dev(ap->host->dev);184 u32 ata66;185 186 if (via_cable_override(pdev))187 return ATA_CBL_PATA40_SHORT;188 189 if ((config->flags & VIA_SATA_PATA) && ap->port_no == 0)190 return ATA_CBL_SATA;191 192 /* Early chips are 40 wire */193 if (config->udma_mask < ATA_UDMA4)194 return ATA_CBL_PATA40;195 /* UDMA 66 chips have only drive side logic */196 else if (config->udma_mask < ATA_UDMA5)197 return ATA_CBL_PATA_UNK;198 /* UDMA 100 or later */199 pci_read_config_dword(pdev, 0x50, &ata66);200 /* Check both the drive cable reporting bits, we might not have201 two drives */202 if (ata66 & (0x10100000 >> (16 * ap->port_no)))203 return ATA_CBL_PATA80;204 /* Check with ACPI so we can spot BIOS reported SATA bridges */205 if (ata_acpi_init_gtm(ap) &&206 ata_acpi_cbl_80wire(ap, ata_acpi_init_gtm(ap)))207 return ATA_CBL_PATA80;208 return ATA_CBL_PATA40;209}210 211static int via_pre_reset(struct ata_link *link, unsigned long deadline)212{213 struct ata_port *ap = link->ap;214 const struct via_isa_bridge *config = ap->host->private_data;215 216 if (!(config->flags & VIA_NO_ENABLES)) {217 static const struct pci_bits via_enable_bits[] = {218 { 0x40, 1, 0x02, 0x02 },219 { 0x40, 1, 0x01, 0x01 }220 };221 struct pci_dev *pdev = to_pci_dev(ap->host->dev);222 if (!pci_test_config_bits(pdev, &via_enable_bits[ap->port_no]))223 return -ENOENT;224 }225 226 return ata_sff_prereset(link, deadline);227}228 229 230/**231 * via_do_set_mode - set transfer mode data232 * @ap: ATA interface233 * @adev: ATA device234 * @mode: ATA mode being programmed235 * @set_ast: Set to program address setup236 * @udma_type: UDMA mode/format of registers237 *238 * Program the VIA registers for DMA and PIO modes. Uses the ata timing239 * support in order to compute modes.240 *241 * FIXME: Hotplug will require we serialize multiple mode changes242 * on the two channels.243 */244 245static void via_do_set_mode(struct ata_port *ap, struct ata_device *adev,246 int mode, int set_ast, int udma_type)247{248 struct pci_dev *pdev = to_pci_dev(ap->host->dev);249 struct ata_device *peer = ata_dev_pair(adev);250 struct ata_timing t, p;251 const int via_clock = 33333; /* Bus clock in kHz */252 const int T = 1000000000 / via_clock;253 int UT = T;254 int ut;255 int offset = 3 - (2*ap->port_no) - adev->devno;256 257 switch (udma_type) {258 case ATA_UDMA4:259 UT = T / 2; break;260 case ATA_UDMA5:261 UT = T / 3; break;262 case ATA_UDMA6:263 UT = T / 4; break;264 }265 266 /* Calculate the timing values we require */267 ata_timing_compute(adev, mode, &t, T, UT);268 269 /* We share 8bit timing so we must merge the constraints */270 if (peer) {271 if (peer->pio_mode) {272 ata_timing_compute(peer, peer->pio_mode, &p, T, UT);273 ata_timing_merge(&p, &t, &t, ATA_TIMING_8BIT);274 }275 }276 277 /* Address setup is programmable but breaks on UDMA133 setups */278 if (set_ast) {279 u8 setup; /* 2 bits per drive */280 int shift = 2 * offset;281 282 pci_read_config_byte(pdev, 0x4C, &setup);283 setup &= ~(3 << shift);284 setup |= (clamp_val(t.setup, 1, 4) - 1) << shift;285 pci_write_config_byte(pdev, 0x4C, setup);286 }287 288 /* Load the PIO mode bits */289 pci_write_config_byte(pdev, 0x4F - ap->port_no,290 ((clamp_val(t.act8b, 1, 16) - 1) << 4) | (clamp_val(t.rec8b, 1, 16) - 1));291 pci_write_config_byte(pdev, 0x48 + offset,292 ((clamp_val(t.active, 1, 16) - 1) << 4) | (clamp_val(t.recover, 1, 16) - 1));293 294 /* Load the UDMA bits according to type */295 switch (udma_type) {296 case ATA_UDMA2:297 default:298 ut = t.udma ? (0xe0 | (clamp_val(t.udma, 2, 5) - 2)) : 0x03;299 break;300 case ATA_UDMA4:301 ut = t.udma ? (0xe8 | (clamp_val(t.udma, 2, 9) - 2)) : 0x0f;302 break;303 case ATA_UDMA5:304 ut = t.udma ? (0xe0 | (clamp_val(t.udma, 2, 9) - 2)) : 0x07;305 break;306 case ATA_UDMA6:307 ut = t.udma ? (0xe0 | (clamp_val(t.udma, 2, 9) - 2)) : 0x07;308 break;309 }310 311 /* Set UDMA unless device is not UDMA capable */312 if (udma_type) {313 u8 udma_etc;314 315 pci_read_config_byte(pdev, 0x50 + offset, &udma_etc);316 317 /* clear transfer mode bit */318 udma_etc &= ~0x20;319 320 if (t.udma) {321 /* preserve 80-wire cable detection bit */322 udma_etc &= 0x10;323 udma_etc |= ut;324 }325 326 pci_write_config_byte(pdev, 0x50 + offset, udma_etc);327 }328}329 330static void via_set_piomode(struct ata_port *ap, struct ata_device *adev)331{332 const struct via_isa_bridge *config = ap->host->private_data;333 int set_ast = (config->flags & VIA_BAD_AST) ? 0 : 1;334 335 via_do_set_mode(ap, adev, adev->pio_mode, set_ast, config->udma_mask);336}337 338static void via_set_dmamode(struct ata_port *ap, struct ata_device *adev)339{340 const struct via_isa_bridge *config = ap->host->private_data;341 int set_ast = (config->flags & VIA_BAD_AST) ? 0 : 1;342 343 via_do_set_mode(ap, adev, adev->dma_mode, set_ast, config->udma_mask);344}345 346/**347 * via_mode_filter - filter buggy device/mode pairs348 * @dev: ATA device349 * @mask: Mode bitmask350 *351 * We need to apply some minimal filtering for old controllers and at least352 * one breed of Transcend SSD. Return the updated mask.353 */354 355static unsigned int via_mode_filter(struct ata_device *dev, unsigned int mask)356{357 struct ata_host *host = dev->link->ap->host;358 const struct via_isa_bridge *config = host->private_data;359 unsigned char model_num[ATA_ID_PROD_LEN + 1];360 361 if (config->id == PCI_DEVICE_ID_VIA_82C586_0) {362 ata_id_c_string(dev->id, model_num, ATA_ID_PROD, sizeof(model_num));363 if (strcmp(model_num, "TS64GSSD25-M") == 0) {364 ata_dev_warn(dev,365 "disabling UDMA mode due to reported lockups with this device\n");366 mask &= ~ ATA_MASK_UDMA;367 }368 }369 370 if (dev->class == ATA_DEV_ATAPI &&371 dmi_check_system(no_atapi_dma_dmi_table)) {372 ata_dev_warn(dev, "controller locks up on ATAPI DMA, forcing PIO\n");373 mask &= ATA_MASK_PIO;374 }375 376 return mask;377}378 379/**380 * via_tf_load - send taskfile registers to host controller381 * @ap: Port to which output is sent382 * @tf: ATA taskfile register set383 *384 * Outputs ATA taskfile to standard ATA host controller.385 *386 * Note: This is to fix the internal bug of via chipsets, which387 * will reset the device register after changing the IEN bit on388 * ctl register389 */390static void via_tf_load(struct ata_port *ap, const struct ata_taskfile *tf)391{392 struct ata_ioports *ioaddr = &ap->ioaddr;393 struct via_port *vp = ap->private_data;394 unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;395 int newctl = 0;396 397 if (tf->ctl != ap->last_ctl) {398 iowrite8(tf->ctl, ioaddr->ctl_addr);399 ap->last_ctl = tf->ctl;400 ata_wait_idle(ap);401 newctl = 1;402 }403 404 if (tf->flags & ATA_TFLAG_DEVICE) {405 iowrite8(tf->device, ioaddr->device_addr);406 vp->cached_device = tf->device;407 } else if (newctl)408 iowrite8(vp->cached_device, ioaddr->device_addr);409 410 if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {411 WARN_ON_ONCE(!ioaddr->ctl_addr);412 iowrite8(tf->hob_feature, ioaddr->feature_addr);413 iowrite8(tf->hob_nsect, ioaddr->nsect_addr);414 iowrite8(tf->hob_lbal, ioaddr->lbal_addr);415 iowrite8(tf->hob_lbam, ioaddr->lbam_addr);416 iowrite8(tf->hob_lbah, ioaddr->lbah_addr);417 }418 419 if (is_addr) {420 iowrite8(tf->feature, ioaddr->feature_addr);421 iowrite8(tf->nsect, ioaddr->nsect_addr);422 iowrite8(tf->lbal, ioaddr->lbal_addr);423 iowrite8(tf->lbam, ioaddr->lbam_addr);424 iowrite8(tf->lbah, ioaddr->lbah_addr);425 }426 427 ata_wait_idle(ap);428}429 430static int via_port_start(struct ata_port *ap)431{432 struct via_port *vp;433 struct pci_dev *pdev = to_pci_dev(ap->host->dev);434 435 int ret = ata_bmdma_port_start(ap);436 if (ret < 0)437 return ret;438 439 vp = devm_kzalloc(&pdev->dev, sizeof(struct via_port), GFP_KERNEL);440 if (vp == NULL)441 return -ENOMEM;442 ap->private_data = vp;443 return 0;444}445 446static const struct scsi_host_template via_sht = {447 ATA_BMDMA_SHT(DRV_NAME),448};449 450static struct ata_port_operations via_port_ops = {451 .inherits = &ata_bmdma_port_ops,452 .cable_detect = via_cable_detect,453 .set_piomode = via_set_piomode,454 .set_dmamode = via_set_dmamode,455 .prereset = via_pre_reset,456 .sff_tf_load = via_tf_load,457 .port_start = via_port_start,458 .mode_filter = via_mode_filter,459};460 461static struct ata_port_operations via_port_ops_noirq = {462 .inherits = &via_port_ops,463 .sff_data_xfer = ata_sff_data_xfer32,464};465 466/**467 * via_config_fifo - set up the FIFO468 * @pdev: PCI device469 * @flags: configuration flags470 *471 * Set the FIFO properties for this device if necessary. Used both on472 * set up and on and the resume path473 */474 475static void via_config_fifo(struct pci_dev *pdev, unsigned int flags)476{477 u8 enable;478 479 /* 0x40 low bits indicate enabled channels */480 pci_read_config_byte(pdev, 0x40 , &enable);481 enable &= 3;482 483 if (flags & VIA_SET_FIFO) {484 static const u8 fifo_setting[4] = {0x00, 0x60, 0x00, 0x20};485 u8 fifo;486 487 pci_read_config_byte(pdev, 0x43, &fifo);488 489 /* Clear PREQ# until DDACK# for errata */490 if (flags & VIA_BAD_PREQ)491 fifo &= 0x7F;492 else493 fifo &= 0x9f;494 /* Turn on FIFO for enabled channels */495 fifo |= fifo_setting[enable];496 pci_write_config_byte(pdev, 0x43, fifo);497 }498}499 500static void via_fixup(struct pci_dev *pdev, const struct via_isa_bridge *config)501{502 u32 timing;503 504 /* Initialise the FIFO for the enabled channels. */505 via_config_fifo(pdev, config->flags);506 507 if (config->udma_mask == ATA_UDMA4) {508 /* The 66 MHz devices require we enable the clock */509 pci_read_config_dword(pdev, 0x50, &timing);510 timing |= 0x80008;511 pci_write_config_dword(pdev, 0x50, timing);512 }513 if (config->flags & VIA_BAD_CLK66) {514 /* Disable the 66MHz clock on problem devices */515 pci_read_config_dword(pdev, 0x50, &timing);516 timing &= ~0x80008;517 pci_write_config_dword(pdev, 0x50, timing);518 }519}520 521/**522 * via_init_one - discovery callback523 * @pdev: PCI device524 * @id: PCI table info525 *526 * A VIA IDE interface has been discovered. Figure out what revision527 * and perform configuration work before handing it to the ATA layer528 */529 530static int via_init_one(struct pci_dev *pdev, const struct pci_device_id *id)531{532 /* Early VIA without UDMA support */533 static const struct ata_port_info via_mwdma_info = {534 .flags = ATA_FLAG_SLAVE_POSS,535 .pio_mask = ATA_PIO4,536 .mwdma_mask = ATA_MWDMA2,537 .port_ops = &via_port_ops538 };539 /* Ditto with IRQ masking required */540 static const struct ata_port_info via_mwdma_info_borked = {541 .flags = ATA_FLAG_SLAVE_POSS,542 .pio_mask = ATA_PIO4,543 .mwdma_mask = ATA_MWDMA2,544 .port_ops = &via_port_ops_noirq,545 };546 /* VIA UDMA 33 devices (and borked 66) */547 static const struct ata_port_info via_udma33_info = {548 .flags = ATA_FLAG_SLAVE_POSS,549 .pio_mask = ATA_PIO4,550 .mwdma_mask = ATA_MWDMA2,551 .udma_mask = ATA_UDMA2,552 .port_ops = &via_port_ops553 };554 /* VIA UDMA 66 devices */555 static const struct ata_port_info via_udma66_info = {556 .flags = ATA_FLAG_SLAVE_POSS,557 .pio_mask = ATA_PIO4,558 .mwdma_mask = ATA_MWDMA2,559 .udma_mask = ATA_UDMA4,560 .port_ops = &via_port_ops561 };562 /* VIA UDMA 100 devices */563 static const struct ata_port_info via_udma100_info = {564 .flags = ATA_FLAG_SLAVE_POSS,565 .pio_mask = ATA_PIO4,566 .mwdma_mask = ATA_MWDMA2,567 .udma_mask = ATA_UDMA5,568 .port_ops = &via_port_ops569 };570 /* UDMA133 with bad AST (All current 133) */571 static const struct ata_port_info via_udma133_info = {572 .flags = ATA_FLAG_SLAVE_POSS,573 .pio_mask = ATA_PIO4,574 .mwdma_mask = ATA_MWDMA2,575 .udma_mask = ATA_UDMA6, /* FIXME: should check north bridge */576 .port_ops = &via_port_ops577 };578 const struct ata_port_info *ppi[] = { NULL, NULL };579 struct pci_dev *isa;580 const struct via_isa_bridge *config;581 u8 enable;582 unsigned long flags = id->driver_data;583 int rc;584 585 ata_print_version_once(&pdev->dev, DRV_VERSION);586 587 rc = pcim_enable_device(pdev);588 if (rc)589 return rc;590 591 if (flags & VIA_IDFLAG_SINGLE)592 ppi[1] = &ata_dummy_port_info;593 594 /* To find out how the IDE will behave and what features we595 actually have to look at the bridge not the IDE controller */596 for (config = via_isa_bridges; config->id != PCI_DEVICE_ID_VIA_ANON;597 config++)598 if ((isa = pci_get_device(PCI_VENDOR_ID_VIA +599 !!(config->flags & VIA_BAD_ID),600 config->id, NULL))) {601 u8 rev = isa->revision;602 pci_dev_put(isa);603 604 if ((id->device == 0x0415 || id->device == 0x3164) &&605 (config->id != id->device))606 continue;607 608 if (rev >= config->rev_min && rev <= config->rev_max)609 break;610 }611 612 if (!(config->flags & VIA_NO_ENABLES)) {613 /* 0x40 low bits indicate enabled channels */614 pci_read_config_byte(pdev, 0x40 , &enable);615 enable &= 3;616 if (enable == 0)617 return -ENODEV;618 }619 620 /* Clock set up */621 switch (config->udma_mask) {622 case 0x00:623 if (config->flags & VIA_NO_UNMASK)624 ppi[0] = &via_mwdma_info_borked;625 else626 ppi[0] = &via_mwdma_info;627 break;628 case ATA_UDMA2:629 ppi[0] = &via_udma33_info;630 break;631 case ATA_UDMA4:632 ppi[0] = &via_udma66_info;633 break;634 case ATA_UDMA5:635 ppi[0] = &via_udma100_info;636 break;637 case ATA_UDMA6:638 ppi[0] = &via_udma133_info;639 break;640 default:641 WARN_ON(1);642 return -ENODEV;643 }644 645 via_fixup(pdev, config);646 647 /* We have established the device type, now fire it up */648 return ata_pci_bmdma_init_one(pdev, ppi, &via_sht, (void *)config, 0);649}650 651#ifdef CONFIG_PM_SLEEP652/**653 * via_reinit_one - reinit after resume654 * @pdev: PCI device655 *656 * Called when the VIA PATA device is resumed. We must then657 * reconfigure the fifo and other setup we may have altered. In658 * addition the kernel needs to have the resume methods on PCI659 * quirk supported.660 */661 662static int via_reinit_one(struct pci_dev *pdev)663{664 struct ata_host *host = pci_get_drvdata(pdev);665 int rc;666 667 rc = ata_pci_device_do_resume(pdev);668 if (rc)669 return rc;670 671 via_fixup(pdev, host->private_data);672 673 ata_host_resume(host);674 return 0;675}676#endif677 678static const struct pci_device_id via[] = {679 { PCI_VDEVICE(VIA, 0x0415), },680 { PCI_VDEVICE(VIA, 0x0571), },681 { PCI_VDEVICE(VIA, 0x0581), },682 { PCI_VDEVICE(VIA, 0x1571), },683 { PCI_VDEVICE(VIA, 0x3164), },684 { PCI_VDEVICE(VIA, 0x5324), },685 { PCI_VDEVICE(VIA, 0xC409), VIA_IDFLAG_SINGLE },686 { PCI_VDEVICE(VIA, 0x9001), VIA_IDFLAG_SINGLE },687 688 { },689};690 691static struct pci_driver via_pci_driver = {692 .name = DRV_NAME,693 .id_table = via,694 .probe = via_init_one,695 .remove = ata_pci_remove_one,696#ifdef CONFIG_PM_SLEEP697 .suspend = ata_pci_device_suspend,698 .resume = via_reinit_one,699#endif700};701 702module_pci_driver(via_pci_driver);703 704MODULE_AUTHOR("Alan Cox");705MODULE_DESCRIPTION("low-level driver for VIA PATA");706MODULE_LICENSE("GPL");707MODULE_DEVICE_TABLE(pci, via);708MODULE_VERSION(DRV_VERSION);709