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1// SPDX-License-Identifier: GPL-2.0-or-later2/*3 * sata_svw.c - ServerWorks / Apple K2 SATA4 *5 * Maintained by: Benjamin Herrenschmidt <benh@kernel.crashing.org> and6 * Jeff Garzik <jgarzik@pobox.com>7 * Please ALWAYS copy linux-ide@vger.kernel.org8 * on emails.9 *10 * Copyright 2003 Benjamin Herrenschmidt <benh@kernel.crashing.org>11 *12 * Bits from Jeff Garzik, Copyright RedHat, Inc.13 *14 * This driver probably works with non-Apple versions of the15 * Broadcom chipset...16 *17 * libata documentation is available via 'make {ps|pdf}docs',18 * as Documentation/driver-api/libata.rst19 *20 * Hardware documentation available under NDA.21 */22 23#include <linux/kernel.h>24#include <linux/module.h>25#include <linux/pci.h>26#include <linux/blkdev.h>27#include <linux/delay.h>28#include <linux/interrupt.h>29#include <linux/device.h>30#include <scsi/scsi_host.h>31#include <scsi/scsi_cmnd.h>32#include <scsi/scsi.h>33#include <linux/libata.h>34#include <linux/of.h>35#include <linux/of_address.h>36 37#define DRV_NAME "sata_svw"38#define DRV_VERSION "2.3"39 40enum {41 /* ap->flags bits */42 K2_FLAG_SATA_8_PORTS = (1 << 24),43 K2_FLAG_NO_ATAPI_DMA = (1 << 25),44 K2_FLAG_BAR_POS_3 = (1 << 26),45 46 /* Taskfile registers offsets */47 K2_SATA_TF_CMD_OFFSET = 0x00,48 K2_SATA_TF_DATA_OFFSET = 0x00,49 K2_SATA_TF_ERROR_OFFSET = 0x04,50 K2_SATA_TF_NSECT_OFFSET = 0x08,51 K2_SATA_TF_LBAL_OFFSET = 0x0c,52 K2_SATA_TF_LBAM_OFFSET = 0x10,53 K2_SATA_TF_LBAH_OFFSET = 0x14,54 K2_SATA_TF_DEVICE_OFFSET = 0x18,55 K2_SATA_TF_CMDSTAT_OFFSET = 0x1c,56 K2_SATA_TF_CTL_OFFSET = 0x20,57 58 /* DMA base */59 K2_SATA_DMA_CMD_OFFSET = 0x30,60 61 /* SCRs base */62 K2_SATA_SCR_STATUS_OFFSET = 0x40,63 K2_SATA_SCR_ERROR_OFFSET = 0x44,64 K2_SATA_SCR_CONTROL_OFFSET = 0x48,65 66 /* Others */67 K2_SATA_SICR1_OFFSET = 0x80,68 K2_SATA_SICR2_OFFSET = 0x84,69 K2_SATA_SIM_OFFSET = 0x88,70 71 /* Port stride */72 K2_SATA_PORT_OFFSET = 0x100,73 74 chip_svw4 = 0,75 chip_svw8 = 1,76 chip_svw42 = 2, /* bar 3 */77 chip_svw43 = 3, /* bar 5 */78};79 80static u8 k2_stat_check_status(struct ata_port *ap);81 82 83static int k2_sata_check_atapi_dma(struct ata_queued_cmd *qc)84{85 u8 cmnd = qc->scsicmd->cmnd[0];86 87 if (qc->ap->flags & K2_FLAG_NO_ATAPI_DMA)88 return -1; /* ATAPI DMA not supported */89 else {90 switch (cmnd) {91 case READ_10:92 case READ_12:93 case READ_16:94 case WRITE_10:95 case WRITE_12:96 case WRITE_16:97 return 0;98 99 default:100 return -1;101 }102 103 }104}105 106static int k2_sata_scr_read(struct ata_link *link,107 unsigned int sc_reg, u32 *val)108{109 if (sc_reg > SCR_CONTROL)110 return -EINVAL;111 *val = readl(link->ap->ioaddr.scr_addr + (sc_reg * 4));112 return 0;113}114 115 116static int k2_sata_scr_write(struct ata_link *link,117 unsigned int sc_reg, u32 val)118{119 if (sc_reg > SCR_CONTROL)120 return -EINVAL;121 writel(val, link->ap->ioaddr.scr_addr + (sc_reg * 4));122 return 0;123}124 125static int k2_sata_softreset(struct ata_link *link,126 unsigned int *class, unsigned long deadline)127{128 u8 dmactl;129 void __iomem *mmio = link->ap->ioaddr.bmdma_addr;130 131 dmactl = readb(mmio + ATA_DMA_CMD);132 133 /* Clear the start bit */134 if (dmactl & ATA_DMA_START) {135 dmactl &= ~ATA_DMA_START;136 writeb(dmactl, mmio + ATA_DMA_CMD);137 }138 139 return ata_sff_softreset(link, class, deadline);140}141 142static int k2_sata_hardreset(struct ata_link *link,143 unsigned int *class, unsigned long deadline)144{145 u8 dmactl;146 void __iomem *mmio = link->ap->ioaddr.bmdma_addr;147 148 dmactl = readb(mmio + ATA_DMA_CMD);149 150 /* Clear the start bit */151 if (dmactl & ATA_DMA_START) {152 dmactl &= ~ATA_DMA_START;153 writeb(dmactl, mmio + ATA_DMA_CMD);154 }155 156 return sata_sff_hardreset(link, class, deadline);157}158 159static void k2_sata_tf_load(struct ata_port *ap, const struct ata_taskfile *tf)160{161 struct ata_ioports *ioaddr = &ap->ioaddr;162 unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;163 164 if (tf->ctl != ap->last_ctl) {165 writeb(tf->ctl, ioaddr->ctl_addr);166 ap->last_ctl = tf->ctl;167 ata_wait_idle(ap);168 }169 if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {170 writew(tf->feature | (((u16)tf->hob_feature) << 8),171 ioaddr->feature_addr);172 writew(tf->nsect | (((u16)tf->hob_nsect) << 8),173 ioaddr->nsect_addr);174 writew(tf->lbal | (((u16)tf->hob_lbal) << 8),175 ioaddr->lbal_addr);176 writew(tf->lbam | (((u16)tf->hob_lbam) << 8),177 ioaddr->lbam_addr);178 writew(tf->lbah | (((u16)tf->hob_lbah) << 8),179 ioaddr->lbah_addr);180 } else if (is_addr) {181 writew(tf->feature, ioaddr->feature_addr);182 writew(tf->nsect, ioaddr->nsect_addr);183 writew(tf->lbal, ioaddr->lbal_addr);184 writew(tf->lbam, ioaddr->lbam_addr);185 writew(tf->lbah, ioaddr->lbah_addr);186 }187 188 if (tf->flags & ATA_TFLAG_DEVICE)189 writeb(tf->device, ioaddr->device_addr);190 191 ata_wait_idle(ap);192}193 194 195static void k2_sata_tf_read(struct ata_port *ap, struct ata_taskfile *tf)196{197 struct ata_ioports *ioaddr = &ap->ioaddr;198 u16 nsect, lbal, lbam, lbah, error;199 200 tf->status = k2_stat_check_status(ap);201 tf->device = readw(ioaddr->device_addr);202 error = readw(ioaddr->error_addr);203 nsect = readw(ioaddr->nsect_addr);204 lbal = readw(ioaddr->lbal_addr);205 lbam = readw(ioaddr->lbam_addr);206 lbah = readw(ioaddr->lbah_addr);207 208 tf->error = error;209 tf->nsect = nsect;210 tf->lbal = lbal;211 tf->lbam = lbam;212 tf->lbah = lbah;213 214 if (tf->flags & ATA_TFLAG_LBA48) {215 tf->hob_feature = error >> 8;216 tf->hob_nsect = nsect >> 8;217 tf->hob_lbal = lbal >> 8;218 tf->hob_lbam = lbam >> 8;219 tf->hob_lbah = lbah >> 8;220 }221}222 223/**224 * k2_bmdma_setup_mmio - Set up PCI IDE BMDMA transaction (MMIO)225 * @qc: Info associated with this ATA transaction.226 *227 * LOCKING:228 * spin_lock_irqsave(host lock)229 */230 231static void k2_bmdma_setup_mmio(struct ata_queued_cmd *qc)232{233 struct ata_port *ap = qc->ap;234 unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);235 u8 dmactl;236 void __iomem *mmio = ap->ioaddr.bmdma_addr;237 238 /* load PRD table addr. */239 mb(); /* make sure PRD table writes are visible to controller */240 writel(ap->bmdma_prd_dma, mmio + ATA_DMA_TABLE_OFS);241 242 /* specify data direction, triple-check start bit is clear */243 dmactl = readb(mmio + ATA_DMA_CMD);244 dmactl &= ~(ATA_DMA_WR | ATA_DMA_START);245 if (!rw)246 dmactl |= ATA_DMA_WR;247 writeb(dmactl, mmio + ATA_DMA_CMD);248 249 /* issue r/w command if this is not a ATA DMA command*/250 if (qc->tf.protocol != ATA_PROT_DMA)251 ap->ops->sff_exec_command(ap, &qc->tf);252}253 254/**255 * k2_bmdma_start_mmio - Start a PCI IDE BMDMA transaction (MMIO)256 * @qc: Info associated with this ATA transaction.257 *258 * LOCKING:259 * spin_lock_irqsave(host lock)260 */261 262static void k2_bmdma_start_mmio(struct ata_queued_cmd *qc)263{264 struct ata_port *ap = qc->ap;265 void __iomem *mmio = ap->ioaddr.bmdma_addr;266 u8 dmactl;267 268 /* start host DMA transaction */269 dmactl = readb(mmio + ATA_DMA_CMD);270 writeb(dmactl | ATA_DMA_START, mmio + ATA_DMA_CMD);271 /* This works around possible data corruption.272 273 On certain SATA controllers that can be seen when the r/w274 command is given to the controller before the host DMA is275 started.276 277 On a Read command, the controller would initiate the278 command to the drive even before it sees the DMA279 start. When there are very fast drives connected to the280 controller, or when the data request hits in the drive281 cache, there is the possibility that the drive returns a282 part or all of the requested data to the controller before283 the DMA start is issued. In this case, the controller284 would become confused as to what to do with the data. In285 the worst case when all the data is returned back to the286 controller, the controller could hang. In other cases it287 could return partial data returning in data288 corruption. This problem has been seen in PPC systems and289 can also appear on an system with very fast disks, where290 the SATA controller is sitting behind a number of bridges,291 and hence there is significant latency between the r/w292 command and the start command. */293 /* issue r/w command if the access is to ATA */294 if (qc->tf.protocol == ATA_PROT_DMA)295 ap->ops->sff_exec_command(ap, &qc->tf);296}297 298 299static u8 k2_stat_check_status(struct ata_port *ap)300{301 return readl(ap->ioaddr.status_addr);302}303 304static int k2_sata_show_info(struct seq_file *m, struct Scsi_Host *shost)305{306 struct ata_port *ap;307 struct device_node *np;308 int index;309 310 /* Find the ata_port */311 ap = ata_shost_to_port(shost);312 if (ap == NULL)313 return 0;314 315 /* Find the OF node for the PCI device proper */316 np = pci_device_to_OF_node(to_pci_dev(ap->host->dev));317 if (np == NULL)318 return 0;319 320 /* Match it to a port node */321 index = (ap == ap->host->ports[0]) ? 0 : 1;322 for (np = np->child; np != NULL; np = np->sibling) {323 u64 reg;324 325 if (of_property_read_reg(np, 0, ®, NULL))326 continue;327 if (index == reg) {328 seq_printf(m, "devspec: %pOF\n", np);329 break;330 }331 }332 return 0;333}334 335static const struct scsi_host_template k2_sata_sht = {336 ATA_BMDMA_SHT(DRV_NAME),337 .show_info = k2_sata_show_info,338};339 340 341static struct ata_port_operations k2_sata_ops = {342 .inherits = &ata_bmdma_port_ops,343 .softreset = k2_sata_softreset,344 .hardreset = k2_sata_hardreset,345 .sff_tf_load = k2_sata_tf_load,346 .sff_tf_read = k2_sata_tf_read,347 .sff_check_status = k2_stat_check_status,348 .check_atapi_dma = k2_sata_check_atapi_dma,349 .bmdma_setup = k2_bmdma_setup_mmio,350 .bmdma_start = k2_bmdma_start_mmio,351 .scr_read = k2_sata_scr_read,352 .scr_write = k2_sata_scr_write,353};354 355static const struct ata_port_info k2_port_info[] = {356 /* chip_svw4 */357 {358 .flags = ATA_FLAG_SATA | K2_FLAG_NO_ATAPI_DMA,359 .pio_mask = ATA_PIO4,360 .mwdma_mask = ATA_MWDMA2,361 .udma_mask = ATA_UDMA6,362 .port_ops = &k2_sata_ops,363 },364 /* chip_svw8 */365 {366 .flags = ATA_FLAG_SATA | K2_FLAG_NO_ATAPI_DMA |367 K2_FLAG_SATA_8_PORTS,368 .pio_mask = ATA_PIO4,369 .mwdma_mask = ATA_MWDMA2,370 .udma_mask = ATA_UDMA6,371 .port_ops = &k2_sata_ops,372 },373 /* chip_svw42 */374 {375 .flags = ATA_FLAG_SATA | K2_FLAG_BAR_POS_3,376 .pio_mask = ATA_PIO4,377 .mwdma_mask = ATA_MWDMA2,378 .udma_mask = ATA_UDMA6,379 .port_ops = &k2_sata_ops,380 },381 /* chip_svw43 */382 {383 .flags = ATA_FLAG_SATA,384 .pio_mask = ATA_PIO4,385 .mwdma_mask = ATA_MWDMA2,386 .udma_mask = ATA_UDMA6,387 .port_ops = &k2_sata_ops,388 },389};390 391static void k2_sata_setup_port(struct ata_ioports *port, void __iomem *base)392{393 port->cmd_addr = base + K2_SATA_TF_CMD_OFFSET;394 port->data_addr = base + K2_SATA_TF_DATA_OFFSET;395 port->feature_addr =396 port->error_addr = base + K2_SATA_TF_ERROR_OFFSET;397 port->nsect_addr = base + K2_SATA_TF_NSECT_OFFSET;398 port->lbal_addr = base + K2_SATA_TF_LBAL_OFFSET;399 port->lbam_addr = base + K2_SATA_TF_LBAM_OFFSET;400 port->lbah_addr = base + K2_SATA_TF_LBAH_OFFSET;401 port->device_addr = base + K2_SATA_TF_DEVICE_OFFSET;402 port->command_addr =403 port->status_addr = base + K2_SATA_TF_CMDSTAT_OFFSET;404 port->altstatus_addr =405 port->ctl_addr = base + K2_SATA_TF_CTL_OFFSET;406 port->bmdma_addr = base + K2_SATA_DMA_CMD_OFFSET;407 port->scr_addr = base + K2_SATA_SCR_STATUS_OFFSET;408}409 410 411static int k2_sata_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)412{413 const struct ata_port_info *ppi[] =414 { &k2_port_info[ent->driver_data], NULL };415 struct ata_host *host;416 void __iomem *mmio_base;417 int n_ports, i, rc, bar_pos;418 419 ata_print_version_once(&pdev->dev, DRV_VERSION);420 421 /* allocate host */422 n_ports = 4;423 if (ppi[0]->flags & K2_FLAG_SATA_8_PORTS)424 n_ports = 8;425 426 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);427 if (!host)428 return -ENOMEM;429 430 bar_pos = 5;431 if (ppi[0]->flags & K2_FLAG_BAR_POS_3)432 bar_pos = 3;433 /*434 * If this driver happens to only be useful on Apple's K2, then435 * we should check that here as it has a normal Serverworks ID436 */437 rc = pcim_enable_device(pdev);438 if (rc)439 return rc;440 441 /*442 * Check if we have resources mapped at all (second function may443 * have been disabled by firmware)444 */445 if (pci_resource_len(pdev, bar_pos) == 0) {446 /* In IDE mode we need to pin the device to ensure that447 pcim_release does not clear the busmaster bit in config448 space, clearing causes busmaster DMA to fail on449 ports 3 & 4 */450 pcim_pin_device(pdev);451 return -ENODEV;452 }453 454 /* Request and iomap PCI regions */455 rc = pcim_iomap_regions(pdev, 1 << bar_pos, DRV_NAME);456 if (rc == -EBUSY)457 pcim_pin_device(pdev);458 if (rc)459 return rc;460 host->iomap = pcim_iomap_table(pdev);461 mmio_base = host->iomap[bar_pos];462 463 /* different controllers have different number of ports - currently 4 or 8 */464 /* All ports are on the same function. Multi-function device is no465 * longer available. This should not be seen in any system. */466 for (i = 0; i < host->n_ports; i++) {467 struct ata_port *ap = host->ports[i];468 unsigned int offset = i * K2_SATA_PORT_OFFSET;469 470 k2_sata_setup_port(&ap->ioaddr, mmio_base + offset);471 472 ata_port_pbar_desc(ap, 5, -1, "mmio");473 ata_port_pbar_desc(ap, 5, offset, "port");474 }475 476 rc = dma_set_mask_and_coherent(&pdev->dev, ATA_DMA_MASK);477 if (rc)478 return rc;479 480 /* Clear a magic bit in SCR1 according to Darwin, those help481 * some funky seagate drives (though so far, those were already482 * set by the firmware on the machines I had access to)483 */484 writel(readl(mmio_base + K2_SATA_SICR1_OFFSET) & ~0x00040000,485 mmio_base + K2_SATA_SICR1_OFFSET);486 487 /* Clear SATA error & interrupts we don't use */488 writel(0xffffffff, mmio_base + K2_SATA_SCR_ERROR_OFFSET);489 writel(0x0, mmio_base + K2_SATA_SIM_OFFSET);490 491 pci_set_master(pdev);492 return ata_host_activate(host, pdev->irq, ata_bmdma_interrupt,493 IRQF_SHARED, &k2_sata_sht);494}495 496/* 0x240 is device ID for Apple K2 device497 * 0x241 is device ID for Serverworks Frodo4498 * 0x242 is device ID for Serverworks Frodo8499 * 0x24a is device ID for BCM5785 (aka HT1000) HT southbridge integrated SATA500 * controller501 * */502static const struct pci_device_id k2_sata_pci_tbl[] = {503 { PCI_VDEVICE(SERVERWORKS, 0x0240), chip_svw4 },504 { PCI_VDEVICE(SERVERWORKS, 0x0241), chip_svw8 },505 { PCI_VDEVICE(SERVERWORKS, 0x0242), chip_svw4 },506 { PCI_VDEVICE(SERVERWORKS, 0x024a), chip_svw4 },507 { PCI_VDEVICE(SERVERWORKS, 0x024b), chip_svw4 },508 { PCI_VDEVICE(SERVERWORKS, 0x0410), chip_svw42 },509 { PCI_VDEVICE(SERVERWORKS, 0x0411), chip_svw43 },510 511 { }512};513 514static struct pci_driver k2_sata_pci_driver = {515 .name = DRV_NAME,516 .id_table = k2_sata_pci_tbl,517 .probe = k2_sata_init_one,518 .remove = ata_pci_remove_one,519};520 521module_pci_driver(k2_sata_pci_driver);522 523MODULE_AUTHOR("Benjamin Herrenschmidt");524MODULE_DESCRIPTION("low-level driver for K2 SATA controller");525MODULE_LICENSE("GPL");526MODULE_DEVICE_TABLE(pci, k2_sata_pci_tbl);527MODULE_VERSION(DRV_VERSION);528