268 lines · plain
1# SPDX-License-Identifier: GPL-2.02#3# Bus Devices4#5 6menu "Bus devices"7 8config ARM_CCI9 bool10 11config ARM_CCI400_COMMON12 bool13 select ARM_CCI14 15config ARM_CCI400_PORT_CTRL16 bool17 depends on ARM && OF && CPU_V718 select ARM_CCI400_COMMON19 help20 Low level power management driver for CCI400 cache coherent21 interconnect for ARM platforms.22 23config ARM_INTEGRATOR_LM24 bool "ARM Integrator Logic Module bus"25 depends on HAS_IOMEM26 depends on ARCH_INTEGRATOR || COMPILE_TEST27 default ARCH_INTEGRATOR28 help29 Say y here to enable support for the ARM Logic Module bus30 found on the ARM Integrator AP (Application Platform)31 32config BRCMSTB_GISB_ARB33 tristate "Broadcom STB GISB bus arbiter"34 depends on ARCH_BRCMSTB || BMIPS_GENERIC35 default ARCH_BRCMSTB || BMIPS_GENERIC36 help37 Driver for the Broadcom Set Top Box System-on-a-chip internal bus38 arbiter. This driver provides timeout and target abort error handling39 and internal bus master decoding.40 41config BT1_APB42 bool "Baikal-T1 APB-bus driver"43 depends on MIPS_BAIKAL_T1 || COMPILE_TEST44 select REGMAP_MMIO45 help46 Baikal-T1 AXI-APB bridge is used to access the SoC subsystem CSRs.47 IO requests are routed to this bus by means of the DW AMBA 3 AXI48 Interconnect. In case of any APB protocol collisions, slave device49 not responding on timeout an IRQ is raised with an erroneous address50 reported to the APB terminator (APB Errors Handler Block). This51 driver provides the interrupt handler to detect the erroneous52 address, prints an error message about the address fault, updates an53 errors counter. The counter and the APB-bus operations timeout can be54 accessed via corresponding sysfs nodes.55 56config BT1_AXI57 bool "Baikal-T1 AXI-bus driver"58 depends on MIPS_BAIKAL_T1 || COMPILE_TEST59 select MFD_SYSCON60 help61 AXI3-bus is the main communication bus connecting all high-speed62 peripheral IP-cores with RAM controller and with MIPS P5600 cores on63 Baikal-T1 SoC. Traffic arbitration is done by means of DW AMBA 3 AXI64 Interconnect (so called AXI Main Interconnect) routing IO requests65 from one SoC block to another. This driver provides a way to detect66 any bus protocol errors and device not responding situations by67 means of an embedded on top of the interconnect errors handler68 block (EHB). AXI Interconnect QoS arbitration tuning is currently69 unsupported.70 71config MOXTET72 tristate "CZ.NIC Turris Mox module configuration bus"73 depends on SPI_MASTER && OF74 help75 Say yes here to add support for the module configuration bus found76 on CZ.NIC's Turris Mox. This is needed for the ability to discover77 the order in which the modules are connected and to get/set some of78 their settings. For example the GPIOs on Mox SFP module are79 configured through this bus.80 81config HISILICON_LPC82 bool "Support for ISA I/O space on HiSilicon Hip06/7"83 depends on (ARM64 && ARCH_HISI) || (COMPILE_TEST && !ALPHA && !HEXAGON && !PARISC)84 depends on HAS_IOPORT85 select INDIRECT_PIO if ARM6486 help87 Driver to enable I/O access to devices attached to the Low Pin88 Count bus on the HiSilicon Hip06/7 SoC.89 90config IMX_WEIM91 bool "Freescale EIM DRIVER"92 depends on ARCH_MXC || COMPILE_TEST93 help94 Driver for i.MX WEIM controller.95 The WEIM(Wireless External Interface Module) works like a bus.96 You can attach many different devices on it, such as NOR, onenand.97 98config INTEL_IXP4XX_EB99 bool "Intel IXP4xx expansion bus interface driver"100 depends on HAS_IOMEM101 depends on ARCH_IXP4XX || COMPILE_TEST102 default ARCH_IXP4XX103 select MFD_SYSCON104 help105 Driver for the Intel IXP4xx expansion bus interface. The driver is106 needed to set up various chip select configuration parameters before107 devices on the expansion bus can be discovered.108 109config MIPS_CDMM110 bool "MIPS Common Device Memory Map (CDMM) Driver"111 depends on CPU_MIPSR2 || CPU_MIPSR5112 help113 Driver needed for the MIPS Common Device Memory Map bus in MIPS114 cores. This bus is for per-CPU tightly coupled devices such as the115 Fast Debug Channel (FDC).116 117 For this to work, either your bootloader needs to enable the CDMM118 region at an unused physical address on the boot CPU, or else your119 platform code needs to implement mips_cdmm_phys_base() (see120 asm/cdmm.h).121 122config MVEBU_MBUS123 bool124 depends on PLAT_ORION125 help126 Driver needed for the MBus configuration on Marvell EBU SoCs127 (Kirkwood, Dove, Orion5x, MV78XX0 and Armada 370/XP).128 129config OMAP_INTERCONNECT130 tristate "OMAP INTERCONNECT DRIVER"131 depends on ARCH_OMAP2PLUS132 133 help134 Driver to enable OMAP interconnect error handling driver.135 136config OMAP_OCP2SCP137 tristate "OMAP OCP2SCP DRIVER"138 depends on ARCH_OMAP2PLUS139 help140 Driver to enable ocp2scp module which transforms ocp interface141 protocol to scp protocol. In OMAP4, USB PHY is connected via142 OCP2SCP and in OMAP5, both USB PHY and SATA PHY is connected via143 OCP2SCP.144 145config QCOM_EBI2146 bool "Qualcomm External Bus Interface 2 (EBI2)"147 depends on HAS_IOMEM148 depends on ARCH_QCOM || COMPILE_TEST149 default ARCH_QCOM150 help151 Say y here to enable support for the Qualcomm External Bus152 Interface 2, which can be used to connect things like NAND Flash,153 SRAM, ethernet adapters, FPGAs and LCD displays.154 155config QCOM_SSC_BLOCK_BUS156 bool "Qualcomm SSC Block Bus Init Driver"157 depends on ARCH_QCOM158 help159 Say y here to enable support for initializing the bus that connects160 the SSC block's internal bus to the cNoC (configurantion NoC) on161 (some) qcom SoCs.162 The SSC (Snapdragon Sensor Core) block contains a gpio controller,163 i2c/spi/uart controllers, a hexagon core, and a clock controller164 which provides clocks for the above.165 166config STM32_FIREWALL167 bool "STM32 Firewall framework"168 depends on (ARCH_STM32 || COMPILE_TEST) && OF169 select OF_DYNAMIC170 help171 Say y to enable STM32 firewall framework and its services. Firewall172 controllers will be able to register to the framework. Access for173 hardware resources linked to a firewall controller can be requested174 through this STM32 framework.175 176config SUN50I_DE2_BUS177 bool "Allwinner A64 DE2 Bus Driver"178 default ARM64179 depends on ARCH_SUNXI180 select SUNXI_SRAM181 help182 Say y here to enable support for Allwinner A64 DE2 bus driver. It's183 mostly transparent, but a SRAM region needs to be claimed in the SRAM184 controller to make the all blocks in the DE2 part accessible.185 186config SUNXI_RSB187 tristate "Allwinner sunXi Reduced Serial Bus Driver"188 default MACH_SUN8I || MACH_SUN9I || ARM64189 depends on ARCH_SUNXI190 select REGMAP191 help192 Say y here to enable support for Allwinner's Reduced Serial Bus193 (RSB) support. This controller is responsible for communicating194 with various RSB based devices, such as AXP223, AXP8XX PMICs,195 and AC100/AC200 ICs.196 197config TEGRA_ACONNECT198 tristate "Tegra ACONNECT Bus Driver"199 depends on ARCH_TEGRA200 depends on OF && PM201 help202 Driver for the Tegra ACONNECT bus which is used to interface with203 the devices inside the Audio Processing Engine (APE) for204 Tegra210 and later.205 206config TEGRA_GMI207 tristate "Tegra Generic Memory Interface bus driver"208 depends on ARCH_TEGRA209 help210 Driver for the Tegra Generic Memory Interface bus which can be used211 to attach devices such as NOR, UART, FPGA and more.212 213config TI_PWMSS214 bool215 default y if (ARCH_OMAP2PLUS) && (PWM_TIECAP || PWM_TIEHRPWM || TI_EQEP)216 help217 PWM Subsystem driver support for AM33xx SOC.218 219 PWM submodules require PWM config space access from submodule220 drivers and require common parent driver support.221 222config TI_SYSC223 bool "TI sysc interconnect target module driver"224 depends on ARCH_OMAP2PLUS || ARCH_K3225 default y226 help227 Generic driver for Texas Instruments interconnect target module228 found on many TI SoCs.229 230config TS_NBUS231 tristate "Technologic Systems NBUS Driver"232 depends on SOC_IMX28233 depends on OF_GPIO && PWM234 help235 Driver for the Technologic Systems NBUS which is used to interface236 with the peripherals in the FPGA of the TS-4600 SoM.237 238config UNIPHIER_SYSTEM_BUS239 tristate "UniPhier System Bus driver"240 depends on ARCH_UNIPHIER && OF241 default y242 help243 Support for UniPhier System Bus, a simple external bus. This is244 needed to use on-board devices connected to UniPhier SoCs.245 246config VEXPRESS_CONFIG247 tristate "Versatile Express configuration bus"248 default y if ARCH_VEXPRESS249 depends on ARM || ARM64250 depends on OF251 select REGMAP252 help253 Platform configuration infrastructure for the ARM Ltd.254 Versatile Express.255 256config DA8XX_MSTPRI257 bool "TI da8xx master peripheral priority driver"258 depends on ARCH_DAVINCI_DA8XX259 help260 Driver for Texas Instruments da8xx master peripheral priority261 configuration. Allows to adjust the priorities of all master262 peripherals.263 264source "drivers/bus/fsl-mc/Kconfig"265source "drivers/bus/mhi/Kconfig"266 267endmenu268