494 lines · c
1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * OMAP L3 Interconnect error handling driver header4 *5 * Copyright (C) 2011-2015 Texas Instruments Incorporated - http://www.ti.com/6 * Santosh Shilimkar <santosh.shilimkar@ti.com>7 * sricharan <r.sricharan@ti.com>8 */9#ifndef __OMAP_L3_NOC_H10#define __OMAP_L3_NOC_H11 12#define MAX_L3_MODULES 313#define MAX_CLKDM_TARGETS 3114 15#define CLEAR_STDERR_LOG (1 << 31)16#define CUSTOM_ERROR 0x217#define STANDARD_ERROR 0x018#define INBAND_ERROR 0x019#define L3_APPLICATION_ERROR 0x020#define L3_DEBUG_ERROR 0x121 22/* L3 TARG register offsets */23#define L3_TARG_STDERRLOG_MAIN 0x4824#define L3_TARG_STDERRLOG_HDR 0x4c25#define L3_TARG_STDERRLOG_MSTADDR 0x5026#define L3_TARG_STDERRLOG_INFO 0x5827#define L3_TARG_STDERRLOG_SLVOFSLSB 0x5c28#define L3_TARG_STDERRLOG_CINFO_INFO 0x6429#define L3_TARG_STDERRLOG_CINFO_MSTADDR 0x6830#define L3_TARG_STDERRLOG_CINFO_OPCODE 0x6c31#define L3_FLAGMUX_REGERR0 0xc32#define L3_FLAGMUX_MASK0 0x833 34#define L3_TARGET_NOT_SUPPORTED NULL35 36#define L3_BASE_IS_SUBMODULE ((void __iomem *)(1 << 0))37 38static const char * const l3_transaction_type[] = {39 /* 0 0 0 */ "Idle",40 /* 0 0 1 */ "Write",41 /* 0 1 0 */ "Read",42 /* 0 1 1 */ "ReadEx",43 /* 1 0 0 */ "Read Link",44 /* 1 0 1 */ "Write Non-Posted",45 /* 1 1 0 */ "Write Conditional",46 /* 1 1 1 */ "Write Broadcast",47};48 49/**50 * struct l3_masters_data - L3 Master information51 * @id: ID of the L3 Master52 * @name: master name53 */54struct l3_masters_data {55 u32 id;56 char *name;57};58 59/**60 * struct l3_target_data - L3 Target information61 * @offset: Offset from base for L3 Target62 * @name: Target name63 *64 * Target information is organized indexed by bit field definitions.65 */66struct l3_target_data {67 u32 offset;68 char *name;69};70 71/**72 * struct l3_flagmux_data - Flag Mux information73 * @offset: offset from base for flagmux register74 * @l3_targ: array indexed by flagmux index (bit offset) pointing to the75 * target data. unsupported ones are marked with76 * L3_TARGET_NOT_SUPPORTED77 * @num_targ_data: number of entries in target data78 * @mask_app_bits: ignore these from raw application irq status79 * @mask_dbg_bits: ignore these from raw debug irq status80 */81struct l3_flagmux_data {82 u32 offset;83 struct l3_target_data *l3_targ;84 u8 num_targ_data;85 u32 mask_app_bits;86 u32 mask_dbg_bits;87};88 89 90/**91 * struct omap_l3 - Description of data relevant for L3 bus.92 * @dev: device representing the bus (populated runtime)93 * @l3_base: base addresses of modules (populated runtime if 0)94 * if set to L3_BASE_IS_SUBMODULE, then uses previous95 * module index as the base address96 * @l3_flag_mux: array containing flag mux data per module97 * offset from corresponding module base indexed per98 * module.99 * @num_modules: number of clock domains / modules.100 * @l3_masters: array pointing to master data containing name and register101 * offset for the master.102 * @num_master: number of masters103 * @mst_addr_mask: Mask representing MSTADDR information of NTTP packet104 * @debug_irq: irq number of the debug interrupt (populated runtime)105 * @app_irq: irq number of the application interrupt (populated runtime)106 */107struct omap_l3 {108 struct device *dev;109 110 void __iomem *l3_base[MAX_L3_MODULES];111 struct l3_flagmux_data **l3_flagmux;112 int num_modules;113 114 struct l3_masters_data *l3_masters;115 int num_masters;116 u32 mst_addr_mask;117 118 int debug_irq;119 int app_irq;120};121 122static struct l3_target_data omap_l3_target_data_clk1[] = {123 {0x100, "DMM1",},124 {0x200, "DMM2",},125 {0x300, "ABE",},126 {0x400, "L4CFG",},127 {0x600, "CLK2PWRDISC",},128 {0x0, "HOSTCLK1",},129 {0x900, "L4WAKEUP",},130};131 132static struct l3_flagmux_data omap_l3_flagmux_clk1 = {133 .offset = 0x500,134 .l3_targ = omap_l3_target_data_clk1,135 .num_targ_data = ARRAY_SIZE(omap_l3_target_data_clk1),136};137 138 139static struct l3_target_data omap_l3_target_data_clk2[] = {140 {0x500, "CORTEXM3",},141 {0x300, "DSS",},142 {0x100, "GPMC",},143 {0x400, "ISS",},144 {0x700, "IVAHD",},145 {0xD00, "AES1",},146 {0x900, "L4PER0",},147 {0x200, "OCMRAM",},148 {0x100, "GPMCsERROR",},149 {0x600, "SGX",},150 {0x800, "SL2",},151 {0x1600, "C2C",},152 {0x1100, "PWRDISCCLK1",},153 {0xF00, "SHA1",},154 {0xE00, "AES2",},155 {0xC00, "L4PER3",},156 {0xA00, "L4PER1",},157 {0xB00, "L4PER2",},158 {0x0, "HOSTCLK2",},159 {0x1800, "CAL",},160 {0x1700, "LLI",},161};162 163static struct l3_flagmux_data omap_l3_flagmux_clk2 = {164 .offset = 0x1000,165 .l3_targ = omap_l3_target_data_clk2,166 .num_targ_data = ARRAY_SIZE(omap_l3_target_data_clk2),167};168 169 170static struct l3_target_data omap4_l3_target_data_clk3[] = {171 {0x0100, "DEBUGSS",},172};173 174static struct l3_flagmux_data omap4_l3_flagmux_clk3 = {175 .offset = 0x0200,176 .l3_targ = omap4_l3_target_data_clk3,177 .num_targ_data = ARRAY_SIZE(omap4_l3_target_data_clk3),178};179 180static struct l3_masters_data omap_l3_masters[] = {181 { 0x00, "MPU"},182 { 0x04, "CS_ADP"},183 { 0x05, "xxx"},184 { 0x08, "DSP"},185 { 0x0C, "IVAHD"},186 { 0x10, "ISS"},187 { 0x11, "DucatiM3"},188 { 0x12, "FaceDetect"},189 { 0x14, "SDMA_Rd"},190 { 0x15, "SDMA_Wr"},191 { 0x16, "xxx"},192 { 0x17, "xxx"},193 { 0x18, "SGX"},194 { 0x1C, "DSS"},195 { 0x20, "C2C"},196 { 0x22, "xxx"},197 { 0x23, "xxx"},198 { 0x24, "HSI"},199 { 0x28, "MMC1"},200 { 0x29, "MMC2"},201 { 0x2A, "MMC6"},202 { 0x2C, "UNIPRO1"},203 { 0x30, "USBHOSTHS"},204 { 0x31, "USBOTGHS"},205 { 0x32, "USBHOSTFS"}206};207 208static struct l3_flagmux_data *omap4_l3_flagmux[] = {209 &omap_l3_flagmux_clk1,210 &omap_l3_flagmux_clk2,211 &omap4_l3_flagmux_clk3,212};213 214static const struct omap_l3 omap4_l3_data = {215 .l3_flagmux = omap4_l3_flagmux,216 .num_modules = ARRAY_SIZE(omap4_l3_flagmux),217 .l3_masters = omap_l3_masters,218 .num_masters = ARRAY_SIZE(omap_l3_masters),219 /* The 6 MSBs of register field used to distinguish initiator */220 .mst_addr_mask = 0xFC,221};222 223/* OMAP5 data */224static struct l3_target_data omap5_l3_target_data_clk3[] = {225 {0x0100, "L3INSTR",},226 {0x0300, "DEBUGSS",},227 {0x0, "HOSTCLK3",},228};229 230static struct l3_flagmux_data omap5_l3_flagmux_clk3 = {231 .offset = 0x0200,232 .l3_targ = omap5_l3_target_data_clk3,233 .num_targ_data = ARRAY_SIZE(omap5_l3_target_data_clk3),234};235 236static struct l3_flagmux_data *omap5_l3_flagmux[] = {237 &omap_l3_flagmux_clk1,238 &omap_l3_flagmux_clk2,239 &omap5_l3_flagmux_clk3,240};241 242static const struct omap_l3 omap5_l3_data = {243 .l3_flagmux = omap5_l3_flagmux,244 .num_modules = ARRAY_SIZE(omap5_l3_flagmux),245 .l3_masters = omap_l3_masters,246 .num_masters = ARRAY_SIZE(omap_l3_masters),247 /* The 6 MSBs of register field used to distinguish initiator */248 .mst_addr_mask = 0x7E0,249};250 251/* DRA7 data */252static struct l3_target_data dra_l3_target_data_clk1[] = {253 {0x2a00, "AES1",},254 {0x0200, "DMM_P1",},255 {0x0600, "DSP2_SDMA",},256 {0x0b00, "EVE2",},257 {0x1300, "DMM_P2",},258 {0x2c00, "AES2",},259 {0x0300, "DSP1_SDMA",},260 {0x0a00, "EVE1",},261 {0x0c00, "EVE3",},262 {0x0d00, "EVE4",},263 {0x2900, "DSS",},264 {0x0100, "GPMC",},265 {0x3700, "PCIE1",},266 {0x1600, "IVA_CONFIG",},267 {0x1800, "IVA_SL2IF",},268 {0x0500, "L4_CFG",},269 {0x1d00, "L4_WKUP",},270 {0x3800, "PCIE2",},271 {0x3300, "SHA2_1",},272 {0x1200, "GPU",},273 {0x1000, "IPU1",},274 {0x1100, "IPU2",},275 {0x2000, "TPCC_EDMA",},276 {0x2e00, "TPTC1_EDMA",},277 {0x2b00, "TPTC2_EDMA",},278 {0x0700, "VCP1",},279 {0x2500, "L4_PER2_P3",},280 {0x0e00, "L4_PER3_P3",},281 {0x2200, "MMU1",},282 {0x1400, "PRUSS1",},283 {0x1500, "PRUSS2"},284 {0x0800, "VCP1",},285};286 287static struct l3_flagmux_data dra_l3_flagmux_clk1 = {288 .offset = 0x803500,289 .l3_targ = dra_l3_target_data_clk1,290 .num_targ_data = ARRAY_SIZE(dra_l3_target_data_clk1),291};292 293static struct l3_target_data dra_l3_target_data_clk2[] = {294 {0x0, "HOST CLK1",},295 {0x800000, "HOST CLK2",},296 {0xdead, L3_TARGET_NOT_SUPPORTED,},297 {0x3400, "SHA2_2",},298 {0x0900, "BB2D",},299 {0xdead, L3_TARGET_NOT_SUPPORTED,},300 {0x2100, "L4_PER1_P3",},301 {0x1c00, "L4_PER1_P1",},302 {0x1f00, "L4_PER1_P2",},303 {0x2300, "L4_PER2_P1",},304 {0x2400, "L4_PER2_P2",},305 {0x2600, "L4_PER3_P1",},306 {0x2700, "L4_PER3_P2",},307 {0x2f00, "MCASP1",},308 {0x3000, "MCASP2",},309 {0x3100, "MCASP3",},310 {0x2800, "MMU2",},311 {0x0f00, "OCMC_RAM1",},312 {0x1700, "OCMC_RAM2",},313 {0x1900, "OCMC_RAM3",},314 {0x1e00, "OCMC_ROM",},315 {0x3900, "QSPI",},316};317 318static struct l3_flagmux_data dra_l3_flagmux_clk2 = {319 .offset = 0x803600,320 .l3_targ = dra_l3_target_data_clk2,321 .num_targ_data = ARRAY_SIZE(dra_l3_target_data_clk2),322};323 324static struct l3_target_data dra_l3_target_data_clk3[] = {325 {0x0100, "L3_INSTR"},326 {0x0300, "DEBUGSS_CT_TBR"},327 {0x0, "HOST CLK3"},328};329 330static struct l3_flagmux_data dra_l3_flagmux_clk3 = {331 .offset = 0x200,332 .l3_targ = dra_l3_target_data_clk3,333 .num_targ_data = ARRAY_SIZE(dra_l3_target_data_clk3),334};335 336static struct l3_masters_data dra_l3_masters[] = {337 { 0x0, "MPU" },338 { 0x4, "CS_DAP" },339 { 0x5, "IEEE1500_2_OCP" },340 { 0x8, "DSP1_MDMA" },341 { 0x9, "DSP1_CFG" },342 { 0xA, "DSP1_DMA" },343 { 0xB, "DSP2_MDMA" },344 { 0xC, "DSP2_CFG" },345 { 0xD, "DSP2_DMA" },346 { 0xE, "IVA" },347 { 0x10, "EVE1_P1" },348 { 0x11, "EVE2_P1" },349 { 0x12, "EVE3_P1" },350 { 0x13, "EVE4_P1" },351 { 0x14, "PRUSS1 PRU1" },352 { 0x15, "PRUSS1 PRU2" },353 { 0x16, "PRUSS2 PRU1" },354 { 0x17, "PRUSS2 PRU2" },355 { 0x18, "IPU1" },356 { 0x19, "IPU2" },357 { 0x1A, "SDMA" },358 { 0x1B, "CDMA" },359 { 0x1C, "TC1_EDMA" },360 { 0x1D, "TC2_EDMA" },361 { 0x20, "DSS" },362 { 0x21, "MMU1" },363 { 0x22, "PCIE1" },364 { 0x23, "MMU2" },365 { 0x24, "VIP1" },366 { 0x25, "VIP2" },367 { 0x26, "VIP3" },368 { 0x27, "VPE" },369 { 0x28, "GPU_P1" },370 { 0x29, "BB2D" },371 { 0x29, "GPU_P2" },372 { 0x2B, "GMAC_SW" },373 { 0x2C, "USB3" },374 { 0x2D, "USB2_SS" },375 { 0x2E, "USB2_ULPI_SS1" },376 { 0x2F, "USB2_ULPI_SS2" },377 { 0x30, "CSI2_1" },378 { 0x31, "CSI2_2" },379 { 0x33, "SATA" },380 { 0x34, "EVE1_P2" },381 { 0x35, "EVE2_P2" },382 { 0x36, "EVE3_P2" },383 { 0x37, "EVE4_P2" }384};385 386static struct l3_flagmux_data *dra_l3_flagmux[] = {387 &dra_l3_flagmux_clk1,388 &dra_l3_flagmux_clk2,389 &dra_l3_flagmux_clk3,390};391 392static const struct omap_l3 dra_l3_data = {393 .l3_base = { [1] = L3_BASE_IS_SUBMODULE },394 .l3_flagmux = dra_l3_flagmux,395 .num_modules = ARRAY_SIZE(dra_l3_flagmux),396 .l3_masters = dra_l3_masters,397 .num_masters = ARRAY_SIZE(dra_l3_masters),398 /* The 6 MSBs of register field used to distinguish initiator */399 .mst_addr_mask = 0xFC,400};401 402/* AM4372 data */403static struct l3_target_data am4372_l3_target_data_200f[] = {404 {0xf00, "EMIF",},405 {0x1200, "DES",},406 {0x400, "OCMCRAM",},407 {0x700, "TPTC0",},408 {0x800, "TPTC1",},409 {0x900, "TPTC2"},410 {0xb00, "TPCC",},411 {0xd00, "DEBUGSS",},412 {0xdead, L3_TARGET_NOT_SUPPORTED,},413 {0x200, "SHA",},414 {0xc00, "SGX530",},415 {0x500, "AES0",},416 {0xa00, "L4_FAST",},417 {0x300, "MPUSS_L2_RAM",},418 {0x100, "ICSS",},419};420 421static struct l3_flagmux_data am4372_l3_flagmux_200f = {422 .offset = 0x1000,423 .l3_targ = am4372_l3_target_data_200f,424 .num_targ_data = ARRAY_SIZE(am4372_l3_target_data_200f),425};426 427static struct l3_target_data am4372_l3_target_data_100s[] = {428 {0x100, "L4_PER_0",},429 {0x200, "L4_PER_1",},430 {0x300, "L4_PER_2",},431 {0x400, "L4_PER_3",},432 {0x800, "McASP0",},433 {0x900, "McASP1",},434 {0xC00, "MMCHS2",},435 {0x700, "GPMC",},436 {0xD00, "L4_FW",},437 {0xdead, L3_TARGET_NOT_SUPPORTED,},438 {0x500, "ADCTSC",},439 {0xE00, "L4_WKUP",},440 {0xA00, "MAG_CARD",},441};442 443static struct l3_flagmux_data am4372_l3_flagmux_100s = {444 .offset = 0x600,445 .l3_targ = am4372_l3_target_data_100s,446 .num_targ_data = ARRAY_SIZE(am4372_l3_target_data_100s),447};448 449static struct l3_masters_data am4372_l3_masters[] = {450 { 0x0, "M1 (128-bit)"},451 { 0x1, "M2 (64-bit)"},452 { 0x4, "DAP"},453 { 0x5, "P1500"},454 { 0xC, "ICSS0"},455 { 0xD, "ICSS1"},456 { 0x14, "Wakeup Processor"},457 { 0x18, "TPTC0 Read"},458 { 0x19, "TPTC0 Write"},459 { 0x1A, "TPTC1 Read"},460 { 0x1B, "TPTC1 Write"},461 { 0x1C, "TPTC2 Read"},462 { 0x1D, "TPTC2 Write"},463 { 0x20, "SGX530"},464 { 0x21, "OCP WP Traffic Probe"},465 { 0x22, "OCP WP DMA Profiling"},466 { 0x23, "OCP WP Event Trace"},467 { 0x25, "DSS"},468 { 0x28, "Crypto DMA RD"},469 { 0x29, "Crypto DMA WR"},470 { 0x2C, "VPFE0"},471 { 0x2D, "VPFE1"},472 { 0x30, "GEMAC"},473 { 0x34, "USB0 RD"},474 { 0x35, "USB0 WR"},475 { 0x36, "USB1 RD"},476 { 0x37, "USB1 WR"},477};478 479static struct l3_flagmux_data *am4372_l3_flagmux[] = {480 &am4372_l3_flagmux_200f,481 &am4372_l3_flagmux_100s,482};483 484static const struct omap_l3 am4372_l3_data = {485 .l3_flagmux = am4372_l3_flagmux,486 .num_modules = ARRAY_SIZE(am4372_l3_flagmux),487 .l3_masters = am4372_l3_masters,488 .num_masters = ARRAY_SIZE(am4372_l3_masters),489 /* All 6 bits of register field used to distinguish initiator */490 .mst_addr_mask = 0x3F,491};492 493#endif /* __OMAP_L3_NOC_H */494