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1/* SPDX-License-Identifier: GPL-2.02 *3 * Driver for AMD network controllers and boards4 *5 * Copyright (C) 2021, Xilinx, Inc.6 * Copyright (C) 2022-2023, Advanced Micro Devices, Inc.7 */8 9#ifndef MC_CDX_PCOL_H10#define MC_CDX_PCOL_H11 12/* The current version of the MCDI protocol. */13#define MCDI_PCOL_VERSION 214 15/*16 * Each MCDI request starts with an MCDI_HEADER, which is a 32bit17 * structure, filled in by the client.18 *19 * 0 7 8 16 20 22 23 24 3120 * | CODE | R | LEN | SEQ | Rsvd | E | R | XFLAGS |21 * | | |22 * | | \--- Response23 * | \------- Error24 * \------------------------------ Resync (always set)25 *26 * The client writes its request into MC shared memory, and rings the27 * doorbell. Each request is completed either by the MC writing28 * back into shared memory, or by writing out an event.29 *30 * All MCDI commands support completion by shared memory response. Each31 * request may also contain additional data (accounted for by HEADER.LEN),32 * and some responses may also contain additional data (again, accounted33 * for by HEADER.LEN).34 *35 * Some MCDI commands support completion by event, in which any associated36 * response data is included in the event.37 *38 * The protocol requires one response to be delivered for every request; a39 * request should not be sent unless the response for the previous request40 * has been received (either by polling shared memory, or by receiving41 * an event).42 */43 44/** Request/Response structure */45#define MCDI_HEADER_OFST 046#define MCDI_HEADER_CODE_LBN 047#define MCDI_HEADER_CODE_WIDTH 748#define MCDI_HEADER_RESYNC_LBN 749#define MCDI_HEADER_RESYNC_WIDTH 150#define MCDI_HEADER_DATALEN_LBN 851#define MCDI_HEADER_DATALEN_WIDTH 852#define MCDI_HEADER_SEQ_LBN 1653#define MCDI_HEADER_SEQ_WIDTH 454#define MCDI_HEADER_RSVD_LBN 2055#define MCDI_HEADER_RSVD_WIDTH 156#define MCDI_HEADER_NOT_EPOCH_LBN 2157#define MCDI_HEADER_NOT_EPOCH_WIDTH 158#define MCDI_HEADER_ERROR_LBN 2259#define MCDI_HEADER_ERROR_WIDTH 160#define MCDI_HEADER_RESPONSE_LBN 2361#define MCDI_HEADER_RESPONSE_WIDTH 162#define MCDI_HEADER_XFLAGS_LBN 2463#define MCDI_HEADER_XFLAGS_WIDTH 864/* Request response using event */65#define MCDI_HEADER_XFLAGS_EVREQ 0x0166/* Request (and signal) early doorbell return */67#define MCDI_HEADER_XFLAGS_DBRET 0x0268 69/* Maximum number of payload bytes */70#define MCDI_CTL_SDU_LEN_MAX_V2 0x40071 72#define MCDI_CTL_SDU_LEN_MAX MCDI_CTL_SDU_LEN_MAX_V273 74/*75 * The MC can generate events for two reasons:76 * - To advance a shared memory request if XFLAGS_EVREQ was set77 * - As a notification (link state, i2c event), controlled78 * via MC_CMD_LOG_CTRL79 *80 * Both events share a common structure:81 *82 * 0 32 33 36 44 52 6083 * | Data | Cont | Level | Src | Code | Rsvd |84 * |85 * \ There is another event pending in this notification86 *87 * If Code==CMDDONE, then the fields are further interpreted as:88 *89 * - LEVEL==INFO Command succeeded90 * - LEVEL==ERR Command failed91 *92 * 0 8 16 24 3293 * | Seq | Datalen | Errno | Rsvd |94 *95 * These fields are taken directly out of the standard MCDI header, i.e.,96 * LEVEL==ERR, Datalen == 0 => Reboot97 *98 * Events can be squirted out of the UART (using LOG_CTRL) without a99 * MCDI header. An event can be distinguished from a MCDI response by100 * examining the first byte which is 0xc0. This corresponds to the101 * non-existent MCDI command MC_CMD_DEBUG_LOG.102 *103 * 0 7 8104 * | command | Resync | = 0xc0105 *106 * Since the event is written in big-endian byte order, this works107 * providing bits 56-63 of the event are 0xc0.108 *109 * 56 60 63110 * | Rsvd | Code | = 0xc0111 *112 * Which means for convenience the event code is 0xc for all MC113 * generated events.114 */115 116/*117 * the errno value may be followed by the (0-based) number of the118 * first argument that could not be processed.119 */120#define MC_CMD_ERR_ARG_OFST 4121 122/* MC_CMD_ERR MCDI error codes. */123/* Operation not permitted. */124#define MC_CMD_ERR_EPERM 0x1125/* Non-existent command target */126#define MC_CMD_ERR_ENOENT 0x2127/* assert() has killed the MC */128#define MC_CMD_ERR_EINTR 0x4129/* I/O failure */130#define MC_CMD_ERR_EIO 0x5131/* Already exists */132#define MC_CMD_ERR_EEXIST 0x6133/* Try again */134#define MC_CMD_ERR_EAGAIN 0xb135/* Out of memory */136#define MC_CMD_ERR_ENOMEM 0xc137/* Caller does not hold required locks */138#define MC_CMD_ERR_EACCES 0xd139/* Resource is currently unavailable (e.g. lock contention) */140#define MC_CMD_ERR_EBUSY 0x10141/* No such device */142#define MC_CMD_ERR_ENODEV 0x13143/* Invalid argument to target */144#define MC_CMD_ERR_EINVAL 0x16145/* No space */146#define MC_CMD_ERR_ENOSPC 0x1c147/* Read-only */148#define MC_CMD_ERR_EROFS 0x1e149/* Broken pipe */150#define MC_CMD_ERR_EPIPE 0x20151/* Out of range */152#define MC_CMD_ERR_ERANGE 0x22153/* Non-recursive resource is already acquired */154#define MC_CMD_ERR_EDEADLK 0x23155/* Operation not implemented */156#define MC_CMD_ERR_ENOSYS 0x26157/* Operation timed out */158#define MC_CMD_ERR_ETIME 0x3e159/* Link has been severed */160#define MC_CMD_ERR_ENOLINK 0x43161/* Protocol error */162#define MC_CMD_ERR_EPROTO 0x47163/* Bad message */164#define MC_CMD_ERR_EBADMSG 0x4a165/* Operation not supported */166#define MC_CMD_ERR_ENOTSUP 0x5f167/* Address not available */168#define MC_CMD_ERR_EADDRNOTAVAIL 0x63169/* Not connected */170#define MC_CMD_ERR_ENOTCONN 0x6b171/* Operation already in progress */172#define MC_CMD_ERR_EALREADY 0x72173/* Stale handle. The handle references resource that no longer exists */174#define MC_CMD_ERR_ESTALE 0x74175/* Resource allocation failed. */176#define MC_CMD_ERR_ALLOC_FAIL 0x1000177/* V-adaptor not found. */178#define MC_CMD_ERR_NO_VADAPTOR 0x1001179/* EVB port not found. */180#define MC_CMD_ERR_NO_EVB_PORT 0x1002181/* V-switch not found. */182#define MC_CMD_ERR_NO_VSWITCH 0x1003183/* Too many VLAN tags. */184#define MC_CMD_ERR_VLAN_LIMIT 0x1004185/* Bad PCI function number. */186#define MC_CMD_ERR_BAD_PCI_FUNC 0x1005187/* Invalid VLAN mode. */188#define MC_CMD_ERR_BAD_VLAN_MODE 0x1006189/* Invalid v-switch type. */190#define MC_CMD_ERR_BAD_VSWITCH_TYPE 0x1007191/* Invalid v-port type. */192#define MC_CMD_ERR_BAD_VPORT_TYPE 0x1008193/* MAC address exists. */194#define MC_CMD_ERR_MAC_EXIST 0x1009195/* Slave core not present */196#define MC_CMD_ERR_SLAVE_NOT_PRESENT 0x100a197/* The datapath is disabled. */198#define MC_CMD_ERR_DATAPATH_DISABLED 0x100b199/* The requesting client is not a function */200#define MC_CMD_ERR_CLIENT_NOT_FN 0x100c201/*202 * The requested operation might require the command to be passed between203 * MCs, and the transport doesn't support that. Should only ever been seen over204 * the UART.205 */206#define MC_CMD_ERR_NO_PRIVILEGE 0x1013207/*208 * Workaround 26807 could not be turned on/off because some functions209 * have already installed filters. See the comment at210 * MC_CMD_WORKAROUND_BUG26807. May also returned for other operations such as211 * sub-variant switching.212 */213#define MC_CMD_ERR_FILTERS_PRESENT 0x1014214/* The clock whose frequency you've attempted to set doesn't exist */215#define MC_CMD_ERR_NO_CLOCK 0x1015216/*217 * Returned by MC_CMD_TESTASSERT if the action that should have caused an218 * assertion failed to do so.219 */220#define MC_CMD_ERR_UNREACHABLE 0x1016221/*222 * This command needs to be processed in the background but there were no223 * resources to do so. Send it again after a command has completed.224 */225#define MC_CMD_ERR_QUEUE_FULL 0x1017226/*227 * The operation could not be completed because the PCIe link has gone228 * away. This error code is never expected to be returned over the TLP229 * transport.230 */231#define MC_CMD_ERR_NO_PCIE 0x1018232/*233 * The operation could not be completed because the datapath has gone234 * away. This is distinct from MC_CMD_ERR_DATAPATH_DISABLED in that the235 * datapath absence may be temporary236 */237#define MC_CMD_ERR_NO_DATAPATH 0x1019238/* The operation could not complete because some VIs are allocated */239#define MC_CMD_ERR_VIS_PRESENT 0x101a240/*241 * The operation could not complete because some PIO buffers are242 * allocated243 */244#define MC_CMD_ERR_PIOBUFS_PRESENT 0x101b245 246/***********************************/247/*248 * MC_CMD_CDX_BUS_ENUM_BUSES249 * CDX bus hosts devices (functions) that are implemented using the Composable250 * DMA subsystem and directly mapped into the memory space of the FGPA PSX251 * Application Processors (APUs). As such, they only apply to the PSX APU side,252 * not the host (PCIe). Unlike PCIe, these devices have no native configuration253 * space or enumeration mechanism, so this message set provides a minimal254 * interface for discovery and management (bus reset, FLR, BME) of such255 * devices. This command returns the number of CDX buses present in the system.256 */257#define MC_CMD_CDX_BUS_ENUM_BUSES 0x1258#define MC_CMD_CDX_BUS_ENUM_BUSES_MSGSET 0x1259#undef MC_CMD_0x1_PRIVILEGE_CTG260 261#define MC_CMD_0x1_PRIVILEGE_CTG SRIOV_CTG_ADMIN262 263/* MC_CMD_CDX_BUS_ENUM_BUSES_IN msgrequest */264#define MC_CMD_CDX_BUS_ENUM_BUSES_IN_LEN 0265 266/* MC_CMD_CDX_BUS_ENUM_BUSES_OUT msgresponse */267#define MC_CMD_CDX_BUS_ENUM_BUSES_OUT_LEN 4268/*269 * Number of CDX buses present in the system. Buses are numbered 0 to270 * BUS_COUNT-1271 */272#define MC_CMD_CDX_BUS_ENUM_BUSES_OUT_BUS_COUNT_OFST 0273#define MC_CMD_CDX_BUS_ENUM_BUSES_OUT_BUS_COUNT_LEN 4274 275/***********************************/276/*277 * MC_CMD_CDX_BUS_ENUM_DEVICES278 * Enumerate CDX bus devices on a given bus279 */280#define MC_CMD_CDX_BUS_ENUM_DEVICES 0x2281#define MC_CMD_CDX_BUS_ENUM_DEVICES_MSGSET 0x2282#undef MC_CMD_0x2_PRIVILEGE_CTG283 284#define MC_CMD_0x2_PRIVILEGE_CTG SRIOV_CTG_ADMIN285 286/* MC_CMD_CDX_BUS_ENUM_DEVICES_IN msgrequest */287#define MC_CMD_CDX_BUS_ENUM_DEVICES_IN_LEN 4288/*289 * Bus number to enumerate, in range 0 to BUS_COUNT-1, as returned by290 * MC_CMD_CDX_BUS_ENUM_BUSES_OUT291 */292#define MC_CMD_CDX_BUS_ENUM_DEVICES_IN_BUS_OFST 0293#define MC_CMD_CDX_BUS_ENUM_DEVICES_IN_BUS_LEN 4294 295/* MC_CMD_CDX_BUS_ENUM_DEVICES_OUT msgresponse */296#define MC_CMD_CDX_BUS_ENUM_DEVICES_OUT_LEN 4297/*298 * Number of devices present on the bus. Devices on the bus are numbered 0 to299 * DEVICE_COUNT-1. Returns EAGAIN if number of devices unknown or if the target300 * devices are not ready (e.g. undergoing a bus reset)301 */302#define MC_CMD_CDX_BUS_ENUM_DEVICES_OUT_DEVICE_COUNT_OFST 0303#define MC_CMD_CDX_BUS_ENUM_DEVICES_OUT_DEVICE_COUNT_LEN 4304 305/***********************************/306/*307 * MC_CMD_CDX_BUS_GET_DEVICE_CONFIG308 * Returns device identification and MMIO/MSI resource data for a CDX device.309 * The expected usage is for the caller to first retrieve the number of devices310 * on the bus using MC_CMD_BUS_ENUM_DEVICES, then loop through the range (0,311 * DEVICE_COUNT - 1), retrieving device resource data. May return EAGAIN if the312 * number of exposed devices or device resources change during enumeration (due313 * to e.g. a PL reload / bus reset), in which case the caller is expected to314 * restart the enumeration loop. MMIO addresses are specified in terms of bus315 * addresses (prior to any potential IOMMU translation). For versal-net, these316 * are equivalent to APU physical addresses. Implementation note - for this to317 * work, the implementation needs to keep state (generation count) per client.318 */319#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG 0x3320#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_MSGSET 0x3321#undef MC_CMD_0x3_PRIVILEGE_CTG322 323#define MC_CMD_0x3_PRIVILEGE_CTG SRIOV_CTG_ADMIN324 325/* MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_IN msgrequest */326#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_IN_LEN 8327/* Device bus number, in range 0 to BUS_COUNT-1 */328#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_IN_BUS_OFST 0329#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_IN_BUS_LEN 4330/* Device number relative to the bus, in range 0 to DEVICE_COUNT-1 for that bus */331#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_IN_DEVICE_OFST 4332#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_IN_DEVICE_LEN 4333 334/* MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT msgresponse */335#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_LEN 88336/* 16-bit Vendor identifier, compliant with PCI-SIG VendorID assignment. */337#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_VENDOR_ID_OFST 0338#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_VENDOR_ID_LEN 2339/* 16-bit Device ID assigned by the vendor */340#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_DEVICE_ID_OFST 2341#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_DEVICE_ID_LEN 2342/*343 * 16-bit Subsystem Vendor ID, , compliant with PCI-SIG VendorID assignment.344 * For further device differentiation, as required. 0 if unused.345 */346#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_SUBSYS_VENDOR_ID_OFST 4347#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_SUBSYS_VENDOR_ID_LEN 2348/*349 * 16-bit Subsystem Device ID assigned by the vendor. For further device350 * differentiation, as required. 0 if unused.351 */352#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_SUBSYS_DEVICE_ID_OFST 6353#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_SUBSYS_DEVICE_ID_LEN 2354/* 24-bit Device Class code, compliant with PCI-SIG Device Class codes */355#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_DEVICE_CLASS_OFST 8356#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_DEVICE_CLASS_LEN 3357/* 8-bit vendor-assigned revision */358#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_DEVICE_REVISION_OFST 11359#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_DEVICE_REVISION_LEN 1360/* Reserved (alignment) */361#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_RESERVED_OFST 12362#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_RESERVED_LEN 4363/* MMIO region 0 base address (bus address), 0 if unused */364#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION0_BASE_OFST 16365#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION0_BASE_LEN 8366#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION0_BASE_LO_OFST 16367#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION0_BASE_LO_LEN 4368#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION0_BASE_LO_LBN 128369#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION0_BASE_LO_WIDTH 32370#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION0_BASE_HI_OFST 20371#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION0_BASE_HI_LEN 4372#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION0_BASE_HI_LBN 160373#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION0_BASE_HI_WIDTH 32374/* MMIO region 0 size, 0 if unused */375#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION0_SIZE_OFST 24376#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION0_SIZE_LEN 8377#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION0_SIZE_LO_OFST 24378#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION0_SIZE_LO_LEN 4379#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION0_SIZE_LO_LBN 192380#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION0_SIZE_LO_WIDTH 32381#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION0_SIZE_HI_OFST 28382#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION0_SIZE_HI_LEN 4383#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION0_SIZE_HI_LBN 224384#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION0_SIZE_HI_WIDTH 32385/* MMIO region 1 base address (bus address), 0 if unused */386#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION1_BASE_OFST 32387#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION1_BASE_LEN 8388#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION1_BASE_LO_OFST 32389#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION1_BASE_LO_LEN 4390#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION1_BASE_LO_LBN 256391#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION1_BASE_LO_WIDTH 32392#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION1_BASE_HI_OFST 36393#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION1_BASE_HI_LEN 4394#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION1_BASE_HI_LBN 288395#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION1_BASE_HI_WIDTH 32396/* MMIO region 1 size, 0 if unused */397#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION1_SIZE_OFST 40398#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION1_SIZE_LEN 8399#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION1_SIZE_LO_OFST 40400#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION1_SIZE_LO_LEN 4401#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION1_SIZE_LO_LBN 320402#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION1_SIZE_LO_WIDTH 32403#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION1_SIZE_HI_OFST 44404#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION1_SIZE_HI_LEN 4405#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION1_SIZE_HI_LBN 352406#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION1_SIZE_HI_WIDTH 32407/* MMIO region 2 base address (bus address), 0 if unused */408#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION2_BASE_OFST 48409#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION2_BASE_LEN 8410#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION2_BASE_LO_OFST 48411#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION2_BASE_LO_LEN 4412#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION2_BASE_LO_LBN 384413#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION2_BASE_LO_WIDTH 32414#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION2_BASE_HI_OFST 52415#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION2_BASE_HI_LEN 4416#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION2_BASE_HI_LBN 416417#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION2_BASE_HI_WIDTH 32418/* MMIO region 2 size, 0 if unused */419#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION2_SIZE_OFST 56420#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION2_SIZE_LEN 8421#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION2_SIZE_LO_OFST 56422#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION2_SIZE_LO_LEN 4423#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION2_SIZE_LO_LBN 448424#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION2_SIZE_LO_WIDTH 32425#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION2_SIZE_HI_OFST 60426#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION2_SIZE_HI_LEN 4427#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION2_SIZE_HI_LBN 480428#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION2_SIZE_HI_WIDTH 32429/* MMIO region 3 base address (bus address), 0 if unused */430#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION3_BASE_OFST 64431#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION3_BASE_LEN 8432#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION3_BASE_LO_OFST 64433#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION3_BASE_LO_LEN 4434#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION3_BASE_LO_LBN 512435#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION3_BASE_LO_WIDTH 32436#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION3_BASE_HI_OFST 68437#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION3_BASE_HI_LEN 4438#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION3_BASE_HI_LBN 544439#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION3_BASE_HI_WIDTH 32440/* MMIO region 3 size, 0 if unused */441#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION3_SIZE_OFST 72442#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION3_SIZE_LEN 8443#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION3_SIZE_LO_OFST 72444#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION3_SIZE_LO_LEN 4445#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION3_SIZE_LO_LBN 576446#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION3_SIZE_LO_WIDTH 32447#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION3_SIZE_HI_OFST 76448#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION3_SIZE_HI_LEN 4449#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION3_SIZE_HI_LBN 608450#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION3_SIZE_HI_WIDTH 32451/* MSI vector count */452#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MSI_COUNT_OFST 80453#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MSI_COUNT_LEN 4454/* Requester ID used by device (SMMU StreamID, GIC ITS DeviceID) */455#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_REQUESTER_ID_OFST 84456#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_REQUESTER_ID_LEN 4457 458/* MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_V2 msgresponse */459#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_V2_LEN 92460/* Requester ID used by device for GIC ITS DeviceID */461#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_V2_REQUESTER_DEVICE_ID_OFST 88462#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_V2_REQUESTER_DEVICE_ID_LEN 4463 464/***********************************/465/*466 * MC_CMD_CDX_BUS_DOWN467 * Asserting reset on the CDX bus causes all devices on the bus to be quiesced.468 * DMA bus mastering is disabled and any pending DMA request are flushed. Once469 * the response is returned, the devices are guaranteed to no longer issue DMA470 * requests or raise MSI interrupts. Further device MMIO accesses may have471 * undefined results. While the bus reset is asserted, any of the enumeration472 * or device configuration MCDIs will fail with EAGAIN. It is only legal to473 * reload the relevant PL region containing CDX devices if the corresponding CDX474 * bus is in reset. Depending on the implementation, the firmware may or may475 * not enforce this restriction and it is up to the caller to make sure this476 * requirement is satisfied.477 */478#define MC_CMD_CDX_BUS_DOWN 0x4479#define MC_CMD_CDX_BUS_DOWN_MSGSET 0x4480 481/* MC_CMD_CDX_BUS_DOWN_IN msgrequest */482#define MC_CMD_CDX_BUS_DOWN_IN_LEN 4483/* Bus number to put in reset, in range 0 to BUS_COUNT-1 */484#define MC_CMD_CDX_BUS_DOWN_IN_BUS_OFST 0485#define MC_CMD_CDX_BUS_DOWN_IN_BUS_LEN 4486 487/*488 * MC_CMD_CDX_BUS_DOWN_OUT msgresponse: The bus is quiesced, no further489 * upstream traffic for devices on this bus.490 */491#define MC_CMD_CDX_BUS_DOWN_OUT_LEN 0492 493/***********************************/494/*495 * MC_CMD_CDX_BUS_UP496 * After bus reset is de-asserted, devices are in a state which is functionally497 * equivalent to each device having been reset with MC_CMD_CDX_DEVICE_RESET. In498 * other words, device logic is reset in a hardware-specific way, MMIO accesses499 * are forwarded to the device, DMA bus mastering is disabled and needs to be500 * re-enabled with MC_CMD_CDX_DEVICE_DMA_ENABLE once the driver is ready to501 * start servicing DMA. If the underlying number of devices or device resources502 * changed (e.g. if PL was reloaded) while the bus was in reset, the bus driver503 * is expected to re-enumerate the bus. Returns EALREADY if the bus was already504 * up before the call.505 */506#define MC_CMD_CDX_BUS_UP 0x5507#define MC_CMD_CDX_BUS_UP_MSGSET 0x5508 509/* MC_CMD_CDX_BUS_UP_IN msgrequest */510#define MC_CMD_CDX_BUS_UP_IN_LEN 4511/* Bus number to take out of reset, in range 0 to BUS_COUNT-1 */512#define MC_CMD_CDX_BUS_UP_IN_BUS_OFST 0513#define MC_CMD_CDX_BUS_UP_IN_BUS_LEN 4514 515/* MC_CMD_CDX_BUS_UP_OUT msgresponse: The bus can now be enumerated. */516#define MC_CMD_CDX_BUS_UP_OUT_LEN 0517 518/***********************************/519/*520 * MC_CMD_CDX_DEVICE_RESET521 * After this call completes, device DMA and interrupts are quiesced, devices522 * logic is reset in a hardware-specific way and DMA bus mastering is disabled.523 */524#define MC_CMD_CDX_DEVICE_RESET 0x6525#define MC_CMD_CDX_DEVICE_RESET_MSGSET 0x6526#undef MC_CMD_0x6_PRIVILEGE_CTG527 528#define MC_CMD_0x6_PRIVILEGE_CTG SRIOV_CTG_ADMIN529 530/* MC_CMD_CDX_DEVICE_RESET_IN msgrequest */531#define MC_CMD_CDX_DEVICE_RESET_IN_LEN 8532/* Device bus number, in range 0 to BUS_COUNT-1 */533#define MC_CMD_CDX_DEVICE_RESET_IN_BUS_OFST 0534#define MC_CMD_CDX_DEVICE_RESET_IN_BUS_LEN 4535/* Device number relative to the bus, in range 0 to DEVICE_COUNT-1 for that bus */536#define MC_CMD_CDX_DEVICE_RESET_IN_DEVICE_OFST 4537#define MC_CMD_CDX_DEVICE_RESET_IN_DEVICE_LEN 4538 539/*540 * MC_CMD_CDX_DEVICE_RESET_OUT msgresponse: The device is quiesced and all541 * pending device initiated DMA has completed.542 */543#define MC_CMD_CDX_DEVICE_RESET_OUT_LEN 0544 545/***********************************/546/*547 * MC_CMD_CDX_DEVICE_CONTROL_SET548 * If BUS_MASTER is set to disabled, device DMA and interrupts are quiesced.549 * Pending DMA requests and MSI interrupts are flushed and no further DMA or550 * interrupts are issued after this command returns. If BUS_MASTER is set to551 * enabled, device is allowed to initiate DMA. Whether interrupts are enabled552 * also depends on the value of MSI_ENABLE bit. Note that, in this case, the553 * device may start DMA before the host receives and processes the MCDI554 * response. MSI_ENABLE masks or unmasks device interrupts only. Note that for555 * interrupts to be delivered to the host, both BUS_MASTER and MSI_ENABLE needs556 * to be set. MMIO_REGIONS_ENABLE enables or disables host accesses to device557 * MMIO regions. Note that an implementation is allowed to permanently set this558 * bit to 1, in which case MC_CMD_CDX_DEVICE_CONTROL_GET will always return 1559 * for this bit, regardless of the value set here.560 */561#define MC_CMD_CDX_DEVICE_CONTROL_SET 0x7562#define MC_CMD_CDX_DEVICE_CONTROL_SET_MSGSET 0x7563#undef MC_CMD_0x7_PRIVILEGE_CTG564 565#define MC_CMD_0x7_PRIVILEGE_CTG SRIOV_CTG_ADMIN566 567/* MC_CMD_CDX_DEVICE_CONTROL_SET_IN msgrequest */568#define MC_CMD_CDX_DEVICE_CONTROL_SET_IN_LEN 12569/* Device bus number, in range 0 to BUS_COUNT-1 */570#define MC_CMD_CDX_DEVICE_CONTROL_SET_IN_BUS_OFST 0571#define MC_CMD_CDX_DEVICE_CONTROL_SET_IN_BUS_LEN 4572/* Device number relative to the bus, in range 0 to DEVICE_COUNT-1 for that bus */573#define MC_CMD_CDX_DEVICE_CONTROL_SET_IN_DEVICE_OFST 4574#define MC_CMD_CDX_DEVICE_CONTROL_SET_IN_DEVICE_LEN 4575#define MC_CMD_CDX_DEVICE_CONTROL_SET_IN_FLAGS_OFST 8576#define MC_CMD_CDX_DEVICE_CONTROL_SET_IN_FLAGS_LEN 4577#define MC_CMD_CDX_DEVICE_CONTROL_SET_IN_BUS_MASTER_ENABLE_OFST 8578#define MC_CMD_CDX_DEVICE_CONTROL_SET_IN_BUS_MASTER_ENABLE_LBN 0579#define MC_CMD_CDX_DEVICE_CONTROL_SET_IN_BUS_MASTER_ENABLE_WIDTH 1580#define MC_CMD_CDX_DEVICE_CONTROL_SET_IN_MSI_ENABLE_OFST 8581#define MC_CMD_CDX_DEVICE_CONTROL_SET_IN_MSI_ENABLE_LBN 1582#define MC_CMD_CDX_DEVICE_CONTROL_SET_IN_MSI_ENABLE_WIDTH 1583#define MC_CMD_CDX_DEVICE_CONTROL_SET_IN_MMIO_REGIONS_ENABLE_OFST 8584#define MC_CMD_CDX_DEVICE_CONTROL_SET_IN_MMIO_REGIONS_ENABLE_LBN 2585#define MC_CMD_CDX_DEVICE_CONTROL_SET_IN_MMIO_REGIONS_ENABLE_WIDTH 1586 587/* MC_CMD_CDX_DEVICE_CONTROL_SET_OUT msgresponse */588#define MC_CMD_CDX_DEVICE_CONTROL_SET_OUT_LEN 0589 590/***********************************/591/*592 * MC_CMD_CDX_DEVICE_CONTROL_GET593 * Returns device DMA, interrupt and MMIO region access control bits. See594 * MC_CMD_CDX_DEVICE_CONTROL_SET for definition of the available control bits.595 */596#define MC_CMD_CDX_DEVICE_CONTROL_GET 0x8597#define MC_CMD_CDX_DEVICE_CONTROL_GET_MSGSET 0x8598#undef MC_CMD_0x8_PRIVILEGE_CTG599 600#define MC_CMD_0x8_PRIVILEGE_CTG SRIOV_CTG_ADMIN601 602/* MC_CMD_CDX_DEVICE_CONTROL_GET_IN msgrequest */603#define MC_CMD_CDX_DEVICE_CONTROL_GET_IN_LEN 8604/* Device bus number, in range 0 to BUS_COUNT-1 */605#define MC_CMD_CDX_DEVICE_CONTROL_GET_IN_BUS_OFST 0606#define MC_CMD_CDX_DEVICE_CONTROL_GET_IN_BUS_LEN 4607/* Device number relative to the bus, in range 0 to DEVICE_COUNT-1 for that bus */608#define MC_CMD_CDX_DEVICE_CONTROL_GET_IN_DEVICE_OFST 4609#define MC_CMD_CDX_DEVICE_CONTROL_GET_IN_DEVICE_LEN 4610 611/* MC_CMD_CDX_DEVICE_CONTROL_GET_OUT msgresponse */612#define MC_CMD_CDX_DEVICE_CONTROL_GET_OUT_LEN 4613#define MC_CMD_CDX_DEVICE_CONTROL_GET_OUT_FLAGS_OFST 0614#define MC_CMD_CDX_DEVICE_CONTROL_GET_OUT_FLAGS_LEN 4615#define MC_CMD_CDX_DEVICE_CONTROL_GET_OUT_BUS_MASTER_ENABLE_OFST 0616#define MC_CMD_CDX_DEVICE_CONTROL_GET_OUT_BUS_MASTER_ENABLE_LBN 0617#define MC_CMD_CDX_DEVICE_CONTROL_GET_OUT_BUS_MASTER_ENABLE_WIDTH 1618#define MC_CMD_CDX_DEVICE_CONTROL_GET_OUT_MSI_ENABLE_OFST 0619#define MC_CMD_CDX_DEVICE_CONTROL_GET_OUT_MSI_ENABLE_LBN 1620#define MC_CMD_CDX_DEVICE_CONTROL_GET_OUT_MSI_ENABLE_WIDTH 1621#define MC_CMD_CDX_DEVICE_CONTROL_GET_OUT_MMIO_REGIONS_ENABLE_OFST 0622#define MC_CMD_CDX_DEVICE_CONTROL_GET_OUT_MMIO_REGIONS_ENABLE_LBN 2623#define MC_CMD_CDX_DEVICE_CONTROL_GET_OUT_MMIO_REGIONS_ENABLE_WIDTH 1624 625/***********************************/626/*627 * MC_CMD_CDX_DEVICE_WRITE_MSI_MSG628 * Populates the MSI message to be used by the hardware to raise the specified629 * interrupt vector. Versal-net implementation specific limitations are that630 * only 4 CDX devices with MSI interrupt capability are supported and all631 * vectors within a device must use the same write address. The command will632 * return EINVAL if any of these limitations is violated.633 */634#define MC_CMD_CDX_DEVICE_WRITE_MSI_MSG 0x9635#define MC_CMD_CDX_DEVICE_WRITE_MSI_MSG_MSGSET 0x9636#undef MC_CMD_0x9_PRIVILEGE_CTG637 638#define MC_CMD_0x9_PRIVILEGE_CTG SRIOV_CTG_ADMIN639 640/* MC_CMD_CDX_DEVICE_WRITE_MSI_MSG_IN msgrequest */641#define MC_CMD_CDX_DEVICE_WRITE_MSI_MSG_IN_LEN 28642/* Device bus number, in range 0 to BUS_COUNT-1 */643#define MC_CMD_CDX_DEVICE_WRITE_MSI_MSG_IN_BUS_OFST 0644#define MC_CMD_CDX_DEVICE_WRITE_MSI_MSG_IN_BUS_LEN 4645/* Device number relative to the bus, in range 0 to DEVICE_COUNT-1 for that bus */646#define MC_CMD_CDX_DEVICE_WRITE_MSI_MSG_IN_DEVICE_OFST 4647#define MC_CMD_CDX_DEVICE_WRITE_MSI_MSG_IN_DEVICE_LEN 4648/*649 * Device-relative MSI vector number. Must be < MSI_COUNT reported for the650 * device.651 */652#define MC_CMD_CDX_DEVICE_WRITE_MSI_MSG_IN_MSI_VECTOR_OFST 8653#define MC_CMD_CDX_DEVICE_WRITE_MSI_MSG_IN_MSI_VECTOR_LEN 4654/* Reserved (alignment) */655#define MC_CMD_CDX_DEVICE_WRITE_MSI_MSG_IN_RESERVED_OFST 12656#define MC_CMD_CDX_DEVICE_WRITE_MSI_MSG_IN_RESERVED_LEN 4657/*658 * MSI address to be used by the hardware. Typically, on ARM systems this659 * address is translated by the IOMMU (if enabled) and it is the responsibility660 * of the entity managing the IOMMU (APU kernel) to supply the correct IOVA661 * here.662 */663#define MC_CMD_CDX_DEVICE_WRITE_MSI_MSG_IN_MSI_ADDRESS_OFST 16664#define MC_CMD_CDX_DEVICE_WRITE_MSI_MSG_IN_MSI_ADDRESS_LEN 8665#define MC_CMD_CDX_DEVICE_WRITE_MSI_MSG_IN_MSI_ADDRESS_LO_OFST 16666#define MC_CMD_CDX_DEVICE_WRITE_MSI_MSG_IN_MSI_ADDRESS_LO_LEN 4667#define MC_CMD_CDX_DEVICE_WRITE_MSI_MSG_IN_MSI_ADDRESS_LO_LBN 128668#define MC_CMD_CDX_DEVICE_WRITE_MSI_MSG_IN_MSI_ADDRESS_LO_WIDTH 32669#define MC_CMD_CDX_DEVICE_WRITE_MSI_MSG_IN_MSI_ADDRESS_HI_OFST 20670#define MC_CMD_CDX_DEVICE_WRITE_MSI_MSG_IN_MSI_ADDRESS_HI_LEN 4671#define MC_CMD_CDX_DEVICE_WRITE_MSI_MSG_IN_MSI_ADDRESS_HI_LBN 160672#define MC_CMD_CDX_DEVICE_WRITE_MSI_MSG_IN_MSI_ADDRESS_HI_WIDTH 32673/*674 * MSI data to be used by the hardware. On versal-net, only the lower 16-bits675 * are used, the remaining bits are ignored and should be set to zero.676 */677#define MC_CMD_CDX_DEVICE_WRITE_MSI_MSG_IN_MSI_DATA_OFST 24678#define MC_CMD_CDX_DEVICE_WRITE_MSI_MSG_IN_MSI_DATA_LEN 4679 680/* MC_CMD_CDX_DEVICE_WRITE_MSI_MSG_OUT msgresponse */681#define MC_CMD_CDX_DEVICE_WRITE_MSI_MSG_OUT_LEN 0682 683/***********************************/684/* MC_CMD_V2_EXTN - Encapsulation for a v2 extended command */685#define MC_CMD_V2_EXTN 0x7f686 687/* MC_CMD_V2_EXTN_IN msgrequest */688#define MC_CMD_V2_EXTN_IN_LEN 4689/* the extended command number */690#define MC_CMD_V2_EXTN_IN_EXTENDED_CMD_LBN 0691#define MC_CMD_V2_EXTN_IN_EXTENDED_CMD_WIDTH 15692#define MC_CMD_V2_EXTN_IN_UNUSED_LBN 15693#define MC_CMD_V2_EXTN_IN_UNUSED_WIDTH 1694/* the actual length of the encapsulated command */695#define MC_CMD_V2_EXTN_IN_ACTUAL_LEN_LBN 16696#define MC_CMD_V2_EXTN_IN_ACTUAL_LEN_WIDTH 10697#define MC_CMD_V2_EXTN_IN_UNUSED2_LBN 26698#define MC_CMD_V2_EXTN_IN_UNUSED2_WIDTH 2699/* Type of command/response */700#define MC_CMD_V2_EXTN_IN_MESSAGE_TYPE_LBN 28701#define MC_CMD_V2_EXTN_IN_MESSAGE_TYPE_WIDTH 4702/*703 * enum: MCDI command directed to versal-net. MCDI responses of this type704 * are not defined.705 */706#define MC_CMD_V2_EXTN_IN_MCDI_MESSAGE_TYPE_PLATFORM 0x2707 708#endif /* MC_CDX_PCOL_H */709