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1/* SPDX-License-Identifier: GPL-2.0 */2/* Copyright (C) 2019-2020 ARM Limited or its affiliates. */3 4#include <linux/bitops.h>5 6#define POWER_DOWN_ENABLE 0x017#define POWER_DOWN_DISABLE 0x008 9/* hwrng quality: bits of true entropy per 1024 bits of input */10#define CC_TRNG_QUALITY 102411 12/* CryptoCell TRNG HW definitions */13#define CC_TRNG_NUM_OF_ROSCS 414/* The number of words generated in the entropy holding register (EHR)15 * 6 words (192 bit) according to HW implementation16 */17#define CC_TRNG_EHR_IN_WORDS 618#define CC_TRNG_EHR_IN_BITS (CC_TRNG_EHR_IN_WORDS * BITS_PER_TYPE(u32))19 20#define CC_HOST_RNG_IRQ_MASK BIT(CC_HOST_RGF_IRR_RNG_INT_BIT_SHIFT)21 22/* RNG interrupt mask */23#define CC_RNG_INT_MASK (BIT(CC_RNG_IMR_EHR_VALID_INT_MASK_BIT_SHIFT) | \24 BIT(CC_RNG_IMR_AUTOCORR_ERR_INT_MASK_BIT_SHIFT) | \25 BIT(CC_RNG_IMR_CRNGT_ERR_INT_MASK_BIT_SHIFT) | \26 BIT(CC_RNG_IMR_VN_ERR_INT_MASK_BIT_SHIFT) | \27 BIT(CC_RNG_IMR_WATCHDOG_INT_MASK_BIT_SHIFT))28 29// --------------------------------------30// BLOCK: RNG31// --------------------------------------32#define CC_RNG_IMR_REG_OFFSET 0x0100UL33#define CC_RNG_IMR_EHR_VALID_INT_MASK_BIT_SHIFT 0x0UL34#define CC_RNG_IMR_AUTOCORR_ERR_INT_MASK_BIT_SHIFT 0x1UL35#define CC_RNG_IMR_CRNGT_ERR_INT_MASK_BIT_SHIFT 0x2UL36#define CC_RNG_IMR_VN_ERR_INT_MASK_BIT_SHIFT 0x3UL37#define CC_RNG_IMR_WATCHDOG_INT_MASK_BIT_SHIFT 0x4UL38#define CC_RNG_ISR_REG_OFFSET 0x0104UL39#define CC_RNG_ISR_EHR_VALID_BIT_SHIFT 0x0UL40#define CC_RNG_ISR_EHR_VALID_BIT_SIZE 0x1UL41#define CC_RNG_ISR_AUTOCORR_ERR_BIT_SHIFT 0x1UL42#define CC_RNG_ISR_AUTOCORR_ERR_BIT_SIZE 0x1UL43#define CC_RNG_ISR_CRNGT_ERR_BIT_SHIFT 0x2UL44#define CC_RNG_ISR_CRNGT_ERR_BIT_SIZE 0x1UL45#define CC_RNG_ISR_WATCHDOG_BIT_SHIFT 0x4UL46#define CC_RNG_ISR_WATCHDOG_BIT_SIZE 0x1UL47#define CC_RNG_ICR_REG_OFFSET 0x0108UL48#define CC_TRNG_CONFIG_REG_OFFSET 0x010CUL49#define CC_EHR_DATA_0_REG_OFFSET 0x0114UL50#define CC_RND_SOURCE_ENABLE_REG_OFFSET 0x012CUL51#define CC_SAMPLE_CNT1_REG_OFFSET 0x0130UL52#define CC_TRNG_DEBUG_CONTROL_REG_OFFSET 0x0138UL53#define CC_RNG_SW_RESET_REG_OFFSET 0x0140UL54#define CC_RNG_CLK_ENABLE_REG_OFFSET 0x01C4UL55#define CC_RNG_DMA_ENABLE_REG_OFFSET 0x01C8UL56#define CC_RNG_WATCHDOG_VAL_REG_OFFSET 0x01D8UL57// --------------------------------------58// BLOCK: SEC_HOST_RGF59// --------------------------------------60#define CC_HOST_RGF_IRR_REG_OFFSET 0x0A00UL61#define CC_HOST_RGF_IRR_RNG_INT_BIT_SHIFT 0xAUL62#define CC_HOST_RGF_IMR_REG_OFFSET 0x0A04UL63#define CC_HOST_RGF_ICR_REG_OFFSET 0x0A08UL64 65#define CC_HOST_POWER_DOWN_EN_REG_OFFSET 0x0A78UL66 67// --------------------------------------68// BLOCK: NVM69// --------------------------------------70#define CC_NVM_IS_IDLE_REG_OFFSET 0x0F10UL71#define CC_NVM_IS_IDLE_VALUE_BIT_SHIFT 0x0UL72#define CC_NVM_IS_IDLE_VALUE_BIT_SIZE 0x1UL73