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1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * Copyright (C) 2005, 2006 IBM Corporation4 * Copyright (C) 2014, 2015 Intel Corporation5 *6 * Authors:7 * Leendert van Doorn <leendert@watson.ibm.com>8 * Kylene Hall <kjhall@us.ibm.com>9 *10 * Maintained by: <tpmdd-devel@lists.sourceforge.net>11 *12 * Device driver for TCG/TCPA TPM (trusted platform module).13 * Specifications at www.trustedcomputinggroup.org14 *15 * This device driver implements the TPM interface as defined in16 * the TCG TPM Interface Spec version 1.2, revision 1.0.17 */18 19#ifndef __TPM_TIS_CORE_H__20#define __TPM_TIS_CORE_H__21 22#include "tpm.h"23 24enum tis_access {25 TPM_ACCESS_VALID = 0x80,26 TPM_ACCESS_ACTIVE_LOCALITY = 0x20,27 TPM_ACCESS_REQUEST_PENDING = 0x04,28 TPM_ACCESS_REQUEST_USE = 0x02,29};30 31enum tis_status {32 TPM_STS_VALID = 0x80,33 TPM_STS_COMMAND_READY = 0x40,34 TPM_STS_GO = 0x20,35 TPM_STS_DATA_AVAIL = 0x10,36 TPM_STS_DATA_EXPECT = 0x08,37 TPM_STS_RESPONSE_RETRY = 0x02,38 TPM_STS_READ_ZERO = 0x23, /* bits that must be zero on read */39};40 41enum tis_int_flags {42 TPM_GLOBAL_INT_ENABLE = 0x80000000,43 TPM_INTF_BURST_COUNT_STATIC = 0x100,44 TPM_INTF_CMD_READY_INT = 0x080,45 TPM_INTF_INT_EDGE_FALLING = 0x040,46 TPM_INTF_INT_EDGE_RISING = 0x020,47 TPM_INTF_INT_LEVEL_LOW = 0x010,48 TPM_INTF_INT_LEVEL_HIGH = 0x008,49 TPM_INTF_LOCALITY_CHANGE_INT = 0x004,50 TPM_INTF_STS_VALID_INT = 0x002,51 TPM_INTF_DATA_AVAIL_INT = 0x001,52};53 54enum tis_defaults {55 TIS_MEM_LEN = 0x5000,56 TIS_SHORT_TIMEOUT = 750, /* ms */57 TIS_LONG_TIMEOUT = 2000, /* 2 sec */58 TIS_TIMEOUT_MIN_ATML = 14700, /* usecs */59 TIS_TIMEOUT_MAX_ATML = 15000, /* usecs */60};61 62/* Some timeout values are needed before it is known whether the chip is63 * TPM 1.0 or TPM 2.0.64 */65#define TIS_TIMEOUT_A_MAX max_t(int, TIS_SHORT_TIMEOUT, TPM2_TIMEOUT_A)66#define TIS_TIMEOUT_B_MAX max_t(int, TIS_LONG_TIMEOUT, TPM2_TIMEOUT_B)67#define TIS_TIMEOUT_C_MAX max_t(int, TIS_SHORT_TIMEOUT, TPM2_TIMEOUT_C)68#define TIS_TIMEOUT_D_MAX max_t(int, TIS_SHORT_TIMEOUT, TPM2_TIMEOUT_D)69 70#define TPM_ACCESS(l) (0x0000 | ((l) << 12))71#define TPM_INT_ENABLE(l) (0x0008 | ((l) << 12))72#define TPM_INT_VECTOR(l) (0x000C | ((l) << 12))73#define TPM_INT_STATUS(l) (0x0010 | ((l) << 12))74#define TPM_INTF_CAPS(l) (0x0014 | ((l) << 12))75#define TPM_STS(l) (0x0018 | ((l) << 12))76#define TPM_STS3(l) (0x001b | ((l) << 12))77#define TPM_DATA_FIFO(l) (0x0024 | ((l) << 12))78 79#define TPM_DID_VID(l) (0x0F00 | ((l) << 12))80#define TPM_RID(l) (0x0F04 | ((l) << 12))81 82#define LPC_CNTRL_OFFSET 0x8483#define LPC_CLKRUN_EN (1 << 2)84#define INTEL_LEGACY_BLK_BASE_ADDR 0xFED0800085#define ILB_REMAP_SIZE 0x10086 87enum tpm_tis_flags {88 TPM_TIS_ITPM_WORKAROUND = 0,89 TPM_TIS_INVALID_STATUS = 1,90 TPM_TIS_DEFAULT_CANCELLATION = 2,91 TPM_TIS_IRQ_TESTED = 3,92};93 94struct tpm_tis_data {95 struct tpm_chip *chip;96 u16 manufacturer_id;97 struct mutex locality_count_mutex;98 unsigned int locality_count;99 int locality;100 int irq;101 struct work_struct free_irq_work;102 unsigned long last_unhandled_irq;103 unsigned int unhandled_irqs;104 unsigned int int_mask;105 unsigned long flags;106 void __iomem *ilb_base_addr;107 u16 clkrun_enabled;108 wait_queue_head_t int_queue;109 wait_queue_head_t read_queue;110 const struct tpm_tis_phy_ops *phy_ops;111 unsigned short rng_quality;112 unsigned int timeout_min; /* usecs */113 unsigned int timeout_max; /* usecs */114};115 116/*117 * IO modes to indicate how many bytes should be read/written at once in the118 * tpm_tis_phy_ops read_bytes/write_bytes calls. Use TPM_TIS_PHYS_8 to119 * receive/transmit byte-wise, TPM_TIS_PHYS_16 for two bytes etc.120 */121enum tpm_tis_io_mode {122 TPM_TIS_PHYS_8,123 TPM_TIS_PHYS_16,124 TPM_TIS_PHYS_32,125};126 127struct tpm_tis_phy_ops {128 /* data is passed in little endian */129 int (*read_bytes)(struct tpm_tis_data *data, u32 addr, u16 len,130 u8 *result, enum tpm_tis_io_mode mode);131 int (*write_bytes)(struct tpm_tis_data *data, u32 addr, u16 len,132 const u8 *value, enum tpm_tis_io_mode mode);133 int (*verify_crc)(struct tpm_tis_data *data, size_t len,134 const u8 *value);135};136 137static inline int tpm_tis_read_bytes(struct tpm_tis_data *data, u32 addr,138 u16 len, u8 *result)139{140 return data->phy_ops->read_bytes(data, addr, len, result,141 TPM_TIS_PHYS_8);142}143 144static inline int tpm_tis_read8(struct tpm_tis_data *data, u32 addr, u8 *result)145{146 return data->phy_ops->read_bytes(data, addr, 1, result, TPM_TIS_PHYS_8);147}148 149static inline int tpm_tis_read16(struct tpm_tis_data *data, u32 addr,150 u16 *result)151{152 __le16 result_le;153 int rc;154 155 rc = data->phy_ops->read_bytes(data, addr, sizeof(u16),156 (u8 *)&result_le, TPM_TIS_PHYS_16);157 if (!rc)158 *result = le16_to_cpu(result_le);159 160 return rc;161}162 163static inline int tpm_tis_read32(struct tpm_tis_data *data, u32 addr,164 u32 *result)165{166 __le32 result_le;167 int rc;168 169 rc = data->phy_ops->read_bytes(data, addr, sizeof(u32),170 (u8 *)&result_le, TPM_TIS_PHYS_32);171 if (!rc)172 *result = le32_to_cpu(result_le);173 174 return rc;175}176 177static inline int tpm_tis_write_bytes(struct tpm_tis_data *data, u32 addr,178 u16 len, const u8 *value)179{180 return data->phy_ops->write_bytes(data, addr, len, value,181 TPM_TIS_PHYS_8);182}183 184static inline int tpm_tis_write8(struct tpm_tis_data *data, u32 addr, u8 value)185{186 return data->phy_ops->write_bytes(data, addr, 1, &value,187 TPM_TIS_PHYS_8);188}189 190static inline int tpm_tis_write32(struct tpm_tis_data *data, u32 addr,191 u32 value)192{193 __le32 value_le;194 int rc;195 196 value_le = cpu_to_le32(value);197 rc = data->phy_ops->write_bytes(data, addr, sizeof(u32),198 (u8 *)&value_le, TPM_TIS_PHYS_32);199 return rc;200}201 202static inline int tpm_tis_verify_crc(struct tpm_tis_data *data, size_t len,203 const u8 *value)204{205 if (!data->phy_ops->verify_crc)206 return 0;207 return data->phy_ops->verify_crc(data, len, value);208}209 210static inline bool is_bsw(void)211{212#ifdef CONFIG_X86213 return (boot_cpu_data.x86_vfm == INTEL_ATOM_AIRMONT) ? 1 : 0;214#else215 return false;216#endif217}218 219void tpm_tis_remove(struct tpm_chip *chip);220int tpm_tis_core_init(struct device *dev, struct tpm_tis_data *priv, int irq,221 const struct tpm_tis_phy_ops *phy_ops,222 acpi_handle acpi_dev_handle);223 224#ifdef CONFIG_PM_SLEEP225int tpm_tis_resume(struct device *dev);226#endif227 228#endif229