127 lines · c
1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * linux/drivers/misc/xillybus.h4 *5 * Copyright 2011 Xillybus Ltd, http://xillybus.com6 *7 * Header file for the Xillybus FPGA/host framework.8 */9 10#ifndef __XILLYBUS_H11#define __XILLYBUS_H12 13#include <linux/list.h>14#include <linux/device.h>15#include <linux/dma-mapping.h>16#include <linux/interrupt.h>17#include <linux/sched.h>18#include <linux/cdev.h>19#include <linux/spinlock.h>20#include <linux/mutex.h>21#include <linux/workqueue.h>22 23struct xilly_endpoint_hardware;24 25struct xilly_buffer {26 void *addr;27 dma_addr_t dma_addr;28 int end_offset; /* Counting elements, not bytes */29};30 31struct xilly_idt_handle {32 unsigned char *chandesc;33 unsigned char *names;34 int names_len;35 int entries;36};37 38/*39 * Read-write confusion: wr_* and rd_* notation sticks to FPGA view, so40 * wr_* buffers are those consumed by read(), since the FPGA writes to them41 * and vice versa.42 */43 44struct xilly_channel {45 struct xilly_endpoint *endpoint;46 int chan_num;47 int log2_element_size;48 int seekable;49 50 struct xilly_buffer **wr_buffers; /* FPGA writes, driver reads! */51 int num_wr_buffers;52 unsigned int wr_buf_size; /* In bytes */53 int wr_fpga_buf_idx;54 int wr_host_buf_idx;55 int wr_host_buf_pos;56 int wr_empty;57 int wr_ready; /* Significant only when wr_empty == 1 */58 int wr_sleepy;59 int wr_eof;60 int wr_hangup;61 spinlock_t wr_spinlock;62 struct mutex wr_mutex;63 wait_queue_head_t wr_wait;64 wait_queue_head_t wr_ready_wait;65 int wr_ref_count;66 int wr_synchronous;67 int wr_allow_partial;68 int wr_exclusive_open;69 int wr_supports_nonempty;70 71 struct xilly_buffer **rd_buffers; /* FPGA reads, driver writes! */72 int num_rd_buffers;73 unsigned int rd_buf_size; /* In bytes */74 int rd_fpga_buf_idx;75 int rd_host_buf_pos;76 int rd_host_buf_idx;77 int rd_full;78 spinlock_t rd_spinlock;79 struct mutex rd_mutex;80 wait_queue_head_t rd_wait;81 int rd_ref_count;82 int rd_allow_partial;83 int rd_synchronous;84 int rd_exclusive_open;85 struct delayed_work rd_workitem;86 unsigned char rd_leftovers[4];87};88 89struct xilly_endpoint {90 struct device *dev;91 struct module *owner;92 93 int dma_using_dac; /* =1 if 64-bit DMA is used, =0 otherwise. */94 __iomem void *registers;95 int fatal_error;96 97 struct mutex register_mutex;98 wait_queue_head_t ep_wait;99 100 int num_channels; /* EXCLUDING message buffer */101 struct xilly_channel **channels;102 int msg_counter;103 int failed_messages;104 int idtlen;105 106 u32 *msgbuf_addr;107 dma_addr_t msgbuf_dma_addr;108 unsigned int msg_buf_size;109};110 111struct xilly_mapping {112 struct device *device;113 dma_addr_t dma_addr;114 size_t size;115 int direction;116};117 118irqreturn_t xillybus_isr(int irq, void *data);119 120struct xilly_endpoint *xillybus_init_endpoint(struct device *dev);121 122int xillybus_endpoint_discovery(struct xilly_endpoint *endpoint);123 124void xillybus_endpoint_remove(struct xilly_endpoint *endpoint);125 126#endif /* __XILLYBUS_H */127