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1# SPDX-License-Identifier: GPL-2.02 3config HAVE_CLK4 bool5 help6 The <linux/clk.h> calls support software clock gating and7 thus are a key power management tool on many systems.8 9config HAVE_CLK_PREPARE10 bool11 12config HAVE_LEGACY_CLK # TODO: Remove once all legacy users are migrated13 bool14 select HAVE_CLK15 help16 Select this option when the clock API in <linux/clk.h> is implemented17 by platform/architecture code. This method is deprecated. Modern18 code should select COMMON_CLK instead and not define a custom19 'struct clk'.20 21menuconfig COMMON_CLK22 bool "Common Clock Framework"23 depends on !HAVE_LEGACY_CLK24 select HAVE_CLK_PREPARE25 select HAVE_CLK26 select RATIONAL27 help28 The common clock framework is a single definition of struct29 clk, useful across many platforms, as well as an30 implementation of the clock API in include/linux/clk.h.31 Architectures utilizing the common struct clk should select32 this option.33 34if COMMON_CLK35 36config COMMON_CLK_WM831X37 tristate "Clock driver for WM831x/2x PMICs"38 depends on MFD_WM831X39 help40 Supports the clocking subsystem of the WM831x/2x series of41 PMICs from Wolfson Microelectronics.42 43source "drivers/clk/versatile/Kconfig"44 45config CLK_HSDK46 bool "PLL Driver for HSDK platform"47 depends on ARC_SOC_HSDK || COMPILE_TEST48 depends on HAS_IOMEM49 help50 This driver supports the HSDK core, system, ddr, tunnel and hdmi PLLs51 control.52 53config LMK0483254 tristate "Ti LMK04832 JESD204B Compliant Clock Jitter Cleaner"55 depends on SPI56 select REGMAP_SPI57 help58 Say yes here to build support for Texas Instruments' LMK04832 Ultra59 Low-Noise JESD204B Compliant Clock Jitter Cleaner With Dual Loop PLLs60 61config COMMON_CLK_APPLE_NCO62 tristate "Clock driver for Apple SoC NCOs"63 depends on ARCH_APPLE || COMPILE_TEST64 default ARCH_APPLE65 help66 This driver supports NCO (Numerically Controlled Oscillator) blocks67 found on Apple SoCs such as t8103 (M1). The blocks are typically68 generators of audio clocks.69 70config COMMON_CLK_MAX7768671 tristate "Clock driver for Maxim 77620/77686/77802 MFD"72 depends on MFD_MAX77686 || MFD_MAX77620 || COMPILE_TEST73 help74 This driver supports Maxim 77620/77686/77802 crystal oscillator75 clock.76 77config COMMON_CLK_MAX948578 tristate "Maxim 9485 Programmable Clock Generator"79 depends on I2C80 help81 This driver supports Maxim 9485 Programmable Audio Clock Generator82 83config COMMON_CLK_RK80884 tristate "Clock driver for RK805/RK808/RK809/RK817/RK818"85 depends on MFD_RK8XX86 help87 This driver supports RK805, RK809 and RK817, RK808 and RK818 crystal oscillator clock.88 These multi-function devices have two fixed-rate oscillators, clocked at 32KHz each.89 Clkout1 is always on, Clkout2 can off by control register.90 91config COMMON_CLK_HI655X92 tristate "Clock driver for Hi655x" if EXPERT93 depends on (MFD_HI655X_PMIC || COMPILE_TEST)94 select REGMAP95 default MFD_HI655X_PMIC96 help97 This driver supports the hi655x PMIC clock. This98 multi-function device has one fixed-rate oscillator, clocked99 at 32KHz.100 101config COMMON_CLK_SCMI102 tristate "Clock driver controlled via SCMI interface"103 depends on ARM_SCMI_PROTOCOL || COMPILE_TEST104 help105 This driver provides support for clocks that are controlled106 by firmware that implements the SCMI interface.107 108 This driver uses SCMI Message Protocol to interact with the109 firmware providing all the clock controls.110 111config COMMON_CLK_SCPI112 tristate "Clock driver controlled via SCPI interface"113 depends on ARM_SCPI_PROTOCOL || COMPILE_TEST114 help115 This driver provides support for clocks that are controlled116 by firmware that implements the SCPI interface.117 118 This driver uses SCPI Message Protocol to interact with the119 firmware providing all the clock controls.120 121config COMMON_CLK_SI5341122 tristate "Clock driver for SiLabs 5341 and 5340 A/B/C/D devices"123 depends on I2C124 select REGMAP_I2C125 help126 This driver supports Silicon Labs Si5341 and Si5340 programmable clock127 generators. Not all features of these chips are currently supported128 by the driver, in particular it only supports XTAL input. The chip can129 be pre-programmed to support other configurations and features not yet130 implemented in the driver.131 132config COMMON_CLK_SI5351133 tristate "Clock driver for SiLabs 5351A/B/C"134 depends on I2C135 select REGMAP_I2C136 help137 This driver supports Silicon Labs 5351A/B/C programmable clock138 generators.139 140config COMMON_CLK_SI514141 tristate "Clock driver for SiLabs 514 devices"142 depends on I2C143 depends on OF144 select REGMAP_I2C145 help146 This driver supports the Silicon Labs 514 programmable clock147 generator.148 149config COMMON_CLK_SI544150 tristate "Clock driver for SiLabs 544 devices"151 depends on I2C152 select REGMAP_I2C153 help154 This driver supports the Silicon Labs 544 programmable clock155 generator.156 157config COMMON_CLK_SI570158 tristate "Clock driver for SiLabs 570 and compatible devices"159 depends on I2C160 depends on OF161 select REGMAP_I2C162 help163 This driver supports Silicon Labs 570/571/598/599 programmable164 clock generators.165 166config COMMON_CLK_BM1880167 bool "Clock driver for Bitmain BM1880 SoC"168 depends on ARCH_BITMAIN || COMPILE_TEST169 default ARCH_BITMAIN170 help171 This driver supports the clocks on Bitmain BM1880 SoC.172 173config COMMON_CLK_CDCE706174 tristate "Clock driver for TI CDCE706 clock synthesizer"175 depends on I2C176 select REGMAP_I2C177 help178 This driver supports TI CDCE706 programmable 3-PLL clock synthesizer.179 180config COMMON_CLK_TPS68470181 tristate "Clock Driver for TI TPS68470 PMIC"182 depends on I2C183 depends on INTEL_SKL_INT3472 || COMPILE_TEST184 select REGMAP_I2C185 help186 This driver supports the clocks provided by the TPS68470 PMIC.187 188config COMMON_CLK_CDCE925189 tristate "Clock driver for TI CDCE913/925/937/949 devices"190 depends on I2C191 depends on OF192 select REGMAP_I2C193 help194 This driver supports the TI CDCE913/925/937/949 programmable clock195 synthesizer. Each chip has different number of PLLs and outputs.196 For example, the CDCE925 contains two PLLs with spread-spectrum197 clocking support and five output dividers. The driver only supports198 the following setup, and uses a fixed setting for the output muxes.199 Y1 is derived from the input clock200 Y2 and Y3 derive from PLL1201 Y4 and Y5 derive from PLL2202 Given a target output frequency, the driver will set the PLL and203 divider to best approximate the desired output.204 205config COMMON_CLK_CS2000_CP206 tristate "Clock driver for CS2000 Fractional-N Clock Synthesizer & Clock Multiplier"207 depends on I2C208 select REGMAP_I2C209 help210 If you say yes here you get support for the CS2000 clock multiplier.211 212config COMMON_CLK_EN7523213 bool "Clock driver for Airoha EN7523 SoC system clocks"214 depends on OF215 depends on ARCH_AIROHA || COMPILE_TEST216 default ARCH_AIROHA217 help218 This driver provides the fixed clocks and gates present on Airoha219 ARM silicon.220 221config COMMON_CLK_EP93XX222 tristate "Clock driver for Cirrus Logic ep93xx SoC"223 depends on ARCH_EP93XX || COMPILE_TEST224 select AUXILIARY_BUS225 select REGMAP_MMIO226 help227 This driver supports the SoC clocks on the Cirrus Logic ep93xx.228 229config COMMON_CLK_FSL_FLEXSPI230 tristate "Clock driver for FlexSPI on Layerscape SoCs"231 depends on ARCH_LAYERSCAPE || COMPILE_TEST232 default ARCH_LAYERSCAPE && SPI_NXP_FLEXSPI233 help234 On Layerscape SoCs there is a special clock for the FlexSPI235 interface.236 237config COMMON_CLK_FSL_SAI238 bool "Clock driver for BCLK of Freescale SAI cores"239 depends on ARCH_LAYERSCAPE || COMPILE_TEST240 help241 This driver supports the Freescale SAI (Synchronous Audio Interface)242 to be used as a generic clock output. Some SoCs have restrictions243 regarding the possible pin multiplexer settings. Eg. on some SoCs244 two SAI interfaces can only be enabled together. If just one is245 needed, the BCLK pin of the second one can be used as general246 purpose clock output. Ideally, it can be used to drive an audio247 codec (sometimes known as MCLK).248 249config COMMON_CLK_GEMINI250 bool "Clock driver for Cortina Systems Gemini SoC"251 depends on ARCH_GEMINI || COMPILE_TEST252 select MFD_SYSCON253 select RESET_CONTROLLER254 help255 This driver supports the SoC clocks on the Cortina Systems Gemini256 platform, also known as SL3516 or CS3516.257 258config COMMON_CLK_LAN966X259 tristate "Generic Clock Controller driver for LAN966X SoC"260 depends on HAS_IOMEM261 depends on OF262 depends on SOC_LAN966 || COMPILE_TEST263 help264 This driver provides support for Generic Clock Controller(GCK) on265 LAN966X SoC. GCK generates and supplies clock to various peripherals266 within the SoC.267 268config COMMON_CLK_ASPEED269 bool "Clock driver for Aspeed BMC SoCs"270 depends on ARCH_ASPEED || COMPILE_TEST271 default ARCH_ASPEED272 select MFD_SYSCON273 select RESET_CONTROLLER274 help275 This driver supports the SoC clocks on the Aspeed BMC platforms.276 277 The G4 and G5 series, including the ast2400 and ast2500, are supported278 by this driver.279 280config COMMON_CLK_S2MPS11281 tristate "Clock driver for S2MPS1X/S5M8767 MFD"282 depends on MFD_SEC_CORE || COMPILE_TEST283 help284 This driver supports S2MPS11/S2MPS14/S5M8767 crystal oscillator285 clock. These multi-function devices have two (S2MPS14) or three286 (S2MPS11, S5M8767) fixed-rate oscillators, clocked at 32KHz each.287 288config CLK_TWL289 tristate "Clock driver for the TWL PMIC family"290 depends on TWL4030_CORE291 help292 Enable support for controlling the clock resources on TWL family293 PMICs. These devices have some 32K clock outputs which can be294 controlled by software. For now, only the TWL6032 clocks are295 supported.296 297config CLK_TWL6040298 tristate "External McPDM functional clock from twl6040"299 depends on TWL6040_CORE300 help301 Enable the external functional clock support on OMAP4+ platforms for302 McPDM. McPDM module is using the external bit clock on the McPDM bus303 as functional clock.304 305config COMMON_CLK_AXI_CLKGEN306 tristate "AXI clkgen driver"307 depends on HAS_IOMEM || COMPILE_TEST308 depends on OF309 help310 Support for the Analog Devices axi-clkgen pcore clock generator for Xilinx311 FPGAs. It is commonly used in Analog Devices' reference designs.312 313config CLK_QORIQ314 bool "Clock driver for Freescale QorIQ platforms"315 depends on OF316 depends on PPC_E500MC || SOC_LS1021A || ARCH_LAYERSCAPE || COMPILE_TEST317 help318 This adds the clock driver support for Freescale QorIQ platforms319 using common clock framework.320 321config CLK_LS1028A_PLLDIG322 tristate "Clock driver for LS1028A Display output"323 depends on ARCH_LAYERSCAPE || COMPILE_TEST324 default ARCH_LAYERSCAPE325 help326 This driver support the Display output interfaces(LCD, DPHY) pixel clocks327 of the QorIQ Layerscape LS1028A, as implemented TSMC CLN28HPM PLL. Not all328 features of the PLL are currently supported by the driver. By default,329 configured bypass mode with this PLL.330 331config COMMON_CLK_XGENE332 bool "Clock driver for APM XGene SoC"333 default ARCH_XGENE334 depends on ARM64 || COMPILE_TEST335 help336 Support for the APM X-Gene SoC reference, PLL, and device clocks.337 338config COMMON_CLK_LOCHNAGAR339 tristate "Cirrus Logic Lochnagar clock driver"340 depends on MFD_LOCHNAGAR341 help342 This driver supports the clocking features of the Cirrus Logic343 Lochnagar audio development board.344 345config COMMON_CLK_LOONGSON2346 bool "Clock driver for Loongson-2 SoC"347 depends on LOONGARCH || COMPILE_TEST348 help349 This driver provides support for clock controller on Loongson-2 SoC.350 The clock controller can generates and supplies clock to various351 peripherals within the SoC.352 Say Y here to support Loongson-2 SoC clock driver.353 354config COMMON_CLK_NXP355 def_bool COMMON_CLK && (ARCH_LPC18XX || ARCH_LPC32XX)356 select REGMAP_MMIO if ARCH_LPC32XX357 select MFD_SYSCON if ARCH_LPC18XX358 help359 Support for clock providers on NXP platforms.360 361config COMMON_CLK_PALMAS362 tristate "Clock driver for TI Palmas devices"363 depends on MFD_PALMAS364 help365 This driver supports TI Palmas devices 32KHz output KG and KG_AUDIO366 using common clock framework.367 368config COMMON_CLK_PWM369 tristate "Clock driver for PWMs used as clock outputs"370 depends on PWM371 help372 Adapter driver so that any PWM output can be (mis)used as clock signal373 at 50% duty cycle.374 375config COMMON_CLK_PXA376 def_bool COMMON_CLK && ARCH_PXA377 help378 Support for the Marvell PXA SoC.379 380config COMMON_CLK_RS9_PCIE381 tristate "Clock driver for Renesas 9-series PCIe clock generators"382 depends on I2C383 depends on OF384 select REGMAP_I2C385 help386 This driver supports the Renesas 9-series PCIe clock generator387 models 9FGV/9DBV/9DMV/9FGL/9DML/9QXL/9SQ.388 389config COMMON_CLK_SI521XX390 tristate "Clock driver for SkyWorks Si521xx PCIe clock generators"391 depends on I2C392 depends on OF393 select REGMAP_I2C394 help395 This driver supports the SkyWorks Si521xx PCIe clock generator396 models Si52144/Si52146/Si52147.397 398config COMMON_CLK_VC3399 tristate "Clock driver for Renesas VersaClock 3 devices"400 depends on I2C401 depends on OF402 select REGMAP_I2C403 help404 This driver supports the Renesas VersaClock 3 programmable clock405 generators.406 407config COMMON_CLK_VC5408 tristate "Clock driver for IDT VersaClock 5,6 devices"409 depends on I2C410 depends on OF411 select REGMAP_I2C412 help413 This driver supports the IDT VersaClock 5 and VersaClock 6414 programmable clock generators.415 416config COMMON_CLK_VC7417 tristate "Clock driver for Renesas Versaclock 7 devices"418 depends on I2C419 depends on OF420 select REGMAP_I2C421 help422 Renesas Versaclock7 is a family of configurable clock generator423 and jitter attenuator ICs with fractional and integer dividers.424 425config COMMON_CLK_STM32F426 def_bool COMMON_CLK && (MACH_STM32F429 || MACH_STM32F469 || MACH_STM32F746)427 help428 Support for stm32f4 and stm32f7 SoC families clocks429 430config COMMON_CLK_STM32H7431 def_bool COMMON_CLK && MACH_STM32H743432 help433 Support for stm32h7 SoC family clocks434 435config COMMON_CLK_MMP2436 def_bool COMMON_CLK && (MACH_MMP2_DT || MACH_MMP3_DT)437 help438 Support for Marvell MMP2 and MMP3 SoC clocks439 440config COMMON_CLK_MMP2_AUDIO441 tristate "Clock driver for MMP2 Audio subsystem"442 depends on COMMON_CLK_MMP2 || COMPILE_TEST443 help444 This driver supports clocks for Audio subsystem on MMP2 SoC.445 446config COMMON_CLK_BD718XX447 tristate "Clock driver for 32K clk gates on ROHM PMICs"448 depends on MFD_ROHM_BD718XX || MFD_ROHM_BD71828449 help450 This driver supports ROHM BD71837, BD71847, BD71850, BD71815451 and BD71828 PMICs clock gates.452 453config COMMON_CLK_FIXED_MMIO454 bool "Clock driver for Memory Mapped Fixed values"455 depends on COMMON_CLK && OF456 depends on HAS_IOMEM457 help458 Support for Memory Mapped IO Fixed clocks459 460config COMMON_CLK_K210461 bool "Clock driver for the Canaan Kendryte K210 SoC"462 depends on OF && RISCV && SOC_CANAAN_K210463 default SOC_CANAAN_K210464 help465 Support for the Canaan Kendryte K210 RISC-V SoC clocks.466 467config COMMON_CLK_SP7021468 tristate "Clock driver for Sunplus SP7021 SoC"469 depends on SOC_SP7021 || COMPILE_TEST470 default SOC_SP7021471 help472 This driver supports the Sunplus SP7021 SoC clocks.473 It implements SP7021 PLLs/gate.474 Not all features of the PLL are currently supported475 by the driver.476 477source "drivers/clk/actions/Kconfig"478source "drivers/clk/analogbits/Kconfig"479source "drivers/clk/baikal-t1/Kconfig"480source "drivers/clk/bcm/Kconfig"481source "drivers/clk/hisilicon/Kconfig"482source "drivers/clk/imgtec/Kconfig"483source "drivers/clk/imx/Kconfig"484source "drivers/clk/ingenic/Kconfig"485source "drivers/clk/keystone/Kconfig"486source "drivers/clk/mediatek/Kconfig"487source "drivers/clk/meson/Kconfig"488source "drivers/clk/mstar/Kconfig"489source "drivers/clk/microchip/Kconfig"490source "drivers/clk/mvebu/Kconfig"491source "drivers/clk/nuvoton/Kconfig"492source "drivers/clk/pistachio/Kconfig"493source "drivers/clk/qcom/Kconfig"494source "drivers/clk/ralink/Kconfig"495source "drivers/clk/renesas/Kconfig"496source "drivers/clk/rockchip/Kconfig"497source "drivers/clk/samsung/Kconfig"498source "drivers/clk/sifive/Kconfig"499source "drivers/clk/socfpga/Kconfig"500source "drivers/clk/sophgo/Kconfig"501source "drivers/clk/sprd/Kconfig"502source "drivers/clk/starfive/Kconfig"503source "drivers/clk/sunxi/Kconfig"504source "drivers/clk/sunxi-ng/Kconfig"505source "drivers/clk/tegra/Kconfig"506source "drivers/clk/thead/Kconfig"507source "drivers/clk/stm32/Kconfig"508source "drivers/clk/ti/Kconfig"509source "drivers/clk/uniphier/Kconfig"510source "drivers/clk/visconti/Kconfig"511source "drivers/clk/x86/Kconfig"512source "drivers/clk/xilinx/Kconfig"513source "drivers/clk/zynqmp/Kconfig"514 515# Kunit test cases516config CLK_KUNIT_TEST517 tristate "Basic Clock Framework Kunit Tests" if !KUNIT_ALL_TESTS518 depends on KUNIT519 default KUNIT_ALL_TESTS520 select OF_OVERLAY if OF521 select DTC522 help523 Kunit tests for the common clock framework.524 525config CLK_FIXED_RATE_KUNIT_TEST526 tristate "Basic fixed rate clk type KUnit test" if !KUNIT_ALL_TESTS527 depends on KUNIT528 default KUNIT_ALL_TESTS529 select OF_OVERLAY if OF530 select DTC531 help532 KUnit tests for the basic fixed rate clk type.533 534config CLK_GATE_KUNIT_TEST535 tristate "Basic gate type Kunit test" if !KUNIT_ALL_TESTS536 depends on KUNIT537 depends on !S390538 default KUNIT_ALL_TESTS539 help540 Kunit test for the basic clk gate type.541 542config CLK_FD_KUNIT_TEST543 tristate "Basic fractional divider type Kunit test" if !KUNIT_ALL_TESTS544 depends on KUNIT545 default KUNIT_ALL_TESTS546 help547 Kunit test for the clk-fractional-divider type.548 549endif550