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1// SPDX-License-Identifier: GPL-2.02#include <linux/clk-provider.h>3#include <linux/mfd/syscon.h>4#include <linux/slab.h>5 6#include <dt-bindings/clock/at91.h>7 8#include "pmc.h"9 10struct sck {11 char *n;12 char *p;13 u8 id;14};15 16struct pck {17 char *n;18 u8 id;19};20 21struct at91sam926x_data {22 const struct clk_pll_layout *plla_layout;23 const struct clk_pll_characteristics *plla_characteristics;24 const struct clk_pll_layout *pllb_layout;25 const struct clk_pll_characteristics *pllb_characteristics;26 const struct clk_master_characteristics *mck_characteristics;27 const struct sck *sck;28 const struct pck *pck;29 u8 num_sck;30 u8 num_pck;31 u8 num_progck;32 bool has_slck;33};34 35static DEFINE_SPINLOCK(at91sam9260_mck_lock);36 37static const struct clk_master_characteristics sam9260_mck_characteristics = {38 .output = { .min = 0, .max = 105000000 },39 .divisors = { 1, 2, 4, 0 },40};41 42static u8 sam9260_plla_out[] = { 0, 2 };43 44static u16 sam9260_plla_icpll[] = { 1, 1 };45 46static const struct clk_range sam9260_plla_outputs[] = {47 { .min = 80000000, .max = 160000000 },48 { .min = 150000000, .max = 240000000 },49};50 51static const struct clk_pll_characteristics sam9260_plla_characteristics = {52 .input = { .min = 1000000, .max = 32000000 },53 .num_output = ARRAY_SIZE(sam9260_plla_outputs),54 .output = sam9260_plla_outputs,55 .icpll = sam9260_plla_icpll,56 .out = sam9260_plla_out,57};58 59static u8 sam9260_pllb_out[] = { 1 };60 61static u16 sam9260_pllb_icpll[] = { 1 };62 63static const struct clk_range sam9260_pllb_outputs[] = {64 { .min = 70000000, .max = 130000000 },65};66 67static const struct clk_pll_characteristics sam9260_pllb_characteristics = {68 .input = { .min = 1000000, .max = 5000000 },69 .num_output = ARRAY_SIZE(sam9260_pllb_outputs),70 .output = sam9260_pllb_outputs,71 .icpll = sam9260_pllb_icpll,72 .out = sam9260_pllb_out,73};74 75static const struct sck at91sam9260_systemck[] = {76 { .n = "uhpck", .p = "usbck", .id = 6 },77 { .n = "udpck", .p = "usbck", .id = 7 },78 { .n = "pck0", .p = "prog0", .id = 8 },79 { .n = "pck1", .p = "prog1", .id = 9 },80};81 82static const struct pck at91sam9260_periphck[] = {83 { .n = "pioA_clk", .id = 2 },84 { .n = "pioB_clk", .id = 3 },85 { .n = "pioC_clk", .id = 4 },86 { .n = "adc_clk", .id = 5 },87 { .n = "usart0_clk", .id = 6 },88 { .n = "usart1_clk", .id = 7 },89 { .n = "usart2_clk", .id = 8 },90 { .n = "mci0_clk", .id = 9 },91 { .n = "udc_clk", .id = 10 },92 { .n = "twi0_clk", .id = 11 },93 { .n = "spi0_clk", .id = 12 },94 { .n = "spi1_clk", .id = 13 },95 { .n = "ssc0_clk", .id = 14 },96 { .n = "tc0_clk", .id = 17 },97 { .n = "tc1_clk", .id = 18 },98 { .n = "tc2_clk", .id = 19 },99 { .n = "ohci_clk", .id = 20 },100 { .n = "macb0_clk", .id = 21 },101 { .n = "isi_clk", .id = 22 },102 { .n = "usart3_clk", .id = 23 },103 { .n = "uart0_clk", .id = 24 },104 { .n = "uart1_clk", .id = 25 },105 { .n = "tc3_clk", .id = 26 },106 { .n = "tc4_clk", .id = 27 },107 { .n = "tc5_clk", .id = 28 },108};109 110static struct at91sam926x_data at91sam9260_data = {111 .plla_layout = &at91rm9200_pll_layout,112 .plla_characteristics = &sam9260_plla_characteristics,113 .pllb_layout = &at91rm9200_pll_layout,114 .pllb_characteristics = &sam9260_pllb_characteristics,115 .mck_characteristics = &sam9260_mck_characteristics,116 .sck = at91sam9260_systemck,117 .num_sck = ARRAY_SIZE(at91sam9260_systemck),118 .pck = at91sam9260_periphck,119 .num_pck = ARRAY_SIZE(at91sam9260_periphck),120 .num_progck = 2,121 .has_slck = true,122};123 124static const struct clk_master_characteristics sam9g20_mck_characteristics = {125 .output = { .min = 0, .max = 133000000 },126 .divisors = { 1, 2, 4, 6 },127};128 129static u8 sam9g20_plla_out[] = { 0, 1, 2, 3, 0, 1, 2, 3 };130 131static u16 sam9g20_plla_icpll[] = { 0, 0, 0, 0, 1, 1, 1, 1 };132 133static const struct clk_range sam9g20_plla_outputs[] = {134 { .min = 745000000, .max = 800000000 },135 { .min = 695000000, .max = 750000000 },136 { .min = 645000000, .max = 700000000 },137 { .min = 595000000, .max = 650000000 },138 { .min = 545000000, .max = 600000000 },139 { .min = 495000000, .max = 550000000 },140 { .min = 445000000, .max = 500000000 },141 { .min = 400000000, .max = 450000000 },142};143 144static const struct clk_pll_characteristics sam9g20_plla_characteristics = {145 .input = { .min = 2000000, .max = 32000000 },146 .num_output = ARRAY_SIZE(sam9g20_plla_outputs),147 .output = sam9g20_plla_outputs,148 .icpll = sam9g20_plla_icpll,149 .out = sam9g20_plla_out,150};151 152static u8 sam9g20_pllb_out[] = { 0 };153 154static u16 sam9g20_pllb_icpll[] = { 0 };155 156static const struct clk_range sam9g20_pllb_outputs[] = {157 { .min = 30000000, .max = 100000000 },158};159 160static const struct clk_pll_characteristics sam9g20_pllb_characteristics = {161 .input = { .min = 2000000, .max = 32000000 },162 .num_output = ARRAY_SIZE(sam9g20_pllb_outputs),163 .output = sam9g20_pllb_outputs,164 .icpll = sam9g20_pllb_icpll,165 .out = sam9g20_pllb_out,166};167 168static struct at91sam926x_data at91sam9g20_data = {169 .plla_layout = &at91sam9g45_pll_layout,170 .plla_characteristics = &sam9g20_plla_characteristics,171 .pllb_layout = &at91sam9g20_pllb_layout,172 .pllb_characteristics = &sam9g20_pllb_characteristics,173 .mck_characteristics = &sam9g20_mck_characteristics,174 .sck = at91sam9260_systemck,175 .num_sck = ARRAY_SIZE(at91sam9260_systemck),176 .pck = at91sam9260_periphck,177 .num_pck = ARRAY_SIZE(at91sam9260_periphck),178 .num_progck = 2,179 .has_slck = true,180};181 182static const struct clk_master_characteristics sam9261_mck_characteristics = {183 .output = { .min = 0, .max = 94000000 },184 .divisors = { 1, 2, 4, 0 },185};186 187static const struct clk_range sam9261_plla_outputs[] = {188 { .min = 80000000, .max = 200000000 },189 { .min = 190000000, .max = 240000000 },190};191 192static const struct clk_pll_characteristics sam9261_plla_characteristics = {193 .input = { .min = 1000000, .max = 32000000 },194 .num_output = ARRAY_SIZE(sam9261_plla_outputs),195 .output = sam9261_plla_outputs,196 .icpll = sam9260_plla_icpll,197 .out = sam9260_plla_out,198};199 200static u8 sam9261_pllb_out[] = { 1 };201 202static u16 sam9261_pllb_icpll[] = { 1 };203 204static const struct clk_range sam9261_pllb_outputs[] = {205 { .min = 70000000, .max = 130000000 },206};207 208static const struct clk_pll_characteristics sam9261_pllb_characteristics = {209 .input = { .min = 1000000, .max = 5000000 },210 .num_output = ARRAY_SIZE(sam9261_pllb_outputs),211 .output = sam9261_pllb_outputs,212 .icpll = sam9261_pllb_icpll,213 .out = sam9261_pllb_out,214};215 216static const struct sck at91sam9261_systemck[] = {217 { .n = "uhpck", .p = "usbck", .id = 6 },218 { .n = "udpck", .p = "usbck", .id = 7 },219 { .n = "pck0", .p = "prog0", .id = 8 },220 { .n = "pck1", .p = "prog1", .id = 9 },221 { .n = "pck2", .p = "prog2", .id = 10 },222 { .n = "pck3", .p = "prog3", .id = 11 },223 { .n = "hclk0", .p = "masterck_div", .id = 16 },224 { .n = "hclk1", .p = "masterck_div", .id = 17 },225};226 227static const struct pck at91sam9261_periphck[] = {228 { .n = "pioA_clk", .id = 2, },229 { .n = "pioB_clk", .id = 3, },230 { .n = "pioC_clk", .id = 4, },231 { .n = "usart0_clk", .id = 6, },232 { .n = "usart1_clk", .id = 7, },233 { .n = "usart2_clk", .id = 8, },234 { .n = "mci0_clk", .id = 9, },235 { .n = "udc_clk", .id = 10, },236 { .n = "twi0_clk", .id = 11, },237 { .n = "spi0_clk", .id = 12, },238 { .n = "spi1_clk", .id = 13, },239 { .n = "ssc0_clk", .id = 14, },240 { .n = "ssc1_clk", .id = 15, },241 { .n = "ssc2_clk", .id = 16, },242 { .n = "tc0_clk", .id = 17, },243 { .n = "tc1_clk", .id = 18, },244 { .n = "tc2_clk", .id = 19, },245 { .n = "ohci_clk", .id = 20, },246 { .n = "lcd_clk", .id = 21, },247};248 249static struct at91sam926x_data at91sam9261_data = {250 .plla_layout = &at91rm9200_pll_layout,251 .plla_characteristics = &sam9261_plla_characteristics,252 .pllb_layout = &at91rm9200_pll_layout,253 .pllb_characteristics = &sam9261_pllb_characteristics,254 .mck_characteristics = &sam9261_mck_characteristics,255 .sck = at91sam9261_systemck,256 .num_sck = ARRAY_SIZE(at91sam9261_systemck),257 .pck = at91sam9261_periphck,258 .num_pck = ARRAY_SIZE(at91sam9261_periphck),259 .num_progck = 4,260};261 262static const struct clk_master_characteristics sam9263_mck_characteristics = {263 .output = { .min = 0, .max = 120000000 },264 .divisors = { 1, 2, 4, 0 },265};266 267static const struct clk_range sam9263_pll_outputs[] = {268 { .min = 80000000, .max = 200000000 },269 { .min = 190000000, .max = 240000000 },270};271 272static const struct clk_pll_characteristics sam9263_pll_characteristics = {273 .input = { .min = 1000000, .max = 32000000 },274 .num_output = ARRAY_SIZE(sam9263_pll_outputs),275 .output = sam9263_pll_outputs,276 .icpll = sam9260_plla_icpll,277 .out = sam9260_plla_out,278};279 280static const struct sck at91sam9263_systemck[] = {281 { .n = "uhpck", .p = "usbck", .id = 6 },282 { .n = "udpck", .p = "usbck", .id = 7 },283 { .n = "pck0", .p = "prog0", .id = 8 },284 { .n = "pck1", .p = "prog1", .id = 9 },285 { .n = "pck2", .p = "prog2", .id = 10 },286 { .n = "pck3", .p = "prog3", .id = 11 },287};288 289static const struct pck at91sam9263_periphck[] = {290 { .n = "pioA_clk", .id = 2, },291 { .n = "pioB_clk", .id = 3, },292 { .n = "pioCDE_clk", .id = 4, },293 { .n = "usart0_clk", .id = 7, },294 { .n = "usart1_clk", .id = 8, },295 { .n = "usart2_clk", .id = 9, },296 { .n = "mci0_clk", .id = 10, },297 { .n = "mci1_clk", .id = 11, },298 { .n = "can_clk", .id = 12, },299 { .n = "twi0_clk", .id = 13, },300 { .n = "spi0_clk", .id = 14, },301 { .n = "spi1_clk", .id = 15, },302 { .n = "ssc0_clk", .id = 16, },303 { .n = "ssc1_clk", .id = 17, },304 { .n = "ac97_clk", .id = 18, },305 { .n = "tcb_clk", .id = 19, },306 { .n = "pwm_clk", .id = 20, },307 { .n = "macb0_clk", .id = 21, },308 { .n = "g2de_clk", .id = 23, },309 { .n = "udc_clk", .id = 24, },310 { .n = "isi_clk", .id = 25, },311 { .n = "lcd_clk", .id = 26, },312 { .n = "dma_clk", .id = 27, },313 { .n = "ohci_clk", .id = 29, },314};315 316static struct at91sam926x_data at91sam9263_data = {317 .plla_layout = &at91rm9200_pll_layout,318 .plla_characteristics = &sam9263_pll_characteristics,319 .pllb_layout = &at91rm9200_pll_layout,320 .pllb_characteristics = &sam9263_pll_characteristics,321 .mck_characteristics = &sam9263_mck_characteristics,322 .sck = at91sam9263_systemck,323 .num_sck = ARRAY_SIZE(at91sam9263_systemck),324 .pck = at91sam9263_periphck,325 .num_pck = ARRAY_SIZE(at91sam9263_periphck),326 .num_progck = 4,327};328 329static void __init at91sam926x_pmc_setup(struct device_node *np,330 struct at91sam926x_data *data)331{332 const char *slowxtal_name, *mainxtal_name;333 struct pmc_data *at91sam9260_pmc;334 u32 usb_div[] = { 1, 2, 4, 0 };335 const char *parent_names[6];336 const char *slck_name;337 struct regmap *regmap;338 struct clk_hw *hw;339 int i;340 bool bypass;341 342 i = of_property_match_string(np, "clock-names", "slow_xtal");343 if (i < 0)344 return;345 346 slowxtal_name = of_clk_get_parent_name(np, i);347 348 i = of_property_match_string(np, "clock-names", "main_xtal");349 if (i < 0)350 return;351 mainxtal_name = of_clk_get_parent_name(np, i);352 353 regmap = device_node_to_regmap(np);354 if (IS_ERR(regmap))355 return;356 357 at91sam9260_pmc = pmc_data_allocate(PMC_PLLBCK + 1,358 ndck(data->sck, data->num_sck),359 ndck(data->pck, data->num_pck),360 0, data->num_progck);361 if (!at91sam9260_pmc)362 return;363 364 bypass = of_property_read_bool(np, "atmel,osc-bypass");365 366 hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name, NULL,367 bypass);368 if (IS_ERR(hw))369 goto err_free;370 371 hw = at91_clk_register_rm9200_main(regmap, "mainck", "main_osc", NULL);372 if (IS_ERR(hw))373 goto err_free;374 375 at91sam9260_pmc->chws[PMC_MAIN] = hw;376 377 if (data->has_slck) {378 hw = clk_hw_register_fixed_rate_with_accuracy(NULL,379 "slow_rc_osc",380 NULL, 0, 32768,381 50000000);382 if (IS_ERR(hw))383 goto err_free;384 385 parent_names[0] = "slow_rc_osc";386 parent_names[1] = "slow_xtal";387 hw = at91_clk_register_sam9260_slow(regmap, "slck",388 parent_names, 2);389 if (IS_ERR(hw))390 goto err_free;391 392 at91sam9260_pmc->chws[PMC_SLOW] = hw;393 slck_name = "slck";394 } else {395 slck_name = slowxtal_name;396 }397 398 hw = at91_clk_register_pll(regmap, "pllack", "mainck", 0,399 data->plla_layout,400 data->plla_characteristics);401 if (IS_ERR(hw))402 goto err_free;403 404 at91sam9260_pmc->chws[PMC_PLLACK] = hw;405 406 hw = at91_clk_register_pll(regmap, "pllbck", "mainck", 1,407 data->pllb_layout,408 data->pllb_characteristics);409 if (IS_ERR(hw))410 goto err_free;411 412 at91sam9260_pmc->chws[PMC_PLLBCK] = hw;413 414 parent_names[0] = slck_name;415 parent_names[1] = "mainck";416 parent_names[2] = "pllack";417 parent_names[3] = "pllbck";418 hw = at91_clk_register_master_pres(regmap, "masterck_pres", 4,419 parent_names, NULL,420 &at91rm9200_master_layout,421 data->mck_characteristics,422 &at91sam9260_mck_lock);423 if (IS_ERR(hw))424 goto err_free;425 426 hw = at91_clk_register_master_div(regmap, "masterck_div",427 "masterck_pres", NULL,428 &at91rm9200_master_layout,429 data->mck_characteristics,430 &at91sam9260_mck_lock,431 CLK_SET_RATE_GATE, 0);432 if (IS_ERR(hw))433 goto err_free;434 435 at91sam9260_pmc->chws[PMC_MCK] = hw;436 437 hw = at91rm9200_clk_register_usb(regmap, "usbck", "pllbck", usb_div);438 if (IS_ERR(hw))439 goto err_free;440 441 parent_names[0] = slck_name;442 parent_names[1] = "mainck";443 parent_names[2] = "pllack";444 parent_names[3] = "pllbck";445 for (i = 0; i < data->num_progck; i++) {446 char name[6];447 448 snprintf(name, sizeof(name), "prog%d", i);449 450 hw = at91_clk_register_programmable(regmap, name,451 parent_names, NULL, 4, i,452 &at91rm9200_programmable_layout,453 NULL);454 if (IS_ERR(hw))455 goto err_free;456 457 at91sam9260_pmc->pchws[i] = hw;458 }459 460 for (i = 0; i < data->num_sck; i++) {461 hw = at91_clk_register_system(regmap, data->sck[i].n,462 data->sck[i].p, NULL,463 data->sck[i].id, 0);464 if (IS_ERR(hw))465 goto err_free;466 467 at91sam9260_pmc->shws[data->sck[i].id] = hw;468 }469 470 for (i = 0; i < data->num_pck; i++) {471 hw = at91_clk_register_peripheral(regmap,472 data->pck[i].n,473 "masterck_div", NULL,474 data->pck[i].id);475 if (IS_ERR(hw))476 goto err_free;477 478 at91sam9260_pmc->phws[data->pck[i].id] = hw;479 }480 481 of_clk_add_hw_provider(np, of_clk_hw_pmc_get, at91sam9260_pmc);482 483 return;484 485err_free:486 kfree(at91sam9260_pmc);487}488 489static void __init at91sam9260_pmc_setup(struct device_node *np)490{491 at91sam926x_pmc_setup(np, &at91sam9260_data);492}493 494CLK_OF_DECLARE(at91sam9260_pmc, "atmel,at91sam9260-pmc", at91sam9260_pmc_setup);495 496static void __init at91sam9261_pmc_setup(struct device_node *np)497{498 at91sam926x_pmc_setup(np, &at91sam9261_data);499}500 501CLK_OF_DECLARE(at91sam9261_pmc, "atmel,at91sam9261-pmc", at91sam9261_pmc_setup);502 503static void __init at91sam9263_pmc_setup(struct device_node *np)504{505 at91sam926x_pmc_setup(np, &at91sam9263_data);506}507 508CLK_OF_DECLARE(at91sam9263_pmc, "atmel,at91sam9263-pmc", at91sam9263_pmc_setup);509 510static void __init at91sam9g20_pmc_setup(struct device_node *np)511{512 at91sam926x_pmc_setup(np, &at91sam9g20_data);513}514 515CLK_OF_DECLARE(at91sam9g20_pmc, "atmel,at91sam9g20-pmc", at91sam9g20_pmc_setup);516