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1/* SPDX-License-Identifier: GPL-2.0-or-later */2/*3 * drivers/clk/at91/pmc.h4 *5 * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>6 */7 8#ifndef __PMC_H_9#define __PMC_H_10 11#include <linux/io.h>12#include <linux/irqdomain.h>13#include <linux/regmap.h>14#include <linux/spinlock.h>15 16#include <dt-bindings/clock/at91.h>17 18extern spinlock_t pmc_pcr_lock;19 20struct pmc_data {21 unsigned int ncore;22 struct clk_hw **chws;23 unsigned int nsystem;24 struct clk_hw **shws;25 unsigned int nperiph;26 struct clk_hw **phws;27 unsigned int ngck;28 struct clk_hw **ghws;29 unsigned int npck;30 struct clk_hw **pchws;31 32 struct clk_hw *hwtable[];33};34 35struct clk_range {36 unsigned long min;37 unsigned long max;38};39 40#define CLK_RANGE(MIN, MAX) {.min = MIN, .max = MAX,}41 42struct clk_master_layout {43 u32 offset;44 u32 mask;45 u8 pres_shift;46};47 48extern const struct clk_master_layout at91rm9200_master_layout;49extern const struct clk_master_layout at91sam9x5_master_layout;50 51struct clk_master_characteristics {52 struct clk_range output;53 u32 divisors[5];54 u8 have_div3_pres;55};56 57struct clk_pll_layout {58 u32 pllr_mask;59 u32 mul_mask;60 u32 frac_mask;61 u32 div_mask;62 u32 endiv_mask;63 u8 mul_shift;64 u8 frac_shift;65 u8 div_shift;66 u8 endiv_shift;67 u8 div2;68};69 70extern const struct clk_pll_layout at91rm9200_pll_layout;71extern const struct clk_pll_layout at91sam9g45_pll_layout;72extern const struct clk_pll_layout at91sam9g20_pllb_layout;73extern const struct clk_pll_layout sama5d3_pll_layout;74 75struct clk_pll_characteristics {76 struct clk_range input;77 int num_output;78 const struct clk_range *output;79 const struct clk_range *core_output;80 u16 *icpll;81 u8 *out;82 u8 upll : 1;83};84 85struct clk_programmable_layout {86 u8 pres_mask;87 u8 pres_shift;88 u8 css_mask;89 u8 have_slck_mck;90 u8 is_pres_direct;91};92 93extern const struct clk_programmable_layout at91rm9200_programmable_layout;94extern const struct clk_programmable_layout at91sam9g45_programmable_layout;95extern const struct clk_programmable_layout at91sam9x5_programmable_layout;96 97struct clk_pcr_layout {98 u32 offset;99 u32 cmd;100 u32 div_mask;101 u32 gckcss_mask;102 u32 pid_mask;103};104 105/**106 * struct at91_clk_pms - Power management state for AT91 clock107 * @rate: clock rate108 * @parent_rate: clock parent rate109 * @status: clock status (enabled or disabled)110 * @parent: clock parent index111 */112struct at91_clk_pms {113 unsigned long rate;114 unsigned long parent_rate;115 unsigned int status;116 unsigned int parent;117};118 119#define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1))120#define field_prep(_mask, _val) (((_val) << (ffs(_mask) - 1)) & (_mask))121 122#define ndck(a, s) (a[s - 1].id + 1)123#define nck(a) (a[ARRAY_SIZE(a) - 1].id + 1)124 125#define PMC_INIT_TABLE(_table, _count) \126 do { \127 u8 _i; \128 for (_i = 0; _i < (_count); _i++) \129 (_table)[_i] = _i; \130 } while (0)131 132#define PMC_FILL_TABLE(_to, _from, _count) \133 do { \134 u8 _i; \135 for (_i = 0; _i < (_count); _i++) { \136 (_to)[_i] = (_from)[_i]; \137 } \138 } while (0)139 140struct pmc_data *pmc_data_allocate(unsigned int ncore, unsigned int nsystem,141 unsigned int nperiph, unsigned int ngck,142 unsigned int npck);143 144int of_at91_get_clk_range(struct device_node *np, const char *propname,145 struct clk_range *range);146 147struct clk_hw *of_clk_hw_pmc_get(struct of_phandle_args *clkspec, void *data);148 149struct clk_hw * __init150at91_clk_register_audio_pll_frac(struct regmap *regmap, const char *name,151 const char *parent_name);152 153struct clk_hw * __init154at91_clk_register_audio_pll_pad(struct regmap *regmap, const char *name,155 const char *parent_name);156 157struct clk_hw * __init158at91_clk_register_audio_pll_pmc(struct regmap *regmap, const char *name,159 const char *parent_name);160 161struct clk_hw * __init162at91_clk_register_generated(struct regmap *regmap, spinlock_t *lock,163 const struct clk_pcr_layout *layout,164 const char *name, const char **parent_names,165 struct clk_hw **parent_hws, u32 *mux_table,166 u8 num_parents, u8 id,167 const struct clk_range *range, int chg_pid);168 169struct clk_hw * __init170at91_clk_register_h32mx(struct regmap *regmap, const char *name,171 const char *parent_name);172 173struct clk_hw * __init174at91_clk_i2s_mux_register(struct regmap *regmap, const char *name,175 const char * const *parent_names,176 unsigned int num_parents, u8 bus_id);177 178struct clk_hw * __init179at91_clk_register_main_rc_osc(struct regmap *regmap, const char *name,180 u32 frequency, u32 accuracy);181struct clk_hw * __init182at91_clk_register_main_osc(struct regmap *regmap, const char *name,183 const char *parent_name,184 struct clk_parent_data *parent_data, bool bypass);185struct clk_hw * __init186at91_clk_register_rm9200_main(struct regmap *regmap,187 const char *name,188 const char *parent_name,189 struct clk_hw *parent_hw);190struct clk_hw * __init191at91_clk_register_sam9x5_main(struct regmap *regmap, const char *name,192 const char **parent_names,193 struct clk_hw **parent_hws, int num_parents);194 195struct clk_hw * __init196at91_clk_register_master_pres(struct regmap *regmap, const char *name,197 int num_parents, const char **parent_names,198 struct clk_hw **parent_hws,199 const struct clk_master_layout *layout,200 const struct clk_master_characteristics *characteristics,201 spinlock_t *lock);202 203struct clk_hw * __init204at91_clk_register_master_div(struct regmap *regmap, const char *name,205 const char *parent_names, struct clk_hw *parent_hw,206 const struct clk_master_layout *layout,207 const struct clk_master_characteristics *characteristics,208 spinlock_t *lock, u32 flags, u32 safe_div);209 210struct clk_hw * __init211at91_clk_sama7g5_register_master(struct regmap *regmap,212 const char *name, int num_parents,213 const char **parent_names,214 struct clk_hw **parent_hws, u32 *mux_table,215 spinlock_t *lock, u8 id, bool critical,216 int chg_pid);217 218struct clk_hw * __init219at91_clk_register_peripheral(struct regmap *regmap, const char *name,220 const char *parent_name, struct clk_hw *parent_hw,221 u32 id);222struct clk_hw * __init223at91_clk_register_sam9x5_peripheral(struct regmap *regmap, spinlock_t *lock,224 const struct clk_pcr_layout *layout,225 const char *name, const char *parent_name,226 struct clk_hw *parent_hw,227 u32 id, const struct clk_range *range,228 int chg_pid, unsigned long flags);229 230struct clk_hw * __init231at91_clk_register_pll(struct regmap *regmap, const char *name,232 const char *parent_name, u8 id,233 const struct clk_pll_layout *layout,234 const struct clk_pll_characteristics *characteristics);235struct clk_hw * __init236at91_clk_register_plldiv(struct regmap *regmap, const char *name,237 const char *parent_name);238 239struct clk_hw * __init240sam9x60_clk_register_div_pll(struct regmap *regmap, spinlock_t *lock,241 const char *name, const char *parent_name,242 struct clk_hw *parent_hw, u8 id,243 const struct clk_pll_characteristics *characteristics,244 const struct clk_pll_layout *layout, u32 flags,245 u32 safe_div);246 247struct clk_hw * __init248sam9x60_clk_register_frac_pll(struct regmap *regmap, spinlock_t *lock,249 const char *name, const char *parent_name,250 struct clk_hw *parent_hw, u8 id,251 const struct clk_pll_characteristics *characteristics,252 const struct clk_pll_layout *layout, u32 flags);253 254struct clk_hw * __init255at91_clk_register_programmable(struct regmap *regmap, const char *name,256 const char **parent_names, struct clk_hw **parent_hws,257 u8 num_parents, u8 id,258 const struct clk_programmable_layout *layout,259 u32 *mux_table);260 261struct clk_hw * __init262at91_clk_register_sam9260_slow(struct regmap *regmap,263 const char *name,264 const char **parent_names,265 int num_parents);266 267struct clk_hw * __init268at91sam9x5_clk_register_smd(struct regmap *regmap, const char *name,269 const char **parent_names, u8 num_parents);270 271struct clk_hw * __init272at91_clk_register_system(struct regmap *regmap, const char *name,273 const char *parent_name, struct clk_hw *parent_hw,274 u8 id, unsigned long flags);275 276struct clk_hw * __init277at91sam9x5_clk_register_usb(struct regmap *regmap, const char *name,278 const char **parent_names, u8 num_parents);279struct clk_hw * __init280at91sam9n12_clk_register_usb(struct regmap *regmap, const char *name,281 const char *parent_name);282struct clk_hw * __init283sam9x60_clk_register_usb(struct regmap *regmap, const char *name,284 const char **parent_names, u8 num_parents);285struct clk_hw * __init286at91rm9200_clk_register_usb(struct regmap *regmap, const char *name,287 const char *parent_name, const u32 *divisors);288 289struct clk_hw * __init290at91_clk_register_utmi(struct regmap *regmap_pmc, struct regmap *regmap_sfr,291 const char *name, const char *parent_name,292 struct clk_hw *parent_hw);293 294struct clk_hw * __init295at91_clk_sama7g5_register_utmi(struct regmap *regmap, const char *name,296 const char *parent_name, struct clk_hw *parent_hw);297 298#endif /* __PMC_H_ */299