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1// SPDX-License-Identifier: GPL-2.02#include <linux/clk-provider.h>3#include <linux/mfd/syscon.h>4#include <linux/slab.h>5 6#include <dt-bindings/clock/at91.h>7 8#include "pmc.h"9 10static DEFINE_SPINLOCK(pmc_pll_lock);11static DEFINE_SPINLOCK(mck_lock);12 13static const struct clk_master_characteristics mck_characteristics = {14 .output = { .min = 140000000, .max = 200000000 },15 .divisors = { 1, 2, 4, 3 },16 .have_div3_pres = 1,17};18 19static const struct clk_master_layout sam9x60_master_layout = {20 .mask = 0x373,21 .pres_shift = 4,22 .offset = 0x28,23};24 25static const struct clk_range plla_outputs[] = {26 { .min = 2343750, .max = 1200000000 },27};28 29/* Fractional PLL core output range. */30static const struct clk_range core_outputs[] = {31 { .min = 600000000, .max = 1200000000 },32};33 34static const struct clk_pll_characteristics plla_characteristics = {35 .input = { .min = 12000000, .max = 48000000 },36 .num_output = ARRAY_SIZE(plla_outputs),37 .output = plla_outputs,38 .core_output = core_outputs,39};40 41static const struct clk_range upll_outputs[] = {42 { .min = 300000000, .max = 500000000 },43};44 45static const struct clk_pll_characteristics upll_characteristics = {46 .input = { .min = 12000000, .max = 48000000 },47 .num_output = ARRAY_SIZE(upll_outputs),48 .output = upll_outputs,49 .core_output = core_outputs,50 .upll = true,51};52 53static const struct clk_pll_layout pll_frac_layout = {54 .mul_mask = GENMASK(31, 24),55 .frac_mask = GENMASK(21, 0),56 .mul_shift = 24,57 .frac_shift = 0,58};59 60static const struct clk_pll_layout pll_div_layout = {61 .div_mask = GENMASK(7, 0),62 .endiv_mask = BIT(29),63 .div_shift = 0,64 .endiv_shift = 29,65};66 67static const struct clk_programmable_layout sam9x60_programmable_layout = {68 .pres_mask = 0xff,69 .pres_shift = 8,70 .css_mask = 0x1f,71 .have_slck_mck = 0,72 .is_pres_direct = 1,73};74 75static const struct clk_pcr_layout sam9x60_pcr_layout = {76 .offset = 0x88,77 .cmd = BIT(31),78 .gckcss_mask = GENMASK(12, 8),79 .pid_mask = GENMASK(6, 0),80};81 82static const struct {83 char *n;84 char *p;85 unsigned long flags;86 u8 id;87} sam9x60_systemck[] = {88 /*89 * ddrck feeds DDR controller and is enabled by bootloader thus we need90 * to keep it enabled in case there is no Linux consumer for it.91 */92 { .n = "ddrck", .p = "masterck_div", .id = 2, .flags = CLK_IS_CRITICAL },93 { .n = "uhpck", .p = "usbck", .id = 6 },94 { .n = "pck0", .p = "prog0", .id = 8 },95 { .n = "pck1", .p = "prog1", .id = 9 },96 { .n = "qspick", .p = "masterck_div", .id = 19 },97};98 99static const struct {100 char *n;101 unsigned long flags;102 u8 id;103} sam9x60_periphck[] = {104 { .n = "pioA_clk", .id = 2, },105 { .n = "pioB_clk", .id = 3, },106 { .n = "pioC_clk", .id = 4, },107 { .n = "flex0_clk", .id = 5, },108 { .n = "flex1_clk", .id = 6, },109 { .n = "flex2_clk", .id = 7, },110 { .n = "flex3_clk", .id = 8, },111 { .n = "flex6_clk", .id = 9, },112 { .n = "flex7_clk", .id = 10, },113 { .n = "flex8_clk", .id = 11, },114 { .n = "sdmmc0_clk", .id = 12, },115 { .n = "flex4_clk", .id = 13, },116 { .n = "flex5_clk", .id = 14, },117 { .n = "flex9_clk", .id = 15, },118 { .n = "flex10_clk", .id = 16, },119 { .n = "tcb0_clk", .id = 17, },120 { .n = "pwm_clk", .id = 18, },121 { .n = "adc_clk", .id = 19, },122 { .n = "dma0_clk", .id = 20, },123 { .n = "matrix_clk", .id = 21, },124 { .n = "uhphs_clk", .id = 22, },125 { .n = "udphs_clk", .id = 23, },126 { .n = "macb0_clk", .id = 24, },127 { .n = "lcd_clk", .id = 25, },128 { .n = "sdmmc1_clk", .id = 26, },129 { .n = "macb1_clk", .id = 27, },130 { .n = "ssc_clk", .id = 28, },131 { .n = "can0_clk", .id = 29, },132 { .n = "can1_clk", .id = 30, },133 { .n = "flex11_clk", .id = 32, },134 { .n = "flex12_clk", .id = 33, },135 { .n = "i2s_clk", .id = 34, },136 { .n = "qspi_clk", .id = 35, },137 { .n = "gfx2d_clk", .id = 36, },138 { .n = "pit64b_clk", .id = 37, },139 { .n = "trng_clk", .id = 38, },140 { .n = "aes_clk", .id = 39, },141 { .n = "tdes_clk", .id = 40, },142 { .n = "sha_clk", .id = 41, },143 { .n = "classd_clk", .id = 42, },144 { .n = "isi_clk", .id = 43, },145 { .n = "pioD_clk", .id = 44, },146 { .n = "tcb1_clk", .id = 45, },147 { .n = "dbgu_clk", .id = 47, },148 /*149 * mpddr_clk feeds DDR controller and is enabled by bootloader thus we150 * need to keep it enabled in case there is no Linux consumer for it.151 */152 { .n = "mpddr_clk", .id = 49, .flags = CLK_IS_CRITICAL },153};154 155static const struct {156 char *n;157 u8 id;158 struct clk_range r;159} sam9x60_gck[] = {160 { .n = "flex0_gclk", .id = 5, },161 { .n = "flex1_gclk", .id = 6, },162 { .n = "flex2_gclk", .id = 7, },163 { .n = "flex3_gclk", .id = 8, },164 { .n = "flex6_gclk", .id = 9, },165 { .n = "flex7_gclk", .id = 10, },166 { .n = "flex8_gclk", .id = 11, },167 { .n = "sdmmc0_gclk", .id = 12, .r = { .min = 0, .max = 105000000 }, },168 { .n = "flex4_gclk", .id = 13, },169 { .n = "flex5_gclk", .id = 14, },170 { .n = "flex9_gclk", .id = 15, },171 { .n = "flex10_gclk", .id = 16, },172 { .n = "tcb0_gclk", .id = 17, },173 { .n = "adc_gclk", .id = 19, },174 { .n = "lcd_gclk", .id = 25, .r = { .min = 0, .max = 140000000 }, },175 { .n = "sdmmc1_gclk", .id = 26, .r = { .min = 0, .max = 105000000 }, },176 { .n = "flex11_gclk", .id = 32, },177 { .n = "flex12_gclk", .id = 33, },178 { .n = "i2s_gclk", .id = 34, .r = { .min = 0, .max = 105000000 }, },179 { .n = "pit64b_gclk", .id = 37, },180 { .n = "classd_gclk", .id = 42, .r = { .min = 0, .max = 100000000 }, },181 { .n = "tcb1_gclk", .id = 45, },182 { .n = "dbgu_gclk", .id = 47, },183};184 185static void __init sam9x60_pmc_setup(struct device_node *np)186{187 struct clk_range range = CLK_RANGE(0, 0);188 const char *td_slck_name, *md_slck_name, *mainxtal_name;189 struct pmc_data *sam9x60_pmc;190 const char *parent_names[6];191 struct clk_hw *main_osc_hw;192 struct regmap *regmap;193 struct clk_hw *hw;194 int i;195 196 i = of_property_match_string(np, "clock-names", "td_slck");197 if (i < 0)198 return;199 200 td_slck_name = of_clk_get_parent_name(np, i);201 202 i = of_property_match_string(np, "clock-names", "md_slck");203 if (i < 0)204 return;205 206 md_slck_name = of_clk_get_parent_name(np, i);207 208 i = of_property_match_string(np, "clock-names", "main_xtal");209 if (i < 0)210 return;211 mainxtal_name = of_clk_get_parent_name(np, i);212 213 regmap = device_node_to_regmap(np);214 if (IS_ERR(regmap))215 return;216 217 sam9x60_pmc = pmc_data_allocate(PMC_PLLACK + 1,218 nck(sam9x60_systemck),219 nck(sam9x60_periphck),220 nck(sam9x60_gck), 8);221 if (!sam9x60_pmc)222 return;223 224 hw = at91_clk_register_main_rc_osc(regmap, "main_rc_osc", 12000000,225 50000000);226 if (IS_ERR(hw))227 goto err_free;228 229 hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name, NULL, 0);230 if (IS_ERR(hw))231 goto err_free;232 main_osc_hw = hw;233 234 parent_names[0] = "main_rc_osc";235 parent_names[1] = "main_osc";236 hw = at91_clk_register_sam9x5_main(regmap, "mainck", parent_names, NULL, 2);237 if (IS_ERR(hw))238 goto err_free;239 240 sam9x60_pmc->chws[PMC_MAIN] = hw;241 242 hw = sam9x60_clk_register_frac_pll(regmap, &pmc_pll_lock, "pllack_fracck",243 "mainck", sam9x60_pmc->chws[PMC_MAIN],244 0, &plla_characteristics,245 &pll_frac_layout,246 /*247 * This feeds pllack_divck which248 * feeds CPU. It should not be249 * disabled.250 */251 CLK_IS_CRITICAL | CLK_SET_RATE_GATE);252 if (IS_ERR(hw))253 goto err_free;254 255 hw = sam9x60_clk_register_div_pll(regmap, &pmc_pll_lock, "pllack_divck",256 "pllack_fracck", NULL, 0, &plla_characteristics,257 &pll_div_layout,258 /*259 * This feeds CPU. It should not260 * be disabled.261 */262 CLK_IS_CRITICAL | CLK_SET_RATE_GATE, 0);263 if (IS_ERR(hw))264 goto err_free;265 266 sam9x60_pmc->chws[PMC_PLLACK] = hw;267 268 hw = sam9x60_clk_register_frac_pll(regmap, &pmc_pll_lock, "upllck_fracck",269 "main_osc", main_osc_hw, 1,270 &upll_characteristics,271 &pll_frac_layout, CLK_SET_RATE_GATE);272 if (IS_ERR(hw))273 goto err_free;274 275 hw = sam9x60_clk_register_div_pll(regmap, &pmc_pll_lock, "upllck_divck",276 "upllck_fracck", NULL, 1, &upll_characteristics,277 &pll_div_layout,278 CLK_SET_RATE_GATE |279 CLK_SET_PARENT_GATE |280 CLK_SET_RATE_PARENT, 0);281 if (IS_ERR(hw))282 goto err_free;283 284 sam9x60_pmc->chws[PMC_UTMI] = hw;285 286 parent_names[0] = md_slck_name;287 parent_names[1] = "mainck";288 parent_names[2] = "pllack_divck";289 hw = at91_clk_register_master_pres(regmap, "masterck_pres", 3,290 parent_names, NULL, &sam9x60_master_layout,291 &mck_characteristics, &mck_lock);292 if (IS_ERR(hw))293 goto err_free;294 295 hw = at91_clk_register_master_div(regmap, "masterck_div",296 "masterck_pres", NULL, &sam9x60_master_layout,297 &mck_characteristics, &mck_lock,298 CLK_SET_RATE_GATE, 0);299 if (IS_ERR(hw))300 goto err_free;301 302 sam9x60_pmc->chws[PMC_MCK] = hw;303 304 parent_names[0] = "pllack_divck";305 parent_names[1] = "upllck_divck";306 parent_names[2] = "main_osc";307 hw = sam9x60_clk_register_usb(regmap, "usbck", parent_names, 3);308 if (IS_ERR(hw))309 goto err_free;310 311 parent_names[0] = md_slck_name;312 parent_names[1] = td_slck_name;313 parent_names[2] = "mainck";314 parent_names[3] = "masterck_div";315 parent_names[4] = "pllack_divck";316 parent_names[5] = "upllck_divck";317 for (i = 0; i < 2; i++) {318 char name[6];319 320 snprintf(name, sizeof(name), "prog%d", i);321 322 hw = at91_clk_register_programmable(regmap, name,323 parent_names, NULL, 6, i,324 &sam9x60_programmable_layout,325 NULL);326 if (IS_ERR(hw))327 goto err_free;328 329 sam9x60_pmc->pchws[i] = hw;330 }331 332 for (i = 0; i < ARRAY_SIZE(sam9x60_systemck); i++) {333 hw = at91_clk_register_system(regmap, sam9x60_systemck[i].n,334 sam9x60_systemck[i].p, NULL,335 sam9x60_systemck[i].id,336 sam9x60_systemck[i].flags);337 if (IS_ERR(hw))338 goto err_free;339 340 sam9x60_pmc->shws[sam9x60_systemck[i].id] = hw;341 }342 343 for (i = 0; i < ARRAY_SIZE(sam9x60_periphck); i++) {344 hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock,345 &sam9x60_pcr_layout,346 sam9x60_periphck[i].n,347 "masterck_div", NULL,348 sam9x60_periphck[i].id,349 &range, INT_MIN,350 sam9x60_periphck[i].flags);351 if (IS_ERR(hw))352 goto err_free;353 354 sam9x60_pmc->phws[sam9x60_periphck[i].id] = hw;355 }356 357 for (i = 0; i < ARRAY_SIZE(sam9x60_gck); i++) {358 hw = at91_clk_register_generated(regmap, &pmc_pcr_lock,359 &sam9x60_pcr_layout,360 sam9x60_gck[i].n,361 parent_names, NULL, NULL, 6,362 sam9x60_gck[i].id,363 &sam9x60_gck[i].r, INT_MIN);364 if (IS_ERR(hw))365 goto err_free;366 367 sam9x60_pmc->ghws[sam9x60_gck[i].id] = hw;368 }369 370 of_clk_add_hw_provider(np, of_clk_hw_pmc_get, sam9x60_pmc);371 372 return;373 374err_free:375 kfree(sam9x60_pmc);376}377/* Some clks are used for a clocksource */378CLK_OF_DECLARE(sam9x60_pmc, "microchip,sam9x60-pmc", sam9x60_pmc_setup);379