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1// SPDX-License-Identifier: GPL-2.02#include <linux/clk-provider.h>3#include <linux/mfd/syscon.h>4#include <linux/slab.h>5 6#include <dt-bindings/clock/at91.h>7 8#include "pmc.h"9 10static DEFINE_SPINLOCK(mck_lock);11 12static const struct clk_master_characteristics mck_characteristics = {13 .output = { .min = 125000000, .max = 200000000 },14 .divisors = { 1, 2, 4, 3 },15};16 17static u8 plla_out[] = { 0 };18 19static u16 plla_icpll[] = { 0 };20 21static const struct clk_range plla_outputs[] = {22 { .min = 600000000, .max = 1200000000 },23};24 25static const struct clk_pll_characteristics plla_characteristics = {26 .input = { .min = 12000000, .max = 12000000 },27 .num_output = ARRAY_SIZE(plla_outputs),28 .output = plla_outputs,29 .icpll = plla_icpll,30 .out = plla_out,31};32 33static const struct clk_pcr_layout sama5d4_pcr_layout = {34 .offset = 0x10c,35 .cmd = BIT(12),36 .pid_mask = GENMASK(6, 0),37};38 39static const struct {40 char *n;41 char *p;42 unsigned long flags;43 u8 id;44} sama5d4_systemck[] = {45 /*46 * ddrck feeds DDR controller and is enabled by bootloader thus we need47 * to keep it enabled in case there is no Linux consumer for it.48 */49 { .n = "ddrck", .p = "masterck_div", .id = 2, .flags = CLK_IS_CRITICAL },50 { .n = "lcdck", .p = "masterck_div", .id = 3 },51 { .n = "smdck", .p = "smdclk", .id = 4 },52 { .n = "uhpck", .p = "usbck", .id = 6 },53 { .n = "udpck", .p = "usbck", .id = 7 },54 { .n = "pck0", .p = "prog0", .id = 8 },55 { .n = "pck1", .p = "prog1", .id = 9 },56 { .n = "pck2", .p = "prog2", .id = 10 },57};58 59static const struct {60 char *n;61 u8 id;62} sama5d4_periph32ck[] = {63 { .n = "pioD_clk", .id = 5 },64 { .n = "usart0_clk", .id = 6 },65 { .n = "usart1_clk", .id = 7 },66 { .n = "icm_clk", .id = 9 },67 { .n = "aes_clk", .id = 12 },68 { .n = "tdes_clk", .id = 14 },69 { .n = "sha_clk", .id = 15 },70 { .n = "matrix1_clk", .id = 17 },71 { .n = "hsmc_clk", .id = 22 },72 { .n = "pioA_clk", .id = 23 },73 { .n = "pioB_clk", .id = 24 },74 { .n = "pioC_clk", .id = 25 },75 { .n = "pioE_clk", .id = 26 },76 { .n = "uart0_clk", .id = 27 },77 { .n = "uart1_clk", .id = 28 },78 { .n = "usart2_clk", .id = 29 },79 { .n = "usart3_clk", .id = 30 },80 { .n = "usart4_clk", .id = 31 },81 { .n = "twi0_clk", .id = 32 },82 { .n = "twi1_clk", .id = 33 },83 { .n = "twi2_clk", .id = 34 },84 { .n = "mci0_clk", .id = 35 },85 { .n = "mci1_clk", .id = 36 },86 { .n = "spi0_clk", .id = 37 },87 { .n = "spi1_clk", .id = 38 },88 { .n = "spi2_clk", .id = 39 },89 { .n = "tcb0_clk", .id = 40 },90 { .n = "tcb1_clk", .id = 41 },91 { .n = "tcb2_clk", .id = 42 },92 { .n = "pwm_clk", .id = 43 },93 { .n = "adc_clk", .id = 44 },94 { .n = "dbgu_clk", .id = 45 },95 { .n = "uhphs_clk", .id = 46 },96 { .n = "udphs_clk", .id = 47 },97 { .n = "ssc0_clk", .id = 48 },98 { .n = "ssc1_clk", .id = 49 },99 { .n = "trng_clk", .id = 53 },100 { .n = "macb0_clk", .id = 54 },101 { .n = "macb1_clk", .id = 55 },102 { .n = "fuse_clk", .id = 57 },103 { .n = "securam_clk", .id = 59 },104 { .n = "smd_clk", .id = 61 },105 { .n = "twi3_clk", .id = 62 },106 { .n = "catb_clk", .id = 63 },107};108 109static const struct {110 char *n;111 unsigned long flags;112 u8 id;113} sama5d4_periphck[] = {114 { .n = "dma0_clk", .id = 8 },115 { .n = "cpkcc_clk", .id = 10 },116 { .n = "aesb_clk", .id = 13 },117 /*118 * mpddr_clk feeds DDR controller and is enabled by bootloader thus we119 * need to keep it enabled in case there is no Linux consumer for it.120 */121 { .n = "mpddr_clk", .id = 16, .flags = CLK_IS_CRITICAL },122 { .n = "matrix0_clk", .id = 18 },123 { .n = "vdec_clk", .id = 19 },124 { .n = "dma1_clk", .id = 50 },125 { .n = "lcdc_clk", .id = 51 },126 { .n = "isi_clk", .id = 52 },127};128 129static void __init sama5d4_pmc_setup(struct device_node *np)130{131 struct clk_range range = CLK_RANGE(0, 0);132 const char *slck_name, *mainxtal_name;133 struct pmc_data *sama5d4_pmc;134 const char *parent_names[5];135 struct regmap *regmap;136 struct clk_hw *hw;137 int i;138 bool bypass;139 140 i = of_property_match_string(np, "clock-names", "slow_clk");141 if (i < 0)142 return;143 144 slck_name = of_clk_get_parent_name(np, i);145 146 i = of_property_match_string(np, "clock-names", "main_xtal");147 if (i < 0)148 return;149 mainxtal_name = of_clk_get_parent_name(np, i);150 151 regmap = device_node_to_regmap(np);152 if (IS_ERR(regmap))153 return;154 155 sama5d4_pmc = pmc_data_allocate(PMC_PLLACK + 1,156 nck(sama5d4_systemck),157 nck(sama5d4_periph32ck), 0, 3);158 if (!sama5d4_pmc)159 return;160 161 hw = at91_clk_register_main_rc_osc(regmap, "main_rc_osc", 12000000,162 100000000);163 if (IS_ERR(hw))164 goto err_free;165 166 bypass = of_property_read_bool(np, "atmel,osc-bypass");167 168 hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name, NULL,169 bypass);170 if (IS_ERR(hw))171 goto err_free;172 173 parent_names[0] = "main_rc_osc";174 parent_names[1] = "main_osc";175 hw = at91_clk_register_sam9x5_main(regmap, "mainck", parent_names, NULL, 2);176 if (IS_ERR(hw))177 goto err_free;178 179 hw = at91_clk_register_pll(regmap, "pllack", "mainck", 0,180 &sama5d3_pll_layout, &plla_characteristics);181 if (IS_ERR(hw))182 goto err_free;183 184 hw = at91_clk_register_plldiv(regmap, "plladivck", "pllack");185 if (IS_ERR(hw))186 goto err_free;187 188 sama5d4_pmc->chws[PMC_PLLACK] = hw;189 190 hw = at91_clk_register_utmi(regmap, NULL, "utmick", "mainck", NULL);191 if (IS_ERR(hw))192 goto err_free;193 194 sama5d4_pmc->chws[PMC_UTMI] = hw;195 196 parent_names[0] = slck_name;197 parent_names[1] = "mainck";198 parent_names[2] = "plladivck";199 parent_names[3] = "utmick";200 hw = at91_clk_register_master_pres(regmap, "masterck_pres", 4,201 parent_names, NULL,202 &at91sam9x5_master_layout,203 &mck_characteristics, &mck_lock);204 if (IS_ERR(hw))205 goto err_free;206 207 hw = at91_clk_register_master_div(regmap, "masterck_div",208 "masterck_pres", NULL,209 &at91sam9x5_master_layout,210 &mck_characteristics, &mck_lock,211 CLK_SET_RATE_GATE, 0);212 if (IS_ERR(hw))213 goto err_free;214 215 sama5d4_pmc->chws[PMC_MCK] = hw;216 217 hw = at91_clk_register_h32mx(regmap, "h32mxck", "masterck_div");218 if (IS_ERR(hw))219 goto err_free;220 221 sama5d4_pmc->chws[PMC_MCK2] = hw;222 223 parent_names[0] = "plladivck";224 parent_names[1] = "utmick";225 hw = at91sam9x5_clk_register_usb(regmap, "usbck", parent_names, 2);226 if (IS_ERR(hw))227 goto err_free;228 229 parent_names[0] = "plladivck";230 parent_names[1] = "utmick";231 hw = at91sam9x5_clk_register_smd(regmap, "smdclk", parent_names, 2);232 if (IS_ERR(hw))233 goto err_free;234 235 parent_names[0] = slck_name;236 parent_names[1] = "mainck";237 parent_names[2] = "plladivck";238 parent_names[3] = "utmick";239 parent_names[4] = "masterck_div";240 for (i = 0; i < 3; i++) {241 char name[6];242 243 snprintf(name, sizeof(name), "prog%d", i);244 245 hw = at91_clk_register_programmable(regmap, name,246 parent_names, NULL, 5, i,247 &at91sam9x5_programmable_layout,248 NULL);249 if (IS_ERR(hw))250 goto err_free;251 252 sama5d4_pmc->pchws[i] = hw;253 }254 255 for (i = 0; i < ARRAY_SIZE(sama5d4_systemck); i++) {256 hw = at91_clk_register_system(regmap, sama5d4_systemck[i].n,257 sama5d4_systemck[i].p, NULL,258 sama5d4_systemck[i].id,259 sama5d4_systemck[i].flags);260 if (IS_ERR(hw))261 goto err_free;262 263 sama5d4_pmc->shws[sama5d4_systemck[i].id] = hw;264 }265 266 for (i = 0; i < ARRAY_SIZE(sama5d4_periphck); i++) {267 hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock,268 &sama5d4_pcr_layout,269 sama5d4_periphck[i].n,270 "masterck_div", NULL,271 sama5d4_periphck[i].id,272 &range, INT_MIN,273 sama5d4_periphck[i].flags);274 if (IS_ERR(hw))275 goto err_free;276 277 sama5d4_pmc->phws[sama5d4_periphck[i].id] = hw;278 }279 280 for (i = 0; i < ARRAY_SIZE(sama5d4_periph32ck); i++) {281 hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock,282 &sama5d4_pcr_layout,283 sama5d4_periph32ck[i].n,284 "h32mxck", NULL,285 sama5d4_periph32ck[i].id,286 &range, INT_MIN, 0);287 if (IS_ERR(hw))288 goto err_free;289 290 sama5d4_pmc->phws[sama5d4_periph32ck[i].id] = hw;291 }292 293 of_clk_add_hw_provider(np, of_clk_hw_pmc_get, sama5d4_pmc);294 295 return;296 297err_free:298 kfree(sama5d4_pmc);299}300 301CLK_OF_DECLARE(sama5d4_pmc, "atmel,sama5d4-pmc", sama5d4_pmc_setup);302