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1// SPDX-License-Identifier: GPL-2.0-only2/*3 * Synopsys AXS10X SDP Generic PLL clock driver4 *5 * Copyright (C) 2017 Synopsys6 */7 8#include <linux/platform_device.h>9#include <linux/module.h>10#include <linux/clk-provider.h>11#include <linux/delay.h>12#include <linux/err.h>13#include <linux/device.h>14#include <linux/io.h>15#include <linux/of.h>16#include <linux/of_address.h>17#include <linux/slab.h>18 19/* PLL registers addresses */20#define PLL_REG_IDIV 0x021#define PLL_REG_FBDIV 0x422#define PLL_REG_ODIV 0x823 24/*25 * Bit fields of the PLL IDIV/FBDIV/ODIV registers:26 * ________________________________________________________________________27 * |31 15| 14 | 13 | 12 |11 6|5 0|28 * |-------RESRVED------|-NOUPDATE-|-BYPASS-|-EDGE-|--HIGHTIME--|--LOWTIME--|29 * |____________________|__________|________|______|____________|___________|30 *31 * Following macros determine the way of access to these registers32 * They should be set up only using the macros.33 * reg should be an u32 variable.34 */35 36#define PLL_REG_GET_LOW(reg) \37 (((reg) & (0x3F << 0)) >> 0)38#define PLL_REG_GET_HIGH(reg) \39 (((reg) & (0x3F << 6)) >> 6)40#define PLL_REG_GET_EDGE(reg) \41 (((reg) & (BIT(12))) ? 1 : 0)42#define PLL_REG_GET_BYPASS(reg) \43 (((reg) & (BIT(13))) ? 1 : 0)44#define PLL_REG_GET_NOUPD(reg) \45 (((reg) & (BIT(14))) ? 1 : 0)46#define PLL_REG_GET_PAD(reg) \47 (((reg) & (0x1FFFF << 15)) >> 15)48 49#define PLL_REG_SET_LOW(reg, value) \50 { reg |= (((value) & 0x3F) << 0); }51#define PLL_REG_SET_HIGH(reg, value) \52 { reg |= (((value) & 0x3F) << 6); }53#define PLL_REG_SET_EDGE(reg, value) \54 { reg |= (((value) & 0x01) << 12); }55#define PLL_REG_SET_BYPASS(reg, value) \56 { reg |= (((value) & 0x01) << 13); }57#define PLL_REG_SET_NOUPD(reg, value) \58 { reg |= (((value) & 0x01) << 14); }59#define PLL_REG_SET_PAD(reg, value) \60 { reg |= (((value) & 0x1FFFF) << 15); }61 62#define PLL_LOCK BIT(0)63#define PLL_ERROR BIT(1)64#define PLL_MAX_LOCK_TIME 100 /* 100 us */65 66struct axs10x_pll_cfg {67 u32 rate;68 u32 idiv;69 u32 fbdiv;70 u32 odiv;71};72 73static const struct axs10x_pll_cfg arc_pll_cfg[] = {74 { 33333333, 1, 1, 1 },75 { 50000000, 1, 30, 20 },76 { 75000000, 2, 45, 10 },77 { 90000000, 2, 54, 10 },78 { 100000000, 1, 30, 10 },79 { 125000000, 2, 45, 6 },80 {}81};82 83static const struct axs10x_pll_cfg pgu_pll_cfg[] = {84 { 25200000, 1, 84, 90 },85 { 50000000, 1, 100, 54 },86 { 74250000, 1, 44, 16 },87 {}88};89 90struct axs10x_pll_clk {91 struct clk_hw hw;92 void __iomem *base;93 void __iomem *lock;94 const struct axs10x_pll_cfg *pll_cfg;95 struct device *dev;96};97 98static inline void axs10x_pll_write(struct axs10x_pll_clk *clk, u32 reg,99 u32 val)100{101 iowrite32(val, clk->base + reg);102}103 104static inline u32 axs10x_pll_read(struct axs10x_pll_clk *clk, u32 reg)105{106 return ioread32(clk->base + reg);107}108 109static inline struct axs10x_pll_clk *to_axs10x_pll_clk(struct clk_hw *hw)110{111 return container_of(hw, struct axs10x_pll_clk, hw);112}113 114static inline u32 axs10x_div_get_value(u32 reg)115{116 if (PLL_REG_GET_BYPASS(reg))117 return 1;118 119 return PLL_REG_GET_HIGH(reg) + PLL_REG_GET_LOW(reg);120}121 122static inline u32 axs10x_encode_div(unsigned int id, int upd)123{124 u32 div = 0;125 126 PLL_REG_SET_LOW(div, (id % 2 == 0) ? id >> 1 : (id >> 1) + 1);127 PLL_REG_SET_HIGH(div, id >> 1);128 PLL_REG_SET_EDGE(div, id % 2);129 PLL_REG_SET_BYPASS(div, id == 1 ? 1 : 0);130 PLL_REG_SET_NOUPD(div, upd == 0 ? 1 : 0);131 132 return div;133}134 135static unsigned long axs10x_pll_recalc_rate(struct clk_hw *hw,136 unsigned long parent_rate)137{138 u64 rate;139 u32 idiv, fbdiv, odiv;140 struct axs10x_pll_clk *clk = to_axs10x_pll_clk(hw);141 142 idiv = axs10x_div_get_value(axs10x_pll_read(clk, PLL_REG_IDIV));143 fbdiv = axs10x_div_get_value(axs10x_pll_read(clk, PLL_REG_FBDIV));144 odiv = axs10x_div_get_value(axs10x_pll_read(clk, PLL_REG_ODIV));145 146 rate = (u64)parent_rate * fbdiv;147 do_div(rate, idiv * odiv);148 149 return rate;150}151 152static long axs10x_pll_round_rate(struct clk_hw *hw, unsigned long rate,153 unsigned long *prate)154{155 int i;156 long best_rate;157 struct axs10x_pll_clk *clk = to_axs10x_pll_clk(hw);158 const struct axs10x_pll_cfg *pll_cfg = clk->pll_cfg;159 160 if (pll_cfg[0].rate == 0)161 return -EINVAL;162 163 best_rate = pll_cfg[0].rate;164 165 for (i = 1; pll_cfg[i].rate != 0; i++) {166 if (abs(rate - pll_cfg[i].rate) < abs(rate - best_rate))167 best_rate = pll_cfg[i].rate;168 }169 170 return best_rate;171}172 173static int axs10x_pll_set_rate(struct clk_hw *hw, unsigned long rate,174 unsigned long parent_rate)175{176 int i;177 struct axs10x_pll_clk *clk = to_axs10x_pll_clk(hw);178 const struct axs10x_pll_cfg *pll_cfg = clk->pll_cfg;179 180 for (i = 0; pll_cfg[i].rate != 0; i++) {181 if (pll_cfg[i].rate == rate) {182 axs10x_pll_write(clk, PLL_REG_IDIV,183 axs10x_encode_div(pll_cfg[i].idiv, 0));184 axs10x_pll_write(clk, PLL_REG_FBDIV,185 axs10x_encode_div(pll_cfg[i].fbdiv, 0));186 axs10x_pll_write(clk, PLL_REG_ODIV,187 axs10x_encode_div(pll_cfg[i].odiv, 1));188 189 /*190 * Wait until CGU relocks and check error status.191 * If after timeout CGU is unlocked yet return error192 */193 udelay(PLL_MAX_LOCK_TIME);194 if (!(ioread32(clk->lock) & PLL_LOCK))195 return -ETIMEDOUT;196 197 if (ioread32(clk->lock) & PLL_ERROR)198 return -EINVAL;199 200 return 0;201 }202 }203 204 dev_err(clk->dev, "invalid rate=%ld, parent_rate=%ld\n", rate,205 parent_rate);206 return -EINVAL;207}208 209static const struct clk_ops axs10x_pll_ops = {210 .recalc_rate = axs10x_pll_recalc_rate,211 .round_rate = axs10x_pll_round_rate,212 .set_rate = axs10x_pll_set_rate,213};214 215static int axs10x_pll_clk_probe(struct platform_device *pdev)216{217 struct device *dev = &pdev->dev;218 const char *parent_name;219 struct axs10x_pll_clk *pll_clk;220 struct clk_init_data init = { };221 int ret;222 223 pll_clk = devm_kzalloc(dev, sizeof(*pll_clk), GFP_KERNEL);224 if (!pll_clk)225 return -ENOMEM;226 227 pll_clk->base = devm_platform_ioremap_resource(pdev, 0);228 if (IS_ERR(pll_clk->base))229 return PTR_ERR(pll_clk->base);230 231 pll_clk->lock = devm_platform_ioremap_resource(pdev, 1);232 if (IS_ERR(pll_clk->lock))233 return PTR_ERR(pll_clk->lock);234 235 init.name = dev->of_node->name;236 init.ops = &axs10x_pll_ops;237 parent_name = of_clk_get_parent_name(dev->of_node, 0);238 init.parent_names = &parent_name;239 init.num_parents = 1;240 pll_clk->hw.init = &init;241 pll_clk->dev = dev;242 pll_clk->pll_cfg = of_device_get_match_data(dev);243 244 if (!pll_clk->pll_cfg) {245 dev_err(dev, "No OF match data provided\n");246 return -EINVAL;247 }248 249 ret = devm_clk_hw_register(dev, &pll_clk->hw);250 if (ret) {251 dev_err(dev, "failed to register %s clock\n", init.name);252 return ret;253 }254 255 return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get,256 &pll_clk->hw);257}258 259static void __init of_axs10x_pll_clk_setup(struct device_node *node)260{261 const char *parent_name;262 struct axs10x_pll_clk *pll_clk;263 struct clk_init_data init = { };264 int ret;265 266 pll_clk = kzalloc(sizeof(*pll_clk), GFP_KERNEL);267 if (!pll_clk)268 return;269 270 pll_clk->base = of_iomap(node, 0);271 if (!pll_clk->base) {272 pr_err("failed to map pll div registers\n");273 goto err_free_pll_clk;274 }275 276 pll_clk->lock = of_iomap(node, 1);277 if (!pll_clk->lock) {278 pr_err("failed to map pll lock register\n");279 goto err_unmap_base;280 }281 282 init.name = node->name;283 init.ops = &axs10x_pll_ops;284 parent_name = of_clk_get_parent_name(node, 0);285 init.parent_names = &parent_name;286 init.num_parents = parent_name ? 1 : 0;287 pll_clk->hw.init = &init;288 pll_clk->pll_cfg = arc_pll_cfg;289 290 ret = clk_hw_register(NULL, &pll_clk->hw);291 if (ret) {292 pr_err("failed to register %pOFn clock\n", node);293 goto err_unmap_lock;294 }295 296 ret = of_clk_add_hw_provider(node, of_clk_hw_simple_get, &pll_clk->hw);297 if (ret) {298 pr_err("failed to add hw provider for %pOFn clock\n", node);299 goto err_unregister_clk;300 }301 302 return;303 304err_unregister_clk:305 clk_hw_unregister(&pll_clk->hw);306err_unmap_lock:307 iounmap(pll_clk->lock);308err_unmap_base:309 iounmap(pll_clk->base);310err_free_pll_clk:311 kfree(pll_clk);312}313CLK_OF_DECLARE(axs10x_pll_clock, "snps,axs10x-arc-pll-clock",314 of_axs10x_pll_clk_setup);315 316static const struct of_device_id axs10x_pll_clk_id[] = {317 { .compatible = "snps,axs10x-pgu-pll-clock", .data = &pgu_pll_cfg},318 { }319};320MODULE_DEVICE_TABLE(of, axs10x_pll_clk_id);321 322static struct platform_driver axs10x_pll_clk_driver = {323 .driver = {324 .name = "axs10x-pll-clock",325 .of_match_table = axs10x_pll_clk_id,326 },327 .probe = axs10x_pll_clk_probe,328};329builtin_platform_driver(axs10x_pll_clk_driver);330 331MODULE_AUTHOR("Vlad Zakharov <vzakhar@synopsys.com>");332MODULE_DESCRIPTION("Synopsys AXS10X SDP Generic PLL Clock Driver");333MODULE_LICENSE("GPL v2");334