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1# SPDX-License-Identifier: GPL-2.0-only2config CLK_BAIKAL_T13 bool "Baikal-T1 Clocks Control Unit interface"4 depends on (MIPS_BAIKAL_T1 && OF) || COMPILE_TEST5 default MIPS_BAIKAL_T16 help7 Clocks Control Unit is the core of Baikal-T1 SoC System Controller8 responsible for the chip subsystems clocking and resetting. It9 consists of multiple global clock domains, which can be reset by10 means of the CCU control registers. These domains and devices placed11 in them are fed with clocks generated by a hierarchy of PLLs,12 configurable and fixed clock dividers. Enable this option to be able13 to select Baikal-T1 CCU PLLs and Dividers drivers.14 15if CLK_BAIKAL_T116 17config CLK_BT1_CCU_PLL18 bool "Baikal-T1 CCU PLLs support"19 select MFD_SYSCON20 default MIPS_BAIKAL_T121 help22 Enable this to support the PLLs embedded into the Baikal-T1 SoC23 System Controller. These are five PLLs placed at the root of the24 clocks hierarchy, right after an external reference oscillator25 (normally of 25MHz). They are used to generate high frequency26 signals, which are either directly wired to the consumers (like27 CPUs, DDR, etc.) or passed over the clock dividers to be only28 then used as an individual reference clock of a target device.29 30config CLK_BT1_CCU_DIV31 bool "Baikal-T1 CCU Dividers support"32 select MFD_SYSCON33 default MIPS_BAIKAL_T134 help35 Enable this to support the CCU dividers used to distribute clocks36 between AXI-bus and system devices coming from CCU PLLs of Baikal-T137 SoC. CCU dividers can be either configurable or with fixed divider,38 either gateable or ungateable. Some of the CCU dividers can be as well39 used to reset the domains they're supplying clock to.40 41config CLK_BT1_CCU_RST42 bool "Baikal-T1 CCU Resets support"43 select RESET_CONTROLLER44 select MFD_SYSCON45 default MIPS_BAIKAL_T146 help47 Enable this to support the CCU reset blocks responsible for the48 AXI-bus and some subsystems reset. These are mainly the49 self-deasserted reset controls but there are several lines which50 can be directly asserted/de-asserted (PCIe and DDR sub-domains).51 52endif53