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1// SPDX-License-Identifier: GPL-2.0+2/*3 * Copyright (C) 2010,2015 Broadcom4 * Copyright (C) 2012 Stephen Warren5 */6 7/**8 * DOC: BCM2835 CPRMAN (clock manager for the "audio" domain)9 *10 * The clock tree on the 2835 has several levels. There's a root11 * oscillator running at 19.2Mhz. After the oscillator there are 512 * PLLs, roughly divided as "camera", "ARM", "core", "DSI displays",13 * and "HDMI displays". Those 5 PLLs each can divide their output to14 * produce up to 4 channels. Finally, there is the level of clocks to15 * be consumed by other hardware components (like "H264" or "HDMI16 * state machine"), which divide off of some subset of the PLL17 * channels.18 *19 * All of the clocks in the tree are exposed in the DT, because the DT20 * may want to make assignments of the final layer of clocks to the21 * PLL channels, and some components of the hardware will actually22 * skip layers of the tree (for example, the pixel clock comes23 * directly from the PLLH PIX channel without using a CM_*CTL clock24 * generator).25 */26 27#include <linux/clk-provider.h>28#include <linux/clkdev.h>29#include <linux/clk.h>30#include <linux/debugfs.h>31#include <linux/delay.h>32#include <linux/io.h>33#include <linux/math.h>34#include <linux/module.h>35#include <linux/of.h>36#include <linux/platform_device.h>37#include <linux/slab.h>38#include <dt-bindings/clock/bcm2835.h>39 40#define CM_PASSWORD 0x5a00000041 42#define CM_GNRICCTL 0x00043#define CM_GNRICDIV 0x00444# define CM_DIV_FRAC_BITS 1245# define CM_DIV_FRAC_MASK GENMASK(CM_DIV_FRAC_BITS - 1, 0)46 47#define CM_VPUCTL 0x00848#define CM_VPUDIV 0x00c49#define CM_SYSCTL 0x01050#define CM_SYSDIV 0x01451#define CM_PERIACTL 0x01852#define CM_PERIADIV 0x01c53#define CM_PERIICTL 0x02054#define CM_PERIIDIV 0x02455#define CM_H264CTL 0x02856#define CM_H264DIV 0x02c57#define CM_ISPCTL 0x03058#define CM_ISPDIV 0x03459#define CM_V3DCTL 0x03860#define CM_V3DDIV 0x03c61#define CM_CAM0CTL 0x04062#define CM_CAM0DIV 0x04463#define CM_CAM1CTL 0x04864#define CM_CAM1DIV 0x04c65#define CM_CCP2CTL 0x05066#define CM_CCP2DIV 0x05467#define CM_DSI0ECTL 0x05868#define CM_DSI0EDIV 0x05c69#define CM_DSI0PCTL 0x06070#define CM_DSI0PDIV 0x06471#define CM_DPICTL 0x06872#define CM_DPIDIV 0x06c73#define CM_GP0CTL 0x07074#define CM_GP0DIV 0x07475#define CM_GP1CTL 0x07876#define CM_GP1DIV 0x07c77#define CM_GP2CTL 0x08078#define CM_GP2DIV 0x08479#define CM_HSMCTL 0x08880#define CM_HSMDIV 0x08c81#define CM_OTPCTL 0x09082#define CM_OTPDIV 0x09483#define CM_PCMCTL 0x09884#define CM_PCMDIV 0x09c85#define CM_PWMCTL 0x0a086#define CM_PWMDIV 0x0a487#define CM_SLIMCTL 0x0a888#define CM_SLIMDIV 0x0ac89#define CM_SMICTL 0x0b090#define CM_SMIDIV 0x0b491/* no definition for 0x0b8 and 0x0bc */92#define CM_TCNTCTL 0x0c093# define CM_TCNT_SRC1_SHIFT 1294#define CM_TCNTCNT 0x0c495#define CM_TECCTL 0x0c896#define CM_TECDIV 0x0cc97#define CM_TD0CTL 0x0d098#define CM_TD0DIV 0x0d499#define CM_TD1CTL 0x0d8100#define CM_TD1DIV 0x0dc101#define CM_TSENSCTL 0x0e0102#define CM_TSENSDIV 0x0e4103#define CM_TIMERCTL 0x0e8104#define CM_TIMERDIV 0x0ec105#define CM_UARTCTL 0x0f0106#define CM_UARTDIV 0x0f4107#define CM_VECCTL 0x0f8108#define CM_VECDIV 0x0fc109#define CM_PULSECTL 0x190110#define CM_PULSEDIV 0x194111#define CM_SDCCTL 0x1a8112#define CM_SDCDIV 0x1ac113#define CM_ARMCTL 0x1b0114#define CM_AVEOCTL 0x1b8115#define CM_AVEODIV 0x1bc116#define CM_EMMCCTL 0x1c0117#define CM_EMMCDIV 0x1c4118#define CM_EMMC2CTL 0x1d0119#define CM_EMMC2DIV 0x1d4120 121/* General bits for the CM_*CTL regs */122# define CM_ENABLE BIT(4)123# define CM_KILL BIT(5)124# define CM_GATE_BIT 6125# define CM_GATE BIT(CM_GATE_BIT)126# define CM_BUSY BIT(7)127# define CM_BUSYD BIT(8)128# define CM_FRAC BIT(9)129# define CM_SRC_SHIFT 0130# define CM_SRC_BITS 4131# define CM_SRC_MASK 0xf132# define CM_SRC_GND 0133# define CM_SRC_OSC 1134# define CM_SRC_TESTDEBUG0 2135# define CM_SRC_TESTDEBUG1 3136# define CM_SRC_PLLA_CORE 4137# define CM_SRC_PLLA_PER 4138# define CM_SRC_PLLC_CORE0 5139# define CM_SRC_PLLC_PER 5140# define CM_SRC_PLLC_CORE1 8141# define CM_SRC_PLLD_CORE 6142# define CM_SRC_PLLD_PER 6143# define CM_SRC_PLLH_AUX 7144# define CM_SRC_PLLC_CORE1 8145# define CM_SRC_PLLC_CORE2 9146 147#define CM_OSCCOUNT 0x100148 149#define CM_PLLA 0x104150# define CM_PLL_ANARST BIT(8)151# define CM_PLLA_HOLDPER BIT(7)152# define CM_PLLA_LOADPER BIT(6)153# define CM_PLLA_HOLDCORE BIT(5)154# define CM_PLLA_LOADCORE BIT(4)155# define CM_PLLA_HOLDCCP2 BIT(3)156# define CM_PLLA_LOADCCP2 BIT(2)157# define CM_PLLA_HOLDDSI0 BIT(1)158# define CM_PLLA_LOADDSI0 BIT(0)159 160#define CM_PLLC 0x108161# define CM_PLLC_HOLDPER BIT(7)162# define CM_PLLC_LOADPER BIT(6)163# define CM_PLLC_HOLDCORE2 BIT(5)164# define CM_PLLC_LOADCORE2 BIT(4)165# define CM_PLLC_HOLDCORE1 BIT(3)166# define CM_PLLC_LOADCORE1 BIT(2)167# define CM_PLLC_HOLDCORE0 BIT(1)168# define CM_PLLC_LOADCORE0 BIT(0)169 170#define CM_PLLD 0x10c171# define CM_PLLD_HOLDPER BIT(7)172# define CM_PLLD_LOADPER BIT(6)173# define CM_PLLD_HOLDCORE BIT(5)174# define CM_PLLD_LOADCORE BIT(4)175# define CM_PLLD_HOLDDSI1 BIT(3)176# define CM_PLLD_LOADDSI1 BIT(2)177# define CM_PLLD_HOLDDSI0 BIT(1)178# define CM_PLLD_LOADDSI0 BIT(0)179 180#define CM_PLLH 0x110181# define CM_PLLH_LOADRCAL BIT(2)182# define CM_PLLH_LOADAUX BIT(1)183# define CM_PLLH_LOADPIX BIT(0)184 185#define CM_LOCK 0x114186# define CM_LOCK_FLOCKH BIT(12)187# define CM_LOCK_FLOCKD BIT(11)188# define CM_LOCK_FLOCKC BIT(10)189# define CM_LOCK_FLOCKB BIT(9)190# define CM_LOCK_FLOCKA BIT(8)191 192#define CM_EVENT 0x118193#define CM_DSI1ECTL 0x158194#define CM_DSI1EDIV 0x15c195#define CM_DSI1PCTL 0x160196#define CM_DSI1PDIV 0x164197#define CM_DFTCTL 0x168198#define CM_DFTDIV 0x16c199 200#define CM_PLLB 0x170201# define CM_PLLB_HOLDARM BIT(1)202# define CM_PLLB_LOADARM BIT(0)203 204#define A2W_PLLA_CTRL 0x1100205#define A2W_PLLC_CTRL 0x1120206#define A2W_PLLD_CTRL 0x1140207#define A2W_PLLH_CTRL 0x1160208#define A2W_PLLB_CTRL 0x11e0209# define A2W_PLL_CTRL_PRST_DISABLE BIT(17)210# define A2W_PLL_CTRL_PWRDN BIT(16)211# define A2W_PLL_CTRL_PDIV_MASK 0x000007000212# define A2W_PLL_CTRL_PDIV_SHIFT 12213# define A2W_PLL_CTRL_NDIV_MASK 0x0000003ff214# define A2W_PLL_CTRL_NDIV_SHIFT 0215 216#define A2W_PLLA_ANA0 0x1010217#define A2W_PLLC_ANA0 0x1030218#define A2W_PLLD_ANA0 0x1050219#define A2W_PLLH_ANA0 0x1070220#define A2W_PLLB_ANA0 0x10f0221 222#define A2W_PLL_KA_SHIFT 7223#define A2W_PLL_KA_MASK GENMASK(9, 7)224#define A2W_PLL_KI_SHIFT 19225#define A2W_PLL_KI_MASK GENMASK(21, 19)226#define A2W_PLL_KP_SHIFT 15227#define A2W_PLL_KP_MASK GENMASK(18, 15)228 229#define A2W_PLLH_KA_SHIFT 19230#define A2W_PLLH_KA_MASK GENMASK(21, 19)231#define A2W_PLLH_KI_LOW_SHIFT 22232#define A2W_PLLH_KI_LOW_MASK GENMASK(23, 22)233#define A2W_PLLH_KI_HIGH_SHIFT 0234#define A2W_PLLH_KI_HIGH_MASK GENMASK(0, 0)235#define A2W_PLLH_KP_SHIFT 1236#define A2W_PLLH_KP_MASK GENMASK(4, 1)237 238#define A2W_XOSC_CTRL 0x1190239# define A2W_XOSC_CTRL_PLLB_ENABLE BIT(7)240# define A2W_XOSC_CTRL_PLLA_ENABLE BIT(6)241# define A2W_XOSC_CTRL_PLLD_ENABLE BIT(5)242# define A2W_XOSC_CTRL_DDR_ENABLE BIT(4)243# define A2W_XOSC_CTRL_CPR1_ENABLE BIT(3)244# define A2W_XOSC_CTRL_USB_ENABLE BIT(2)245# define A2W_XOSC_CTRL_HDMI_ENABLE BIT(1)246# define A2W_XOSC_CTRL_PLLC_ENABLE BIT(0)247 248#define A2W_PLLA_FRAC 0x1200249#define A2W_PLLC_FRAC 0x1220250#define A2W_PLLD_FRAC 0x1240251#define A2W_PLLH_FRAC 0x1260252#define A2W_PLLB_FRAC 0x12e0253# define A2W_PLL_FRAC_MASK ((1 << A2W_PLL_FRAC_BITS) - 1)254# define A2W_PLL_FRAC_BITS 20255 256#define A2W_PLL_CHANNEL_DISABLE BIT(8)257#define A2W_PLL_DIV_BITS 8258#define A2W_PLL_DIV_SHIFT 0259 260#define A2W_PLLA_DSI0 0x1300261#define A2W_PLLA_CORE 0x1400262#define A2W_PLLA_PER 0x1500263#define A2W_PLLA_CCP2 0x1600264 265#define A2W_PLLC_CORE2 0x1320266#define A2W_PLLC_CORE1 0x1420267#define A2W_PLLC_PER 0x1520268#define A2W_PLLC_CORE0 0x1620269 270#define A2W_PLLD_DSI0 0x1340271#define A2W_PLLD_CORE 0x1440272#define A2W_PLLD_PER 0x1540273#define A2W_PLLD_DSI1 0x1640274 275#define A2W_PLLH_AUX 0x1360276#define A2W_PLLH_RCAL 0x1460277#define A2W_PLLH_PIX 0x1560278#define A2W_PLLH_STS 0x1660279 280#define A2W_PLLH_CTRLR 0x1960281#define A2W_PLLH_FRACR 0x1a60282#define A2W_PLLH_AUXR 0x1b60283#define A2W_PLLH_RCALR 0x1c60284#define A2W_PLLH_PIXR 0x1d60285#define A2W_PLLH_STSR 0x1e60286 287#define A2W_PLLB_ARM 0x13e0288#define A2W_PLLB_SP0 0x14e0289#define A2W_PLLB_SP1 0x15e0290#define A2W_PLLB_SP2 0x16e0291 292#define LOCK_TIMEOUT_NS 100000000293#define BCM2835_MAX_FB_RATE 1750000000u294 295#define SOC_BCM2835 BIT(0)296#define SOC_BCM2711 BIT(1)297#define SOC_ALL (SOC_BCM2835 | SOC_BCM2711)298 299/*300 * Names of clocks used within the driver that need to be replaced301 * with an external parent's name. This array is in the order that302 * the clocks node in the DT references external clocks.303 */304static const char *const cprman_parent_names[] = {305 "xosc",306 "dsi0_byte",307 "dsi0_ddr2",308 "dsi0_ddr",309 "dsi1_byte",310 "dsi1_ddr2",311 "dsi1_ddr",312};313 314struct bcm2835_cprman {315 struct device *dev;316 void __iomem *regs;317 spinlock_t regs_lock; /* spinlock for all clocks */318 unsigned int soc;319 320 /*321 * Real names of cprman clock parents looked up through322 * of_clk_get_parent_name(), which will be used in the323 * parent_names[] arrays for clock registration.324 */325 const char *real_parent_names[ARRAY_SIZE(cprman_parent_names)];326 327 /* Must be last */328 struct clk_hw_onecell_data onecell;329};330 331struct cprman_plat_data {332 unsigned int soc;333};334 335static inline void cprman_write(struct bcm2835_cprman *cprman, u32 reg, u32 val)336{337 writel(CM_PASSWORD | val, cprman->regs + reg);338}339 340static inline u32 cprman_read(struct bcm2835_cprman *cprman, u32 reg)341{342 return readl(cprman->regs + reg);343}344 345/* Does a cycle of measuring a clock through the TCNT clock, which may346 * source from many other clocks in the system.347 */348static unsigned long bcm2835_measure_tcnt_mux(struct bcm2835_cprman *cprman,349 u32 tcnt_mux)350{351 u32 osccount = 19200; /* 1ms */352 u32 count;353 ktime_t timeout;354 355 spin_lock(&cprman->regs_lock);356 357 cprman_write(cprman, CM_TCNTCTL, CM_KILL);358 359 cprman_write(cprman, CM_TCNTCTL,360 (tcnt_mux & CM_SRC_MASK) |361 (tcnt_mux >> CM_SRC_BITS) << CM_TCNT_SRC1_SHIFT);362 363 cprman_write(cprman, CM_OSCCOUNT, osccount);364 365 /* do a kind delay at the start */366 mdelay(1);367 368 /* Finish off whatever is left of OSCCOUNT */369 timeout = ktime_add_ns(ktime_get(), LOCK_TIMEOUT_NS);370 while (cprman_read(cprman, CM_OSCCOUNT)) {371 if (ktime_after(ktime_get(), timeout)) {372 dev_err(cprman->dev, "timeout waiting for OSCCOUNT\n");373 count = 0;374 goto out;375 }376 cpu_relax();377 }378 379 /* Wait for BUSY to clear. */380 timeout = ktime_add_ns(ktime_get(), LOCK_TIMEOUT_NS);381 while (cprman_read(cprman, CM_TCNTCTL) & CM_BUSY) {382 if (ktime_after(ktime_get(), timeout)) {383 dev_err(cprman->dev, "timeout waiting for !BUSY\n");384 count = 0;385 goto out;386 }387 cpu_relax();388 }389 390 count = cprman_read(cprman, CM_TCNTCNT);391 392 cprman_write(cprman, CM_TCNTCTL, 0);393 394out:395 spin_unlock(&cprman->regs_lock);396 397 return count * 1000;398}399 400static void bcm2835_debugfs_regset(struct bcm2835_cprman *cprman, u32 base,401 const struct debugfs_reg32 *regs,402 size_t nregs, struct dentry *dentry)403{404 struct debugfs_regset32 *regset;405 406 regset = devm_kzalloc(cprman->dev, sizeof(*regset), GFP_KERNEL);407 if (!regset)408 return;409 410 regset->regs = regs;411 regset->nregs = nregs;412 regset->base = cprman->regs + base;413 414 debugfs_create_regset32("regdump", S_IRUGO, dentry, regset);415}416 417struct bcm2835_pll_data {418 const char *name;419 u32 cm_ctrl_reg;420 u32 a2w_ctrl_reg;421 u32 frac_reg;422 u32 ana_reg_base;423 u32 reference_enable_mask;424 /* Bit in CM_LOCK to indicate when the PLL has locked. */425 u32 lock_mask;426 u32 flags;427 428 const struct bcm2835_pll_ana_bits *ana;429 430 unsigned long min_rate;431 unsigned long max_rate;432 /*433 * Highest rate for the VCO before we have to use the434 * pre-divide-by-2.435 */436 unsigned long max_fb_rate;437};438 439struct bcm2835_pll_ana_bits {440 u32 mask0;441 u32 set0;442 u32 mask1;443 u32 set1;444 u32 mask3;445 u32 set3;446 u32 fb_prediv_mask;447};448 449static const struct bcm2835_pll_ana_bits bcm2835_ana_default = {450 .mask0 = 0,451 .set0 = 0,452 .mask1 = A2W_PLL_KI_MASK | A2W_PLL_KP_MASK,453 .set1 = (2 << A2W_PLL_KI_SHIFT) | (8 << A2W_PLL_KP_SHIFT),454 .mask3 = A2W_PLL_KA_MASK,455 .set3 = (2 << A2W_PLL_KA_SHIFT),456 .fb_prediv_mask = BIT(14),457};458 459static const struct bcm2835_pll_ana_bits bcm2835_ana_pllh = {460 .mask0 = A2W_PLLH_KA_MASK | A2W_PLLH_KI_LOW_MASK,461 .set0 = (2 << A2W_PLLH_KA_SHIFT) | (2 << A2W_PLLH_KI_LOW_SHIFT),462 .mask1 = A2W_PLLH_KI_HIGH_MASK | A2W_PLLH_KP_MASK,463 .set1 = (6 << A2W_PLLH_KP_SHIFT),464 .mask3 = 0,465 .set3 = 0,466 .fb_prediv_mask = BIT(11),467};468 469struct bcm2835_pll_divider_data {470 const char *name;471 const char *source_pll;472 473 u32 cm_reg;474 u32 a2w_reg;475 476 u32 load_mask;477 u32 hold_mask;478 u32 fixed_divider;479 u32 flags;480};481 482struct bcm2835_clock_data {483 const char *name;484 485 const char *const *parents;486 int num_mux_parents;487 488 /* Bitmap encoding which parents accept rate change propagation. */489 unsigned int set_rate_parent;490 491 u32 ctl_reg;492 u32 div_reg;493 494 /* Number of integer bits in the divider */495 u32 int_bits;496 /* Number of fractional bits in the divider */497 u32 frac_bits;498 499 u32 flags;500 501 bool is_vpu_clock;502 bool is_mash_clock;503 bool low_jitter;504 505 u32 tcnt_mux;506 507 bool round_up;508};509 510struct bcm2835_gate_data {511 const char *name;512 const char *parent;513 514 u32 ctl_reg;515};516 517struct bcm2835_pll {518 struct clk_hw hw;519 struct bcm2835_cprman *cprman;520 const struct bcm2835_pll_data *data;521};522 523static int bcm2835_pll_is_on(struct clk_hw *hw)524{525 struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw);526 struct bcm2835_cprman *cprman = pll->cprman;527 const struct bcm2835_pll_data *data = pll->data;528 529 return cprman_read(cprman, data->a2w_ctrl_reg) &530 A2W_PLL_CTRL_PRST_DISABLE;531}532 533static u32 bcm2835_pll_get_prediv_mask(struct bcm2835_cprman *cprman,534 const struct bcm2835_pll_data *data)535{536 /*537 * On BCM2711 there isn't a pre-divisor available in the PLL feedback538 * loop. Bits 13:14 of ANA1 (PLLA,PLLB,PLLC,PLLD) have been re-purposed539 * for to for VCO RANGE bits.540 */541 if (cprman->soc & SOC_BCM2711)542 return 0;543 544 return data->ana->fb_prediv_mask;545}546 547static void bcm2835_pll_choose_ndiv_and_fdiv(unsigned long rate,548 unsigned long parent_rate,549 u32 *ndiv, u32 *fdiv)550{551 u64 div;552 553 div = (u64)rate << A2W_PLL_FRAC_BITS;554 do_div(div, parent_rate);555 556 *ndiv = div >> A2W_PLL_FRAC_BITS;557 *fdiv = div & ((1 << A2W_PLL_FRAC_BITS) - 1);558}559 560static long bcm2835_pll_rate_from_divisors(unsigned long parent_rate,561 u32 ndiv, u32 fdiv, u32 pdiv)562{563 u64 rate;564 565 if (pdiv == 0)566 return 0;567 568 rate = (u64)parent_rate * ((ndiv << A2W_PLL_FRAC_BITS) + fdiv);569 do_div(rate, pdiv);570 return rate >> A2W_PLL_FRAC_BITS;571}572 573static long bcm2835_pll_round_rate(struct clk_hw *hw, unsigned long rate,574 unsigned long *parent_rate)575{576 struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw);577 const struct bcm2835_pll_data *data = pll->data;578 u32 ndiv, fdiv;579 580 rate = clamp(rate, data->min_rate, data->max_rate);581 582 bcm2835_pll_choose_ndiv_and_fdiv(rate, *parent_rate, &ndiv, &fdiv);583 584 return bcm2835_pll_rate_from_divisors(*parent_rate, ndiv, fdiv, 1);585}586 587static unsigned long bcm2835_pll_get_rate(struct clk_hw *hw,588 unsigned long parent_rate)589{590 struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw);591 struct bcm2835_cprman *cprman = pll->cprman;592 const struct bcm2835_pll_data *data = pll->data;593 u32 a2wctrl = cprman_read(cprman, data->a2w_ctrl_reg);594 u32 ndiv, pdiv, fdiv;595 bool using_prediv;596 597 if (parent_rate == 0)598 return 0;599 600 fdiv = cprman_read(cprman, data->frac_reg) & A2W_PLL_FRAC_MASK;601 ndiv = (a2wctrl & A2W_PLL_CTRL_NDIV_MASK) >> A2W_PLL_CTRL_NDIV_SHIFT;602 pdiv = (a2wctrl & A2W_PLL_CTRL_PDIV_MASK) >> A2W_PLL_CTRL_PDIV_SHIFT;603 using_prediv = cprman_read(cprman, data->ana_reg_base + 4) &604 bcm2835_pll_get_prediv_mask(cprman, data);605 606 if (using_prediv) {607 ndiv *= 2;608 fdiv *= 2;609 }610 611 return bcm2835_pll_rate_from_divisors(parent_rate, ndiv, fdiv, pdiv);612}613 614static void bcm2835_pll_off(struct clk_hw *hw)615{616 struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw);617 struct bcm2835_cprman *cprman = pll->cprman;618 const struct bcm2835_pll_data *data = pll->data;619 620 spin_lock(&cprman->regs_lock);621 cprman_write(cprman, data->cm_ctrl_reg, CM_PLL_ANARST);622 cprman_write(cprman, data->a2w_ctrl_reg,623 cprman_read(cprman, data->a2w_ctrl_reg) |624 A2W_PLL_CTRL_PWRDN);625 spin_unlock(&cprman->regs_lock);626}627 628static int bcm2835_pll_on(struct clk_hw *hw)629{630 struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw);631 struct bcm2835_cprman *cprman = pll->cprman;632 const struct bcm2835_pll_data *data = pll->data;633 ktime_t timeout;634 635 cprman_write(cprman, data->a2w_ctrl_reg,636 cprman_read(cprman, data->a2w_ctrl_reg) &637 ~A2W_PLL_CTRL_PWRDN);638 639 /* Take the PLL out of reset. */640 spin_lock(&cprman->regs_lock);641 cprman_write(cprman, data->cm_ctrl_reg,642 cprman_read(cprman, data->cm_ctrl_reg) & ~CM_PLL_ANARST);643 spin_unlock(&cprman->regs_lock);644 645 /* Wait for the PLL to lock. */646 timeout = ktime_add_ns(ktime_get(), LOCK_TIMEOUT_NS);647 while (!(cprman_read(cprman, CM_LOCK) & data->lock_mask)) {648 if (ktime_after(ktime_get(), timeout)) {649 dev_err(cprman->dev, "%s: couldn't lock PLL\n",650 clk_hw_get_name(hw));651 return -ETIMEDOUT;652 }653 654 cpu_relax();655 }656 657 cprman_write(cprman, data->a2w_ctrl_reg,658 cprman_read(cprman, data->a2w_ctrl_reg) |659 A2W_PLL_CTRL_PRST_DISABLE);660 661 return 0;662}663 664static void665bcm2835_pll_write_ana(struct bcm2835_cprman *cprman, u32 ana_reg_base, u32 *ana)666{667 int i;668 669 /*670 * ANA register setup is done as a series of writes to671 * ANA3-ANA0, in that order. This lets us write all 4672 * registers as a single cycle of the serdes interface (taking673 * 100 xosc clocks), whereas if we were to update ana0, 1, and674 * 3 individually through their partial-write registers, each675 * would be their own serdes cycle.676 */677 for (i = 3; i >= 0; i--)678 cprman_write(cprman, ana_reg_base + i * 4, ana[i]);679}680 681static int bcm2835_pll_set_rate(struct clk_hw *hw,682 unsigned long rate, unsigned long parent_rate)683{684 struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw);685 struct bcm2835_cprman *cprman = pll->cprman;686 const struct bcm2835_pll_data *data = pll->data;687 u32 prediv_mask = bcm2835_pll_get_prediv_mask(cprman, data);688 bool was_using_prediv, use_fb_prediv, do_ana_setup_first;689 u32 ndiv, fdiv, a2w_ctl;690 u32 ana[4];691 int i;692 693 if (rate > data->max_fb_rate) {694 use_fb_prediv = true;695 rate /= 2;696 } else {697 use_fb_prediv = false;698 }699 700 bcm2835_pll_choose_ndiv_and_fdiv(rate, parent_rate, &ndiv, &fdiv);701 702 for (i = 3; i >= 0; i--)703 ana[i] = cprman_read(cprman, data->ana_reg_base + i * 4);704 705 was_using_prediv = ana[1] & prediv_mask;706 707 ana[0] &= ~data->ana->mask0;708 ana[0] |= data->ana->set0;709 ana[1] &= ~data->ana->mask1;710 ana[1] |= data->ana->set1;711 ana[3] &= ~data->ana->mask3;712 ana[3] |= data->ana->set3;713 714 if (was_using_prediv && !use_fb_prediv) {715 ana[1] &= ~prediv_mask;716 do_ana_setup_first = true;717 } else if (!was_using_prediv && use_fb_prediv) {718 ana[1] |= prediv_mask;719 do_ana_setup_first = false;720 } else {721 do_ana_setup_first = true;722 }723 724 /* Unmask the reference clock from the oscillator. */725 spin_lock(&cprman->regs_lock);726 cprman_write(cprman, A2W_XOSC_CTRL,727 cprman_read(cprman, A2W_XOSC_CTRL) |728 data->reference_enable_mask);729 spin_unlock(&cprman->regs_lock);730 731 if (do_ana_setup_first)732 bcm2835_pll_write_ana(cprman, data->ana_reg_base, ana);733 734 /* Set the PLL multiplier from the oscillator. */735 cprman_write(cprman, data->frac_reg, fdiv);736 737 a2w_ctl = cprman_read(cprman, data->a2w_ctrl_reg);738 a2w_ctl &= ~A2W_PLL_CTRL_NDIV_MASK;739 a2w_ctl |= ndiv << A2W_PLL_CTRL_NDIV_SHIFT;740 a2w_ctl &= ~A2W_PLL_CTRL_PDIV_MASK;741 a2w_ctl |= 1 << A2W_PLL_CTRL_PDIV_SHIFT;742 cprman_write(cprman, data->a2w_ctrl_reg, a2w_ctl);743 744 if (!do_ana_setup_first)745 bcm2835_pll_write_ana(cprman, data->ana_reg_base, ana);746 747 return 0;748}749 750static void bcm2835_pll_debug_init(struct clk_hw *hw,751 struct dentry *dentry)752{753 struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw);754 struct bcm2835_cprman *cprman = pll->cprman;755 const struct bcm2835_pll_data *data = pll->data;756 struct debugfs_reg32 *regs;757 758 regs = devm_kcalloc(cprman->dev, 7, sizeof(*regs), GFP_KERNEL);759 if (!regs)760 return;761 762 regs[0].name = "cm_ctrl";763 regs[0].offset = data->cm_ctrl_reg;764 regs[1].name = "a2w_ctrl";765 regs[1].offset = data->a2w_ctrl_reg;766 regs[2].name = "frac";767 regs[2].offset = data->frac_reg;768 regs[3].name = "ana0";769 regs[3].offset = data->ana_reg_base + 0 * 4;770 regs[4].name = "ana1";771 regs[4].offset = data->ana_reg_base + 1 * 4;772 regs[5].name = "ana2";773 regs[5].offset = data->ana_reg_base + 2 * 4;774 regs[6].name = "ana3";775 regs[6].offset = data->ana_reg_base + 3 * 4;776 777 bcm2835_debugfs_regset(cprman, 0, regs, 7, dentry);778}779 780static const struct clk_ops bcm2835_pll_clk_ops = {781 .is_prepared = bcm2835_pll_is_on,782 .prepare = bcm2835_pll_on,783 .unprepare = bcm2835_pll_off,784 .recalc_rate = bcm2835_pll_get_rate,785 .set_rate = bcm2835_pll_set_rate,786 .round_rate = bcm2835_pll_round_rate,787 .debug_init = bcm2835_pll_debug_init,788};789 790struct bcm2835_pll_divider {791 struct clk_divider div;792 struct bcm2835_cprman *cprman;793 const struct bcm2835_pll_divider_data *data;794};795 796static struct bcm2835_pll_divider *797bcm2835_pll_divider_from_hw(struct clk_hw *hw)798{799 return container_of(hw, struct bcm2835_pll_divider, div.hw);800}801 802static int bcm2835_pll_divider_is_on(struct clk_hw *hw)803{804 struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw);805 struct bcm2835_cprman *cprman = divider->cprman;806 const struct bcm2835_pll_divider_data *data = divider->data;807 808 return !(cprman_read(cprman, data->a2w_reg) & A2W_PLL_CHANNEL_DISABLE);809}810 811static int bcm2835_pll_divider_determine_rate(struct clk_hw *hw,812 struct clk_rate_request *req)813{814 return clk_divider_ops.determine_rate(hw, req);815}816 817static unsigned long bcm2835_pll_divider_get_rate(struct clk_hw *hw,818 unsigned long parent_rate)819{820 return clk_divider_ops.recalc_rate(hw, parent_rate);821}822 823static void bcm2835_pll_divider_off(struct clk_hw *hw)824{825 struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw);826 struct bcm2835_cprman *cprman = divider->cprman;827 const struct bcm2835_pll_divider_data *data = divider->data;828 829 spin_lock(&cprman->regs_lock);830 cprman_write(cprman, data->cm_reg,831 (cprman_read(cprman, data->cm_reg) &832 ~data->load_mask) | data->hold_mask);833 cprman_write(cprman, data->a2w_reg,834 cprman_read(cprman, data->a2w_reg) |835 A2W_PLL_CHANNEL_DISABLE);836 spin_unlock(&cprman->regs_lock);837}838 839static int bcm2835_pll_divider_on(struct clk_hw *hw)840{841 struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw);842 struct bcm2835_cprman *cprman = divider->cprman;843 const struct bcm2835_pll_divider_data *data = divider->data;844 845 spin_lock(&cprman->regs_lock);846 cprman_write(cprman, data->a2w_reg,847 cprman_read(cprman, data->a2w_reg) &848 ~A2W_PLL_CHANNEL_DISABLE);849 850 cprman_write(cprman, data->cm_reg,851 cprman_read(cprman, data->cm_reg) & ~data->hold_mask);852 spin_unlock(&cprman->regs_lock);853 854 return 0;855}856 857static int bcm2835_pll_divider_set_rate(struct clk_hw *hw,858 unsigned long rate,859 unsigned long parent_rate)860{861 struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw);862 struct bcm2835_cprman *cprman = divider->cprman;863 const struct bcm2835_pll_divider_data *data = divider->data;864 u32 cm, div, max_div = 1 << A2W_PLL_DIV_BITS;865 866 div = DIV_ROUND_UP_ULL(parent_rate, rate);867 868 div = min(div, max_div);869 if (div == max_div)870 div = 0;871 872 cprman_write(cprman, data->a2w_reg, div);873 cm = cprman_read(cprman, data->cm_reg);874 cprman_write(cprman, data->cm_reg, cm | data->load_mask);875 cprman_write(cprman, data->cm_reg, cm & ~data->load_mask);876 877 return 0;878}879 880static void bcm2835_pll_divider_debug_init(struct clk_hw *hw,881 struct dentry *dentry)882{883 struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw);884 struct bcm2835_cprman *cprman = divider->cprman;885 const struct bcm2835_pll_divider_data *data = divider->data;886 struct debugfs_reg32 *regs;887 888 regs = devm_kcalloc(cprman->dev, 7, sizeof(*regs), GFP_KERNEL);889 if (!regs)890 return;891 892 regs[0].name = "cm";893 regs[0].offset = data->cm_reg;894 regs[1].name = "a2w";895 regs[1].offset = data->a2w_reg;896 897 bcm2835_debugfs_regset(cprman, 0, regs, 2, dentry);898}899 900static const struct clk_ops bcm2835_pll_divider_clk_ops = {901 .is_prepared = bcm2835_pll_divider_is_on,902 .prepare = bcm2835_pll_divider_on,903 .unprepare = bcm2835_pll_divider_off,904 .recalc_rate = bcm2835_pll_divider_get_rate,905 .set_rate = bcm2835_pll_divider_set_rate,906 .determine_rate = bcm2835_pll_divider_determine_rate,907 .debug_init = bcm2835_pll_divider_debug_init,908};909 910/*911 * The CM dividers do fixed-point division, so we can't use the912 * generic integer divider code like the PLL dividers do (and we can't913 * fake it by having some fixed shifts preceding it in the clock tree,914 * because we'd run out of bits in a 32-bit unsigned long).915 */916struct bcm2835_clock {917 struct clk_hw hw;918 struct bcm2835_cprman *cprman;919 const struct bcm2835_clock_data *data;920};921 922static struct bcm2835_clock *bcm2835_clock_from_hw(struct clk_hw *hw)923{924 return container_of(hw, struct bcm2835_clock, hw);925}926 927static int bcm2835_clock_is_on(struct clk_hw *hw)928{929 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);930 struct bcm2835_cprman *cprman = clock->cprman;931 const struct bcm2835_clock_data *data = clock->data;932 933 return (cprman_read(cprman, data->ctl_reg) & CM_ENABLE) != 0;934}935 936static u32 bcm2835_clock_choose_div(struct clk_hw *hw,937 unsigned long rate,938 unsigned long parent_rate)939{940 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);941 const struct bcm2835_clock_data *data = clock->data;942 u32 unused_frac_mask =943 GENMASK(CM_DIV_FRAC_BITS - data->frac_bits, 0) >> 1;944 u64 temp = (u64)parent_rate << CM_DIV_FRAC_BITS;945 u32 div, mindiv, maxdiv;946 947 do_div(temp, rate);948 div = temp;949 div &= ~unused_frac_mask;950 951 /* different clamping limits apply for a mash clock */952 if (data->is_mash_clock) {953 /* clamp to min divider of 2 */954 mindiv = 2 << CM_DIV_FRAC_BITS;955 /* clamp to the highest possible integer divider */956 maxdiv = (BIT(data->int_bits) - 1) << CM_DIV_FRAC_BITS;957 } else {958 /* clamp to min divider of 1 */959 mindiv = 1 << CM_DIV_FRAC_BITS;960 /* clamp to the highest possible fractional divider */961 maxdiv = GENMASK(data->int_bits + CM_DIV_FRAC_BITS - 1,962 CM_DIV_FRAC_BITS - data->frac_bits);963 }964 965 /* apply the clamping limits */966 div = max_t(u32, div, mindiv);967 div = min_t(u32, div, maxdiv);968 969 return div;970}971 972static unsigned long bcm2835_clock_rate_from_divisor(struct bcm2835_clock *clock,973 unsigned long parent_rate,974 u32 div)975{976 const struct bcm2835_clock_data *data = clock->data;977 u64 temp;978 979 if (data->int_bits == 0 && data->frac_bits == 0)980 return parent_rate;981 982 /*983 * The divisor is a 12.12 fixed point field, but only some of984 * the bits are populated in any given clock.985 */986 div >>= CM_DIV_FRAC_BITS - data->frac_bits;987 div &= (1 << (data->int_bits + data->frac_bits)) - 1;988 989 if (div == 0)990 return 0;991 992 temp = (u64)parent_rate << data->frac_bits;993 994 do_div(temp, div);995 996 return temp;997}998 999static unsigned long bcm2835_round_rate(unsigned long rate)1000{1001 unsigned long scaler;1002 unsigned long limit;1003 1004 limit = rate / 100000;1005 1006 scaler = 1;1007 while (scaler < limit)1008 scaler *= 10;1009 1010 /*1011 * If increasing a clock by less than 0.1% changes it1012 * from ..999.. to ..000.., round up.1013 */1014 if ((rate + scaler - 1) / scaler % 1000 == 0)1015 rate = roundup(rate, scaler);1016 1017 return rate;1018}1019 1020static unsigned long bcm2835_clock_get_rate(struct clk_hw *hw,1021 unsigned long parent_rate)1022{1023 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);1024 struct bcm2835_cprman *cprman = clock->cprman;1025 const struct bcm2835_clock_data *data = clock->data;1026 unsigned long rate;1027 u32 div;1028 1029 if (data->int_bits == 0 && data->frac_bits == 0)1030 return parent_rate;1031 1032 div = cprman_read(cprman, data->div_reg);1033 1034 rate = bcm2835_clock_rate_from_divisor(clock, parent_rate, div);1035 1036 if (data->round_up)1037 rate = bcm2835_round_rate(rate);1038 1039 return rate;1040}1041 1042static void bcm2835_clock_wait_busy(struct bcm2835_clock *clock)1043{1044 struct bcm2835_cprman *cprman = clock->cprman;1045 const struct bcm2835_clock_data *data = clock->data;1046 ktime_t timeout = ktime_add_ns(ktime_get(), LOCK_TIMEOUT_NS);1047 1048 while (cprman_read(cprman, data->ctl_reg) & CM_BUSY) {1049 if (ktime_after(ktime_get(), timeout)) {1050 dev_err(cprman->dev, "%s: couldn't lock PLL\n",1051 clk_hw_get_name(&clock->hw));1052 return;1053 }1054 cpu_relax();1055 }1056}1057 1058static void bcm2835_clock_off(struct clk_hw *hw)1059{1060 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);1061 struct bcm2835_cprman *cprman = clock->cprman;1062 const struct bcm2835_clock_data *data = clock->data;1063 1064 spin_lock(&cprman->regs_lock);1065 cprman_write(cprman, data->ctl_reg,1066 cprman_read(cprman, data->ctl_reg) & ~CM_ENABLE);1067 spin_unlock(&cprman->regs_lock);1068 1069 /* BUSY will remain high until the divider completes its cycle. */1070 bcm2835_clock_wait_busy(clock);1071}1072 1073static int bcm2835_clock_on(struct clk_hw *hw)1074{1075 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);1076 struct bcm2835_cprman *cprman = clock->cprman;1077 const struct bcm2835_clock_data *data = clock->data;1078 1079 spin_lock(&cprman->regs_lock);1080 cprman_write(cprman, data->ctl_reg,1081 cprman_read(cprman, data->ctl_reg) |1082 CM_ENABLE |1083 CM_GATE);1084 spin_unlock(&cprman->regs_lock);1085 1086 /* Debug code to measure the clock once it's turned on to see1087 * if it's ticking at the rate we expect.1088 */1089 if (data->tcnt_mux && false) {1090 dev_info(cprman->dev,1091 "clk %s: rate %ld, measure %ld\n",1092 data->name,1093 clk_hw_get_rate(hw),1094 bcm2835_measure_tcnt_mux(cprman, data->tcnt_mux));1095 }1096 1097 return 0;1098}1099 1100static int bcm2835_clock_set_rate(struct clk_hw *hw,1101 unsigned long rate, unsigned long parent_rate)1102{1103 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);1104 struct bcm2835_cprman *cprman = clock->cprman;1105 const struct bcm2835_clock_data *data = clock->data;1106 u32 div = bcm2835_clock_choose_div(hw, rate, parent_rate);1107 u32 ctl;1108 1109 spin_lock(&cprman->regs_lock);1110 1111 /*1112 * Setting up frac support1113 *1114 * In principle it is recommended to stop/start the clock first,1115 * but as we set CLK_SET_RATE_GATE during registration of the1116 * clock this requirement should be take care of by the1117 * clk-framework.1118 */1119 ctl = cprman_read(cprman, data->ctl_reg) & ~CM_FRAC;1120 ctl |= (div & CM_DIV_FRAC_MASK) ? CM_FRAC : 0;1121 cprman_write(cprman, data->ctl_reg, ctl);1122 1123 cprman_write(cprman, data->div_reg, div);1124 1125 spin_unlock(&cprman->regs_lock);1126 1127 return 0;1128}1129 1130static bool1131bcm2835_clk_is_pllc(struct clk_hw *hw)1132{1133 if (!hw)1134 return false;1135 1136 return strncmp(clk_hw_get_name(hw), "pllc", 4) == 0;1137}1138 1139static unsigned long bcm2835_clock_choose_div_and_prate(struct clk_hw *hw,1140 int parent_idx,1141 unsigned long rate,1142 u32 *div,1143 unsigned long *prate,1144 unsigned long *avgrate)1145{1146 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);1147 struct bcm2835_cprman *cprman = clock->cprman;1148 const struct bcm2835_clock_data *data = clock->data;1149 unsigned long best_rate = 0;1150 u32 curdiv, mindiv, maxdiv;1151 struct clk_hw *parent;1152 1153 parent = clk_hw_get_parent_by_index(hw, parent_idx);1154 1155 if (!(BIT(parent_idx) & data->set_rate_parent)) {1156 *prate = clk_hw_get_rate(parent);1157 *div = bcm2835_clock_choose_div(hw, rate, *prate);1158 1159 *avgrate = bcm2835_clock_rate_from_divisor(clock, *prate, *div);1160 1161 if (data->low_jitter && (*div & CM_DIV_FRAC_MASK)) {1162 unsigned long high, low;1163 u32 int_div = *div & ~CM_DIV_FRAC_MASK;1164 1165 high = bcm2835_clock_rate_from_divisor(clock, *prate,1166 int_div);1167 int_div += CM_DIV_FRAC_MASK + 1;1168 low = bcm2835_clock_rate_from_divisor(clock, *prate,1169 int_div);1170 1171 /*1172 * Return a value which is the maximum deviation1173 * below the ideal rate, for use as a metric.1174 */1175 return *avgrate - max(*avgrate - low, high - *avgrate);1176 }1177 return *avgrate;1178 }1179 1180 if (data->frac_bits)1181 dev_warn(cprman->dev,1182 "frac bits are not used when propagating rate change");1183 1184 /* clamp to min divider of 2 if we're dealing with a mash clock */1185 mindiv = data->is_mash_clock ? 2 : 1;1186 maxdiv = BIT(data->int_bits) - 1;1187 1188 /* TODO: Be smart, and only test a subset of the available divisors. */1189 for (curdiv = mindiv; curdiv <= maxdiv; curdiv++) {1190 unsigned long tmp_rate;1191 1192 tmp_rate = clk_hw_round_rate(parent, rate * curdiv);1193 tmp_rate /= curdiv;1194 if (curdiv == mindiv ||1195 (tmp_rate > best_rate && tmp_rate <= rate))1196 best_rate = tmp_rate;1197 1198 if (best_rate == rate)1199 break;1200 }1201 1202 *div = curdiv << CM_DIV_FRAC_BITS;1203 *prate = curdiv * best_rate;1204 *avgrate = best_rate;1205 1206 return best_rate;1207}1208 1209static int bcm2835_clock_determine_rate(struct clk_hw *hw,1210 struct clk_rate_request *req)1211{1212 struct clk_hw *parent, *best_parent = NULL;1213 bool current_parent_is_pllc;1214 unsigned long rate, best_rate = 0;1215 unsigned long prate, best_prate = 0;1216 unsigned long avgrate, best_avgrate = 0;1217 size_t i;1218 u32 div;1219 1220 current_parent_is_pllc = bcm2835_clk_is_pllc(clk_hw_get_parent(hw));1221 1222 /*1223 * Select parent clock that results in the closest but lower rate1224 */1225 for (i = 0; i < clk_hw_get_num_parents(hw); ++i) {1226 parent = clk_hw_get_parent_by_index(hw, i);1227 if (!parent)1228 continue;1229 1230 /*1231 * Don't choose a PLLC-derived clock as our parent1232 * unless it had been manually set that way. PLLC's1233 * frequency gets adjusted by the firmware due to1234 * over-temp or under-voltage conditions, without1235 * prior notification to our clock consumer.1236 */1237 if (bcm2835_clk_is_pllc(parent) && !current_parent_is_pllc)1238 continue;1239 1240 rate = bcm2835_clock_choose_div_and_prate(hw, i, req->rate,1241 &div, &prate,1242 &avgrate);1243 if (abs(req->rate - rate) < abs(req->rate - best_rate)) {1244 best_parent = parent;1245 best_prate = prate;1246 best_rate = rate;1247 best_avgrate = avgrate;1248 }1249 }1250 1251 if (!best_parent)1252 return -EINVAL;1253 1254 req->best_parent_hw = best_parent;1255 req->best_parent_rate = best_prate;1256 1257 req->rate = best_avgrate;1258 1259 return 0;1260}1261 1262static int bcm2835_clock_set_parent(struct clk_hw *hw, u8 index)1263{1264 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);1265 struct bcm2835_cprman *cprman = clock->cprman;1266 const struct bcm2835_clock_data *data = clock->data;1267 u8 src = (index << CM_SRC_SHIFT) & CM_SRC_MASK;1268 1269 cprman_write(cprman, data->ctl_reg, src);1270 return 0;1271}1272 1273static u8 bcm2835_clock_get_parent(struct clk_hw *hw)1274{1275 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);1276 struct bcm2835_cprman *cprman = clock->cprman;1277 const struct bcm2835_clock_data *data = clock->data;1278 u32 src = cprman_read(cprman, data->ctl_reg);1279 1280 return (src & CM_SRC_MASK) >> CM_SRC_SHIFT;1281}1282 1283static const struct debugfs_reg32 bcm2835_debugfs_clock_reg32[] = {1284 {1285 .name = "ctl",1286 .offset = 0,1287 },1288 {1289 .name = "div",1290 .offset = 4,1291 },1292};1293 1294static void bcm2835_clock_debug_init(struct clk_hw *hw,1295 struct dentry *dentry)1296{1297 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);1298 struct bcm2835_cprman *cprman = clock->cprman;1299 const struct bcm2835_clock_data *data = clock->data;1300 1301 bcm2835_debugfs_regset(cprman, data->ctl_reg,1302 bcm2835_debugfs_clock_reg32,1303 ARRAY_SIZE(bcm2835_debugfs_clock_reg32),1304 dentry);1305}1306 1307static const struct clk_ops bcm2835_clock_clk_ops = {1308 .is_prepared = bcm2835_clock_is_on,1309 .prepare = bcm2835_clock_on,1310 .unprepare = bcm2835_clock_off,1311 .recalc_rate = bcm2835_clock_get_rate,1312 .set_rate = bcm2835_clock_set_rate,1313 .determine_rate = bcm2835_clock_determine_rate,1314 .set_parent = bcm2835_clock_set_parent,1315 .get_parent = bcm2835_clock_get_parent,1316 .debug_init = bcm2835_clock_debug_init,1317};1318 1319static int bcm2835_vpu_clock_is_on(struct clk_hw *hw)1320{1321 return true;1322}1323 1324/*1325 * The VPU clock can never be disabled (it doesn't have an ENABLE1326 * bit), so it gets its own set of clock ops.1327 */1328static const struct clk_ops bcm2835_vpu_clock_clk_ops = {1329 .is_prepared = bcm2835_vpu_clock_is_on,1330 .recalc_rate = bcm2835_clock_get_rate,1331 .set_rate = bcm2835_clock_set_rate,1332 .determine_rate = bcm2835_clock_determine_rate,1333 .set_parent = bcm2835_clock_set_parent,1334 .get_parent = bcm2835_clock_get_parent,1335 .debug_init = bcm2835_clock_debug_init,1336};1337 1338static struct clk_hw *bcm2835_register_pll(struct bcm2835_cprman *cprman,1339 const void *data)1340{1341 const struct bcm2835_pll_data *pll_data = data;1342 struct bcm2835_pll *pll;1343 struct clk_init_data init;1344 int ret;1345 1346 memset(&init, 0, sizeof(init));1347 1348 /* All of the PLLs derive from the external oscillator. */1349 init.parent_names = &cprman->real_parent_names[0];1350 init.num_parents = 1;1351 init.name = pll_data->name;1352 init.ops = &bcm2835_pll_clk_ops;1353 init.flags = pll_data->flags | CLK_IGNORE_UNUSED;1354 1355 pll = kzalloc(sizeof(*pll), GFP_KERNEL);1356 if (!pll)1357 return NULL;1358 1359 pll->cprman = cprman;1360 pll->data = pll_data;1361 pll->hw.init = &init;1362 1363 ret = devm_clk_hw_register(cprman->dev, &pll->hw);1364 if (ret) {1365 kfree(pll);1366 return NULL;1367 }1368 return &pll->hw;1369}1370 1371static struct clk_hw *1372bcm2835_register_pll_divider(struct bcm2835_cprman *cprman,1373 const void *data)1374{1375 const struct bcm2835_pll_divider_data *divider_data = data;1376 struct bcm2835_pll_divider *divider;1377 struct clk_init_data init;1378 const char *divider_name;1379 int ret;1380 1381 if (divider_data->fixed_divider != 1) {1382 divider_name = devm_kasprintf(cprman->dev, GFP_KERNEL,1383 "%s_prediv", divider_data->name);1384 if (!divider_name)1385 return NULL;1386 } else {1387 divider_name = divider_data->name;1388 }1389 1390 memset(&init, 0, sizeof(init));1391 1392 init.parent_names = ÷r_data->source_pll;1393 init.num_parents = 1;1394 init.name = divider_name;1395 init.ops = &bcm2835_pll_divider_clk_ops;1396 init.flags = divider_data->flags | CLK_IGNORE_UNUSED;1397 1398 divider = devm_kzalloc(cprman->dev, sizeof(*divider), GFP_KERNEL);1399 if (!divider)1400 return NULL;1401 1402 divider->div.reg = cprman->regs + divider_data->a2w_reg;1403 divider->div.shift = A2W_PLL_DIV_SHIFT;1404 divider->div.width = A2W_PLL_DIV_BITS;1405 divider->div.flags = CLK_DIVIDER_MAX_AT_ZERO;1406 divider->div.lock = &cprman->regs_lock;1407 divider->div.hw.init = &init;1408 divider->div.table = NULL;1409 1410 divider->cprman = cprman;1411 divider->data = divider_data;1412 1413 ret = devm_clk_hw_register(cprman->dev, ÷r->div.hw);1414 if (ret)1415 return ERR_PTR(ret);1416 1417 /*1418 * PLLH's channels have a fixed divide by 10 afterwards, which1419 * is what our consumers are actually using.1420 */1421 if (divider_data->fixed_divider != 1) {1422 return clk_hw_register_fixed_factor(cprman->dev,1423 divider_data->name,1424 divider_name,1425 CLK_SET_RATE_PARENT,1426 1,1427 divider_data->fixed_divider);1428 }1429 1430 return ÷r->div.hw;1431}1432 1433static struct clk_hw *bcm2835_register_clock(struct bcm2835_cprman *cprman,1434 const void *data)1435{1436 const struct bcm2835_clock_data *clock_data = data;1437 struct bcm2835_clock *clock;1438 struct clk_init_data init;1439 const char *parents[1 << CM_SRC_BITS];1440 size_t i;1441 int ret;1442 1443 /*1444 * Replace our strings referencing parent clocks with the1445 * actual clock-output-name of the parent.1446 */1447 for (i = 0; i < clock_data->num_mux_parents; i++) {1448 parents[i] = clock_data->parents[i];1449 1450 ret = match_string(cprman_parent_names,1451 ARRAY_SIZE(cprman_parent_names),1452 parents[i]);1453 if (ret >= 0)1454 parents[i] = cprman->real_parent_names[ret];1455 }1456 1457 memset(&init, 0, sizeof(init));1458 init.parent_names = parents;1459 init.num_parents = clock_data->num_mux_parents;1460 init.name = clock_data->name;1461 init.flags = clock_data->flags | CLK_IGNORE_UNUSED;1462 1463 /*1464 * Pass the CLK_SET_RATE_PARENT flag if we are allowed to propagate1465 * rate changes on at least of the parents.1466 */1467 if (clock_data->set_rate_parent)1468 init.flags |= CLK_SET_RATE_PARENT;1469 1470 if (clock_data->is_vpu_clock) {1471 init.ops = &bcm2835_vpu_clock_clk_ops;1472 } else {1473 init.ops = &bcm2835_clock_clk_ops;1474 init.flags |= CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE;1475 1476 /* If the clock wasn't actually enabled at boot, it's not1477 * critical.1478 */1479 if (!(cprman_read(cprman, clock_data->ctl_reg) & CM_ENABLE))1480 init.flags &= ~CLK_IS_CRITICAL;1481 }1482 1483 clock = devm_kzalloc(cprman->dev, sizeof(*clock), GFP_KERNEL);1484 if (!clock)1485 return NULL;1486 1487 clock->cprman = cprman;1488 clock->data = clock_data;1489 clock->hw.init = &init;1490 1491 ret = devm_clk_hw_register(cprman->dev, &clock->hw);1492 if (ret)1493 return ERR_PTR(ret);1494 return &clock->hw;1495}1496 1497static struct clk_hw *bcm2835_register_gate(struct bcm2835_cprman *cprman,1498 const void *data)1499{1500 const struct bcm2835_gate_data *gate_data = data;1501 1502 return clk_hw_register_gate(cprman->dev, gate_data->name,1503 gate_data->parent,1504 CLK_IGNORE_UNUSED | CLK_SET_RATE_GATE,1505 cprman->regs + gate_data->ctl_reg,1506 CM_GATE_BIT, 0, &cprman->regs_lock);1507}1508 1509struct bcm2835_clk_desc {1510 struct clk_hw *(*clk_register)(struct bcm2835_cprman *cprman,1511 const void *data);1512 unsigned int supported;1513 const void *data;1514};1515 1516/* assignment helper macros for different clock types */1517#define _REGISTER(f, s, ...) { .clk_register = f, \1518 .supported = s, \1519 .data = __VA_ARGS__ }1520#define REGISTER_PLL(s, ...) _REGISTER(&bcm2835_register_pll, \1521 s, \1522 &(struct bcm2835_pll_data) \1523 {__VA_ARGS__})1524#define REGISTER_PLL_DIV(s, ...) _REGISTER(&bcm2835_register_pll_divider, \1525 s, \1526 &(struct bcm2835_pll_divider_data) \1527 {__VA_ARGS__})1528#define REGISTER_CLK(s, ...) _REGISTER(&bcm2835_register_clock, \1529 s, \1530 &(struct bcm2835_clock_data) \1531 {__VA_ARGS__})1532#define REGISTER_GATE(s, ...) _REGISTER(&bcm2835_register_gate, \1533 s, \1534 &(struct bcm2835_gate_data) \1535 {__VA_ARGS__})1536 1537/* parent mux arrays plus helper macros */1538 1539/* main oscillator parent mux */1540static const char *const bcm2835_clock_osc_parents[] = {1541 "gnd",1542 "xosc",1543 "testdebug0",1544 "testdebug1"1545};1546 1547#define REGISTER_OSC_CLK(s, ...) REGISTER_CLK( \1548 s, \1549 .num_mux_parents = ARRAY_SIZE(bcm2835_clock_osc_parents), \1550 .parents = bcm2835_clock_osc_parents, \1551 __VA_ARGS__)1552 1553/* main peripherial parent mux */1554static const char *const bcm2835_clock_per_parents[] = {1555 "gnd",1556 "xosc",1557 "testdebug0",1558 "testdebug1",1559 "plla_per",1560 "pllc_per",1561 "plld_per",1562 "pllh_aux",1563};1564 1565#define REGISTER_PER_CLK(s, ...) REGISTER_CLK( \1566 s, \1567 .num_mux_parents = ARRAY_SIZE(bcm2835_clock_per_parents), \1568 .parents = bcm2835_clock_per_parents, \1569 __VA_ARGS__)1570 1571/*1572 * Restrict clock sources for the PCM peripheral to the oscillator and1573 * PLLD_PER because other source may have varying rates or be switched1574 * off.1575 *1576 * Prevent other sources from being selected by replacing their names in1577 * the list of potential parents with dummy entries (entry index is1578 * significant).1579 */1580static const char *const bcm2835_pcm_per_parents[] = {1581 "-",1582 "xosc",1583 "-",1584 "-",1585 "-",1586 "-",1587 "plld_per",1588 "-",1589};1590 1591#define REGISTER_PCM_CLK(s, ...) REGISTER_CLK( \1592 s, \1593 .num_mux_parents = ARRAY_SIZE(bcm2835_pcm_per_parents), \1594 .parents = bcm2835_pcm_per_parents, \1595 __VA_ARGS__)1596 1597/* main vpu parent mux */1598static const char *const bcm2835_clock_vpu_parents[] = {1599 "gnd",1600 "xosc",1601 "testdebug0",1602 "testdebug1",1603 "plla_core",1604 "pllc_core0",1605 "plld_core",1606 "pllh_aux",1607 "pllc_core1",1608 "pllc_core2",1609};1610 1611#define REGISTER_VPU_CLK(s, ...) REGISTER_CLK( \1612 s, \1613 .num_mux_parents = ARRAY_SIZE(bcm2835_clock_vpu_parents), \1614 .parents = bcm2835_clock_vpu_parents, \1615 __VA_ARGS__)1616 1617/*1618 * DSI parent clocks. The DSI byte/DDR/DDR2 clocks come from the DSI1619 * analog PHY. The _inv variants are generated internally to cprman,1620 * but we don't use them so they aren't hooked up.1621 */1622static const char *const bcm2835_clock_dsi0_parents[] = {1623 "gnd",1624 "xosc",1625 "testdebug0",1626 "testdebug1",1627 "dsi0_ddr",1628 "dsi0_ddr_inv",1629 "dsi0_ddr2",1630 "dsi0_ddr2_inv",1631 "dsi0_byte",1632 "dsi0_byte_inv",1633};1634 1635static const char *const bcm2835_clock_dsi1_parents[] = {1636 "gnd",1637 "xosc",1638 "testdebug0",1639 "testdebug1",1640 "dsi1_ddr",1641 "dsi1_ddr_inv",1642 "dsi1_ddr2",1643 "dsi1_ddr2_inv",1644 "dsi1_byte",1645 "dsi1_byte_inv",1646};1647 1648#define REGISTER_DSI0_CLK(s, ...) REGISTER_CLK( \1649 s, \1650 .num_mux_parents = ARRAY_SIZE(bcm2835_clock_dsi0_parents), \1651 .parents = bcm2835_clock_dsi0_parents, \1652 __VA_ARGS__)1653 1654#define REGISTER_DSI1_CLK(s, ...) REGISTER_CLK( \1655 s, \1656 .num_mux_parents = ARRAY_SIZE(bcm2835_clock_dsi1_parents), \1657 .parents = bcm2835_clock_dsi1_parents, \1658 __VA_ARGS__)1659 1660/*1661 * the real definition of all the pll, pll_dividers and clocks1662 * these make use of the above REGISTER_* macros1663 */1664static const struct bcm2835_clk_desc clk_desc_array[] = {1665 /* the PLL + PLL dividers */1666 1667 /*1668 * PLLA is the auxiliary PLL, used to drive the CCP21669 * (Compact Camera Port 2) transmitter clock.1670 *1671 * It is in the PX LDO power domain, which is on when the1672 * AUDIO domain is on.1673 */1674 [BCM2835_PLLA] = REGISTER_PLL(1675 SOC_ALL,1676 .name = "plla",1677 .cm_ctrl_reg = CM_PLLA,1678 .a2w_ctrl_reg = A2W_PLLA_CTRL,1679 .frac_reg = A2W_PLLA_FRAC,1680 .ana_reg_base = A2W_PLLA_ANA0,1681 .reference_enable_mask = A2W_XOSC_CTRL_PLLA_ENABLE,1682 .lock_mask = CM_LOCK_FLOCKA,1683 1684 .ana = &bcm2835_ana_default,1685 1686 .min_rate = 600000000u,1687 .max_rate = 2400000000u,1688 .max_fb_rate = BCM2835_MAX_FB_RATE),1689 [BCM2835_PLLA_CORE] = REGISTER_PLL_DIV(1690 SOC_ALL,1691 .name = "plla_core",1692 .source_pll = "plla",1693 .cm_reg = CM_PLLA,1694 .a2w_reg = A2W_PLLA_CORE,1695 .load_mask = CM_PLLA_LOADCORE,1696 .hold_mask = CM_PLLA_HOLDCORE,1697 .fixed_divider = 1,1698 .flags = CLK_SET_RATE_PARENT),1699 [BCM2835_PLLA_PER] = REGISTER_PLL_DIV(1700 SOC_ALL,1701 .name = "plla_per",1702 .source_pll = "plla",1703 .cm_reg = CM_PLLA,1704 .a2w_reg = A2W_PLLA_PER,1705 .load_mask = CM_PLLA_LOADPER,1706 .hold_mask = CM_PLLA_HOLDPER,1707 .fixed_divider = 1,1708 .flags = CLK_SET_RATE_PARENT),1709 [BCM2835_PLLA_DSI0] = REGISTER_PLL_DIV(1710 SOC_ALL,1711 .name = "plla_dsi0",1712 .source_pll = "plla",1713 .cm_reg = CM_PLLA,1714 .a2w_reg = A2W_PLLA_DSI0,1715 .load_mask = CM_PLLA_LOADDSI0,1716 .hold_mask = CM_PLLA_HOLDDSI0,1717 .fixed_divider = 1),1718 [BCM2835_PLLA_CCP2] = REGISTER_PLL_DIV(1719 SOC_ALL,1720 .name = "plla_ccp2",1721 .source_pll = "plla",1722 .cm_reg = CM_PLLA,1723 .a2w_reg = A2W_PLLA_CCP2,1724 .load_mask = CM_PLLA_LOADCCP2,1725 .hold_mask = CM_PLLA_HOLDCCP2,1726 .fixed_divider = 1,1727 .flags = CLK_SET_RATE_PARENT),1728 1729 /* PLLB is used for the ARM's clock. */1730 [BCM2835_PLLB] = REGISTER_PLL(1731 SOC_ALL,1732 .name = "pllb",1733 .cm_ctrl_reg = CM_PLLB,1734 .a2w_ctrl_reg = A2W_PLLB_CTRL,1735 .frac_reg = A2W_PLLB_FRAC,1736 .ana_reg_base = A2W_PLLB_ANA0,1737 .reference_enable_mask = A2W_XOSC_CTRL_PLLB_ENABLE,1738 .lock_mask = CM_LOCK_FLOCKB,1739 1740 .ana = &bcm2835_ana_default,1741 1742 .min_rate = 600000000u,1743 .max_rate = 3000000000u,1744 .max_fb_rate = BCM2835_MAX_FB_RATE,1745 .flags = CLK_GET_RATE_NOCACHE),1746 [BCM2835_PLLB_ARM] = REGISTER_PLL_DIV(1747 SOC_ALL,1748 .name = "pllb_arm",1749 .source_pll = "pllb",1750 .cm_reg = CM_PLLB,1751 .a2w_reg = A2W_PLLB_ARM,1752 .load_mask = CM_PLLB_LOADARM,1753 .hold_mask = CM_PLLB_HOLDARM,1754 .fixed_divider = 1,1755 .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE),1756 1757 /*1758 * PLLC is the core PLL, used to drive the core VPU clock.1759 *1760 * It is in the PX LDO power domain, which is on when the1761 * AUDIO domain is on.1762 */1763 [BCM2835_PLLC] = REGISTER_PLL(1764 SOC_ALL,1765 .name = "pllc",1766 .cm_ctrl_reg = CM_PLLC,1767 .a2w_ctrl_reg = A2W_PLLC_CTRL,1768 .frac_reg = A2W_PLLC_FRAC,1769 .ana_reg_base = A2W_PLLC_ANA0,1770 .reference_enable_mask = A2W_XOSC_CTRL_PLLC_ENABLE,1771 .lock_mask = CM_LOCK_FLOCKC,1772 1773 .ana = &bcm2835_ana_default,1774 1775 .min_rate = 600000000u,1776 .max_rate = 3000000000u,1777 .max_fb_rate = BCM2835_MAX_FB_RATE),1778 [BCM2835_PLLC_CORE0] = REGISTER_PLL_DIV(1779 SOC_ALL,1780 .name = "pllc_core0",1781 .source_pll = "pllc",1782 .cm_reg = CM_PLLC,1783 .a2w_reg = A2W_PLLC_CORE0,1784 .load_mask = CM_PLLC_LOADCORE0,1785 .hold_mask = CM_PLLC_HOLDCORE0,1786 .fixed_divider = 1,1787 .flags = CLK_SET_RATE_PARENT),1788 [BCM2835_PLLC_CORE1] = REGISTER_PLL_DIV(1789 SOC_ALL,1790 .name = "pllc_core1",1791 .source_pll = "pllc",1792 .cm_reg = CM_PLLC,1793 .a2w_reg = A2W_PLLC_CORE1,1794 .load_mask = CM_PLLC_LOADCORE1,1795 .hold_mask = CM_PLLC_HOLDCORE1,1796 .fixed_divider = 1,1797 .flags = CLK_SET_RATE_PARENT),1798 [BCM2835_PLLC_CORE2] = REGISTER_PLL_DIV(1799 SOC_ALL,1800 .name = "pllc_core2",1801 .source_pll = "pllc",1802 .cm_reg = CM_PLLC,1803 .a2w_reg = A2W_PLLC_CORE2,1804 .load_mask = CM_PLLC_LOADCORE2,1805 .hold_mask = CM_PLLC_HOLDCORE2,1806 .fixed_divider = 1,1807 .flags = CLK_SET_RATE_PARENT),1808 [BCM2835_PLLC_PER] = REGISTER_PLL_DIV(1809 SOC_ALL,1810 .name = "pllc_per",1811 .source_pll = "pllc",1812 .cm_reg = CM_PLLC,1813 .a2w_reg = A2W_PLLC_PER,1814 .load_mask = CM_PLLC_LOADPER,1815 .hold_mask = CM_PLLC_HOLDPER,1816 .fixed_divider = 1,1817 .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),1818 1819 /*1820 * PLLD is the display PLL, used to drive DSI display panels.1821 *1822 * It is in the PX LDO power domain, which is on when the1823 * AUDIO domain is on.1824 */1825 [BCM2835_PLLD] = REGISTER_PLL(1826 SOC_ALL,1827 .name = "plld",1828 .cm_ctrl_reg = CM_PLLD,1829 .a2w_ctrl_reg = A2W_PLLD_CTRL,1830 .frac_reg = A2W_PLLD_FRAC,1831 .ana_reg_base = A2W_PLLD_ANA0,1832 .reference_enable_mask = A2W_XOSC_CTRL_DDR_ENABLE,1833 .lock_mask = CM_LOCK_FLOCKD,1834 1835 .ana = &bcm2835_ana_default,1836 1837 .min_rate = 600000000u,1838 .max_rate = 2400000000u,1839 .max_fb_rate = BCM2835_MAX_FB_RATE),1840 [BCM2835_PLLD_CORE] = REGISTER_PLL_DIV(1841 SOC_ALL,1842 .name = "plld_core",1843 .source_pll = "plld",1844 .cm_reg = CM_PLLD,1845 .a2w_reg = A2W_PLLD_CORE,1846 .load_mask = CM_PLLD_LOADCORE,1847 .hold_mask = CM_PLLD_HOLDCORE,1848 .fixed_divider = 1,1849 .flags = CLK_SET_RATE_PARENT),1850 /*1851 * VPU firmware assumes that PLLD_PER isn't disabled by the ARM core.1852 * Otherwise this could cause firmware lookups. That's why we mark1853 * it as critical.1854 */1855 [BCM2835_PLLD_PER] = REGISTER_PLL_DIV(1856 SOC_ALL,1857 .name = "plld_per",1858 .source_pll = "plld",1859 .cm_reg = CM_PLLD,1860 .a2w_reg = A2W_PLLD_PER,1861 .load_mask = CM_PLLD_LOADPER,1862 .hold_mask = CM_PLLD_HOLDPER,1863 .fixed_divider = 1,1864 .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),1865 [BCM2835_PLLD_DSI0] = REGISTER_PLL_DIV(1866 SOC_ALL,1867 .name = "plld_dsi0",1868 .source_pll = "plld",1869 .cm_reg = CM_PLLD,1870 .a2w_reg = A2W_PLLD_DSI0,1871 .load_mask = CM_PLLD_LOADDSI0,1872 .hold_mask = CM_PLLD_HOLDDSI0,1873 .fixed_divider = 1),1874 [BCM2835_PLLD_DSI1] = REGISTER_PLL_DIV(1875 SOC_ALL,1876 .name = "plld_dsi1",1877 .source_pll = "plld",1878 .cm_reg = CM_PLLD,1879 .a2w_reg = A2W_PLLD_DSI1,1880 .load_mask = CM_PLLD_LOADDSI1,1881 .hold_mask = CM_PLLD_HOLDDSI1,1882 .fixed_divider = 1),1883 1884 /*1885 * PLLH is used to supply the pixel clock or the AUX clock for the1886 * TV encoder.1887 *1888 * It is in the HDMI power domain.1889 */1890 [BCM2835_PLLH] = REGISTER_PLL(1891 SOC_BCM2835,1892 "pllh",1893 .cm_ctrl_reg = CM_PLLH,1894 .a2w_ctrl_reg = A2W_PLLH_CTRL,1895 .frac_reg = A2W_PLLH_FRAC,1896 .ana_reg_base = A2W_PLLH_ANA0,1897 .reference_enable_mask = A2W_XOSC_CTRL_PLLC_ENABLE,1898 .lock_mask = CM_LOCK_FLOCKH,1899 1900 .ana = &bcm2835_ana_pllh,1901 1902 .min_rate = 600000000u,1903 .max_rate = 3000000000u,1904 .max_fb_rate = BCM2835_MAX_FB_RATE),1905 [BCM2835_PLLH_RCAL] = REGISTER_PLL_DIV(1906 SOC_BCM2835,1907 .name = "pllh_rcal",1908 .source_pll = "pllh",1909 .cm_reg = CM_PLLH,1910 .a2w_reg = A2W_PLLH_RCAL,1911 .load_mask = CM_PLLH_LOADRCAL,1912 .hold_mask = 0,1913 .fixed_divider = 10,1914 .flags = CLK_SET_RATE_PARENT),1915 [BCM2835_PLLH_AUX] = REGISTER_PLL_DIV(1916 SOC_BCM2835,1917 .name = "pllh_aux",1918 .source_pll = "pllh",1919 .cm_reg = CM_PLLH,1920 .a2w_reg = A2W_PLLH_AUX,1921 .load_mask = CM_PLLH_LOADAUX,1922 .hold_mask = 0,1923 .fixed_divider = 1,1924 .flags = CLK_SET_RATE_PARENT),1925 [BCM2835_PLLH_PIX] = REGISTER_PLL_DIV(1926 SOC_BCM2835,1927 .name = "pllh_pix",1928 .source_pll = "pllh",1929 .cm_reg = CM_PLLH,1930 .a2w_reg = A2W_PLLH_PIX,1931 .load_mask = CM_PLLH_LOADPIX,1932 .hold_mask = 0,1933 .fixed_divider = 10,1934 .flags = CLK_SET_RATE_PARENT),1935 1936 /* the clocks */1937 1938 /* clocks with oscillator parent mux */1939 1940 /* One Time Programmable Memory clock. Maximum 10Mhz. */1941 [BCM2835_CLOCK_OTP] = REGISTER_OSC_CLK(1942 SOC_ALL,1943 .name = "otp",1944 .ctl_reg = CM_OTPCTL,1945 .div_reg = CM_OTPDIV,1946 .int_bits = 4,1947 .frac_bits = 0,1948 .tcnt_mux = 6),1949 /*1950 * Used for a 1Mhz clock for the system clocksource, and also used1951 * bythe watchdog timer and the camera pulse generator.1952 */1953 [BCM2835_CLOCK_TIMER] = REGISTER_OSC_CLK(1954 SOC_ALL,1955 .name = "timer",1956 .ctl_reg = CM_TIMERCTL,1957 .div_reg = CM_TIMERDIV,1958 .int_bits = 6,1959 .frac_bits = 12),1960 /*1961 * Clock for the temperature sensor.1962 * Generally run at 2Mhz, max 5Mhz.1963 */1964 [BCM2835_CLOCK_TSENS] = REGISTER_OSC_CLK(1965 SOC_ALL,1966 .name = "tsens",1967 .ctl_reg = CM_TSENSCTL,1968 .div_reg = CM_TSENSDIV,1969 .int_bits = 5,1970 .frac_bits = 0),1971 [BCM2835_CLOCK_TEC] = REGISTER_OSC_CLK(1972 SOC_ALL,1973 .name = "tec",1974 .ctl_reg = CM_TECCTL,1975 .div_reg = CM_TECDIV,1976 .int_bits = 6,1977 .frac_bits = 0),1978 1979 /* clocks with vpu parent mux */1980 [BCM2835_CLOCK_H264] = REGISTER_VPU_CLK(1981 SOC_ALL,1982 .name = "h264",1983 .ctl_reg = CM_H264CTL,1984 .div_reg = CM_H264DIV,1985 .int_bits = 4,1986 .frac_bits = 8,1987 .tcnt_mux = 1),1988 [BCM2835_CLOCK_ISP] = REGISTER_VPU_CLK(1989 SOC_ALL,1990 .name = "isp",1991 .ctl_reg = CM_ISPCTL,1992 .div_reg = CM_ISPDIV,1993 .int_bits = 4,1994 .frac_bits = 8,1995 .tcnt_mux = 2),1996 1997 /*1998 * Secondary SDRAM clock. Used for low-voltage modes when the PLL1999 * in the SDRAM controller can't be used.2000 */2001 [BCM2835_CLOCK_SDRAM] = REGISTER_VPU_CLK(2002 SOC_ALL,2003 .name = "sdram",2004 .ctl_reg = CM_SDCCTL,2005 .div_reg = CM_SDCDIV,2006 .int_bits = 6,2007 .frac_bits = 0,2008 .tcnt_mux = 3),2009 [BCM2835_CLOCK_V3D] = REGISTER_VPU_CLK(2010 SOC_ALL,2011 .name = "v3d",2012 .ctl_reg = CM_V3DCTL,2013 .div_reg = CM_V3DDIV,2014 .int_bits = 4,2015 .frac_bits = 8,2016 .tcnt_mux = 4),2017 /*2018 * VPU clock. This doesn't have an enable bit, since it drives2019 * the bus for everything else, and is special so it doesn't need2020 * to be gated for rate changes. It is also known as "clk_audio"2021 * in various hardware documentation.2022 */2023 [BCM2835_CLOCK_VPU] = REGISTER_VPU_CLK(2024 SOC_ALL,2025 .name = "vpu",2026 .ctl_reg = CM_VPUCTL,2027 .div_reg = CM_VPUDIV,2028 .int_bits = 12,2029 .frac_bits = 8,2030 .flags = CLK_IS_CRITICAL,2031 .is_vpu_clock = true,2032 .tcnt_mux = 5),2033 2034 /* clocks with per parent mux */2035 [BCM2835_CLOCK_AVEO] = REGISTER_PER_CLK(2036 SOC_ALL,2037 .name = "aveo",2038 .ctl_reg = CM_AVEOCTL,2039 .div_reg = CM_AVEODIV,2040 .int_bits = 4,2041 .frac_bits = 0,2042 .tcnt_mux = 38),2043 [BCM2835_CLOCK_CAM0] = REGISTER_PER_CLK(2044 SOC_ALL,2045 .name = "cam0",2046 .ctl_reg = CM_CAM0CTL,2047 .div_reg = CM_CAM0DIV,2048 .int_bits = 4,2049 .frac_bits = 8,2050 .tcnt_mux = 14),2051 [BCM2835_CLOCK_CAM1] = REGISTER_PER_CLK(2052 SOC_ALL,2053 .name = "cam1",2054 .ctl_reg = CM_CAM1CTL,2055 .div_reg = CM_CAM1DIV,2056 .int_bits = 4,2057 .frac_bits = 8,2058 .tcnt_mux = 15),2059 [BCM2835_CLOCK_DFT] = REGISTER_PER_CLK(2060 SOC_ALL,2061 .name = "dft",2062 .ctl_reg = CM_DFTCTL,2063 .div_reg = CM_DFTDIV,2064 .int_bits = 5,2065 .frac_bits = 0),2066 [BCM2835_CLOCK_DPI] = REGISTER_PER_CLK(2067 SOC_ALL,2068 .name = "dpi",2069 .ctl_reg = CM_DPICTL,2070 .div_reg = CM_DPIDIV,2071 .int_bits = 4,2072 .frac_bits = 8,2073 .tcnt_mux = 17),2074 2075 /* Arasan EMMC clock */2076 [BCM2835_CLOCK_EMMC] = REGISTER_PER_CLK(2077 SOC_ALL,2078 .name = "emmc",2079 .ctl_reg = CM_EMMCCTL,2080 .div_reg = CM_EMMCDIV,2081 .int_bits = 4,2082 .frac_bits = 8,2083 .tcnt_mux = 39),2084 2085 /* EMMC2 clock (only available for BCM2711) */2086 [BCM2711_CLOCK_EMMC2] = REGISTER_PER_CLK(2087 SOC_BCM2711,2088 .name = "emmc2",2089 .ctl_reg = CM_EMMC2CTL,2090 .div_reg = CM_EMMC2DIV,2091 .int_bits = 4,2092 .frac_bits = 8,2093 .tcnt_mux = 42),2094 2095 /* General purpose (GPIO) clocks */2096 [BCM2835_CLOCK_GP0] = REGISTER_PER_CLK(2097 SOC_ALL,2098 .name = "gp0",2099 .ctl_reg = CM_GP0CTL,2100 .div_reg = CM_GP0DIV,2101 .int_bits = 12,2102 .frac_bits = 12,2103 .is_mash_clock = true,2104 .tcnt_mux = 20),2105 [BCM2835_CLOCK_GP1] = REGISTER_PER_CLK(2106 SOC_ALL,2107 .name = "gp1",2108 .ctl_reg = CM_GP1CTL,2109 .div_reg = CM_GP1DIV,2110 .int_bits = 12,2111 .frac_bits = 12,2112 .flags = CLK_IS_CRITICAL,2113 .is_mash_clock = true,2114 .tcnt_mux = 21),2115 [BCM2835_CLOCK_GP2] = REGISTER_PER_CLK(2116 SOC_ALL,2117 .name = "gp2",2118 .ctl_reg = CM_GP2CTL,2119 .div_reg = CM_GP2DIV,2120 .int_bits = 12,2121 .frac_bits = 12,2122 .flags = CLK_IS_CRITICAL),2123 2124 /* HDMI state machine */2125 [BCM2835_CLOCK_HSM] = REGISTER_PER_CLK(2126 SOC_ALL,2127 .name = "hsm",2128 .ctl_reg = CM_HSMCTL,2129 .div_reg = CM_HSMDIV,2130 .int_bits = 4,2131 .frac_bits = 8,2132 .tcnt_mux = 22),2133 [BCM2835_CLOCK_PCM] = REGISTER_PCM_CLK(2134 SOC_ALL,2135 .name = "pcm",2136 .ctl_reg = CM_PCMCTL,2137 .div_reg = CM_PCMDIV,2138 .int_bits = 12,2139 .frac_bits = 12,2140 .is_mash_clock = true,2141 .low_jitter = true,2142 .tcnt_mux = 23),2143 [BCM2835_CLOCK_PWM] = REGISTER_PER_CLK(2144 SOC_ALL,2145 .name = "pwm",2146 .ctl_reg = CM_PWMCTL,2147 .div_reg = CM_PWMDIV,2148 .int_bits = 12,2149 .frac_bits = 12,2150 .is_mash_clock = true,2151 .tcnt_mux = 24),2152 [BCM2835_CLOCK_SLIM] = REGISTER_PER_CLK(2153 SOC_ALL,2154 .name = "slim",2155 .ctl_reg = CM_SLIMCTL,2156 .div_reg = CM_SLIMDIV,2157 .int_bits = 12,2158 .frac_bits = 12,2159 .is_mash_clock = true,2160 .tcnt_mux = 25),2161 [BCM2835_CLOCK_SMI] = REGISTER_PER_CLK(2162 SOC_ALL,2163 .name = "smi",2164 .ctl_reg = CM_SMICTL,2165 .div_reg = CM_SMIDIV,2166 .int_bits = 4,2167 .frac_bits = 8,2168 .tcnt_mux = 27),2169 [BCM2835_CLOCK_UART] = REGISTER_PER_CLK(2170 SOC_ALL,2171 .name = "uart",2172 .ctl_reg = CM_UARTCTL,2173 .div_reg = CM_UARTDIV,2174 .int_bits = 10,2175 .frac_bits = 12,2176 .tcnt_mux = 28,2177 .round_up = true),2178 2179 /* TV encoder clock. Only operating frequency is 108Mhz. */2180 [BCM2835_CLOCK_VEC] = REGISTER_PER_CLK(2181 SOC_ALL,2182 .name = "vec",2183 .ctl_reg = CM_VECCTL,2184 .div_reg = CM_VECDIV,2185 .int_bits = 4,2186 .frac_bits = 0,2187 /*2188 * Allow rate change propagation only on PLLH_AUX which is2189 * assigned index 7 in the parent array.2190 */2191 .set_rate_parent = BIT(7),2192 .tcnt_mux = 29),2193 2194 /* dsi clocks */2195 [BCM2835_CLOCK_DSI0E] = REGISTER_PER_CLK(2196 SOC_ALL,2197 .name = "dsi0e",2198 .ctl_reg = CM_DSI0ECTL,2199 .div_reg = CM_DSI0EDIV,2200 .int_bits = 4,2201 .frac_bits = 8,2202 .tcnt_mux = 18),2203 [BCM2835_CLOCK_DSI1E] = REGISTER_PER_CLK(2204 SOC_ALL,2205 .name = "dsi1e",2206 .ctl_reg = CM_DSI1ECTL,2207 .div_reg = CM_DSI1EDIV,2208 .int_bits = 4,2209 .frac_bits = 8,2210 .tcnt_mux = 19),2211 [BCM2835_CLOCK_DSI0P] = REGISTER_DSI0_CLK(2212 SOC_ALL,2213 .name = "dsi0p",2214 .ctl_reg = CM_DSI0PCTL,2215 .div_reg = CM_DSI0PDIV,2216 .int_bits = 0,2217 .frac_bits = 0,2218 .tcnt_mux = 12),2219 [BCM2835_CLOCK_DSI1P] = REGISTER_DSI1_CLK(2220 SOC_ALL,2221 .name = "dsi1p",2222 .ctl_reg = CM_DSI1PCTL,2223 .div_reg = CM_DSI1PDIV,2224 .int_bits = 0,2225 .frac_bits = 0,2226 .tcnt_mux = 13),2227 2228 /* the gates */2229 2230 /*2231 * CM_PERIICTL (and CM_PERIACTL, CM_SYSCTL and CM_VPUCTL if2232 * you have the debug bit set in the power manager, which we2233 * don't bother exposing) are individual gates off of the2234 * non-stop vpu clock.2235 */2236 [BCM2835_CLOCK_PERI_IMAGE] = REGISTER_GATE(2237 SOC_ALL,2238 .name = "peri_image",2239 .parent = "vpu",2240 .ctl_reg = CM_PERIICTL),2241};2242 2243/*2244 * Permanently take a reference on the parent of the SDRAM clock.2245 *2246 * While the SDRAM is being driven by its dedicated PLL most of the2247 * time, there is a little loop running in the firmware that2248 * periodically switches the SDRAM to using our CM clock to do PVT2249 * recalibration, with the assumption that the previously configured2250 * SDRAM parent is still enabled and running.2251 */2252static int bcm2835_mark_sdc_parent_critical(struct clk *sdc)2253{2254 struct clk *parent = clk_get_parent(sdc);2255 2256 if (IS_ERR(parent))2257 return PTR_ERR(parent);2258 2259 return clk_prepare_enable(parent);2260}2261 2262static int bcm2835_clk_probe(struct platform_device *pdev)2263{2264 struct device *dev = &pdev->dev;2265 struct clk_hw **hws;2266 struct bcm2835_cprman *cprman;2267 const struct bcm2835_clk_desc *desc;2268 const size_t asize = ARRAY_SIZE(clk_desc_array);2269 const struct cprman_plat_data *pdata;2270 size_t i;2271 int ret;2272 2273 pdata = of_device_get_match_data(&pdev->dev);2274 if (!pdata)2275 return -ENODEV;2276 2277 cprman = devm_kzalloc(dev,2278 struct_size(cprman, onecell.hws, asize),2279 GFP_KERNEL);2280 if (!cprman)2281 return -ENOMEM;2282 2283 spin_lock_init(&cprman->regs_lock);2284 cprman->dev = dev;2285 cprman->regs = devm_platform_ioremap_resource(pdev, 0);2286 if (IS_ERR(cprman->regs))2287 return PTR_ERR(cprman->regs);2288 2289 memcpy(cprman->real_parent_names, cprman_parent_names,2290 sizeof(cprman_parent_names));2291 of_clk_parent_fill(dev->of_node, cprman->real_parent_names,2292 ARRAY_SIZE(cprman_parent_names));2293 2294 /*2295 * Make sure the external oscillator has been registered.2296 *2297 * The other (DSI) clocks are not present on older device2298 * trees, which we still need to support for backwards2299 * compatibility.2300 */2301 if (!cprman->real_parent_names[0])2302 return -ENODEV;2303 2304 platform_set_drvdata(pdev, cprman);2305 2306 cprman->onecell.num = asize;2307 cprman->soc = pdata->soc;2308 hws = cprman->onecell.hws;2309 2310 for (i = 0; i < asize; i++) {2311 desc = &clk_desc_array[i];2312 if (desc->clk_register && desc->data &&2313 (desc->supported & pdata->soc)) {2314 hws[i] = desc->clk_register(cprman, desc->data);2315 }2316 }2317 2318 ret = bcm2835_mark_sdc_parent_critical(hws[BCM2835_CLOCK_SDRAM]->clk);2319 if (ret)2320 return ret;2321 2322 return of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get,2323 &cprman->onecell);2324}2325 2326static const struct cprman_plat_data cprman_bcm2835_plat_data = {2327 .soc = SOC_BCM2835,2328};2329 2330static const struct cprman_plat_data cprman_bcm2711_plat_data = {2331 .soc = SOC_BCM2711,2332};2333 2334static const struct of_device_id bcm2835_clk_of_match[] = {2335 { .compatible = "brcm,bcm2835-cprman", .data = &cprman_bcm2835_plat_data },2336 { .compatible = "brcm,bcm2711-cprman", .data = &cprman_bcm2711_plat_data },2337 {}2338};2339MODULE_DEVICE_TABLE(of, bcm2835_clk_of_match);2340 2341static struct platform_driver bcm2835_clk_driver = {2342 .driver = {2343 .name = "bcm2835-clk",2344 .of_match_table = bcm2835_clk_of_match,2345 },2346 .probe = bcm2835_clk_probe,2347};2348 2349builtin_platform_driver(bcm2835_clk_driver);2350 2351MODULE_AUTHOR("Eric Anholt <eric@anholt.net>");2352MODULE_DESCRIPTION("BCM2835 clock driver");2353