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1// SPDX-License-Identifier: GPL-2.02/*3 * Cortina Gemini SoC Clock Controller driver4 * Copyright (c) 2017 Linus Walleij <linus.walleij@linaro.org>5 */6 7#define pr_fmt(fmt) "clk-gemini: " fmt8 9#include <linux/init.h>10#include <linux/module.h>11#include <linux/platform_device.h>12#include <linux/slab.h>13#include <linux/err.h>14#include <linux/io.h>15#include <linux/clk-provider.h>16#include <linux/of.h>17#include <linux/of_address.h>18#include <linux/mfd/syscon.h>19#include <linux/regmap.h>20#include <linux/spinlock.h>21#include <linux/reset-controller.h>22#include <dt-bindings/reset/cortina,gemini-reset.h>23#include <dt-bindings/clock/cortina,gemini-clock.h>24 25/* Globally visible clocks */26static DEFINE_SPINLOCK(gemini_clk_lock);27 28#define GEMINI_GLOBAL_STATUS 0x0429#define PLL_OSC_SEL BIT(30)30#define AHBSPEED_SHIFT (15)31#define AHBSPEED_MASK 0x0732#define CPU_AHB_RATIO_SHIFT (18)33#define CPU_AHB_RATIO_MASK 0x0334 35#define GEMINI_GLOBAL_PLL_CONTROL 0x0836 37#define GEMINI_GLOBAL_SOFT_RESET 0x0c38 39#define GEMINI_GLOBAL_MISC_CONTROL 0x3040#define PCI_CLK_66MHZ BIT(18)41 42#define GEMINI_GLOBAL_CLOCK_CONTROL 0x3443#define PCI_CLKRUN_EN BIT(16)44#define TVC_HALFDIV_SHIFT (24)45#define TVC_HALFDIV_MASK 0x1f46#define SECURITY_CLK_SEL BIT(29)47 48#define GEMINI_GLOBAL_PCI_DLL_CONTROL 0x4449#define PCI_DLL_BYPASS BIT(31)50#define PCI_DLL_TAP_SEL_MASK 0x1f51 52/**53 * struct gemini_gate_data - Gemini gated clocks54 * @bit_idx: the bit used to gate this clock in the clock register55 * @name: the clock name56 * @parent_name: the name of the parent clock57 * @flags: standard clock framework flags58 */59struct gemini_gate_data {60 u8 bit_idx;61 const char *name;62 const char *parent_name;63 unsigned long flags;64};65 66/**67 * struct clk_gemini_pci - Gemini PCI clock68 * @hw: corresponding clock hardware entry69 * @map: regmap to access the registers70 */71struct clk_gemini_pci {72 struct clk_hw hw;73 struct regmap *map;74};75 76/**77 * struct gemini_reset - gemini reset controller78 * @map: regmap to access the containing system controller79 * @rcdev: reset controller device80 */81struct gemini_reset {82 struct regmap *map;83 struct reset_controller_dev rcdev;84};85 86/* Keeps track of all clocks */87static struct clk_hw_onecell_data *gemini_clk_data;88 89static const struct gemini_gate_data gemini_gates[] = {90 { 1, "security-gate", "secdiv", 0 },91 { 2, "gmac0-gate", "ahb", 0 },92 { 3, "gmac1-gate", "ahb", 0 },93 { 4, "sata0-gate", "ahb", 0 },94 { 5, "sata1-gate", "ahb", 0 },95 { 6, "usb0-gate", "ahb", 0 },96 { 7, "usb1-gate", "ahb", 0 },97 { 8, "ide-gate", "ahb", 0 },98 { 9, "pci-gate", "ahb", 0 },99 /*100 * The DDR controller may never have a driver, but certainly must101 * not be gated off.102 */103 { 10, "ddr-gate", "ahb", CLK_IS_CRITICAL },104 /*105 * The flash controller must be on to access NOR flash through the106 * memory map.107 */108 { 11, "flash-gate", "ahb", CLK_IGNORE_UNUSED },109 { 12, "tvc-gate", "ahb", 0 },110 { 13, "boot-gate", "apb", 0 },111};112 113#define to_pciclk(_hw) container_of(_hw, struct clk_gemini_pci, hw)114 115#define to_gemini_reset(p) container_of((p), struct gemini_reset, rcdev)116 117static unsigned long gemini_pci_recalc_rate(struct clk_hw *hw,118 unsigned long parent_rate)119{120 struct clk_gemini_pci *pciclk = to_pciclk(hw);121 u32 val;122 123 regmap_read(pciclk->map, GEMINI_GLOBAL_MISC_CONTROL, &val);124 if (val & PCI_CLK_66MHZ)125 return 66000000;126 return 33000000;127}128 129static long gemini_pci_round_rate(struct clk_hw *hw, unsigned long rate,130 unsigned long *prate)131{132 /* We support 33 and 66 MHz */133 if (rate < 48000000)134 return 33000000;135 return 66000000;136}137 138static int gemini_pci_set_rate(struct clk_hw *hw, unsigned long rate,139 unsigned long parent_rate)140{141 struct clk_gemini_pci *pciclk = to_pciclk(hw);142 143 if (rate == 33000000)144 return regmap_update_bits(pciclk->map,145 GEMINI_GLOBAL_MISC_CONTROL,146 PCI_CLK_66MHZ, 0);147 if (rate == 66000000)148 return regmap_update_bits(pciclk->map,149 GEMINI_GLOBAL_MISC_CONTROL,150 0, PCI_CLK_66MHZ);151 return -EINVAL;152}153 154static int gemini_pci_enable(struct clk_hw *hw)155{156 struct clk_gemini_pci *pciclk = to_pciclk(hw);157 158 regmap_update_bits(pciclk->map, GEMINI_GLOBAL_CLOCK_CONTROL,159 0, PCI_CLKRUN_EN);160 return 0;161}162 163static void gemini_pci_disable(struct clk_hw *hw)164{165 struct clk_gemini_pci *pciclk = to_pciclk(hw);166 167 regmap_update_bits(pciclk->map, GEMINI_GLOBAL_CLOCK_CONTROL,168 PCI_CLKRUN_EN, 0);169}170 171static int gemini_pci_is_enabled(struct clk_hw *hw)172{173 struct clk_gemini_pci *pciclk = to_pciclk(hw);174 unsigned int val;175 176 regmap_read(pciclk->map, GEMINI_GLOBAL_CLOCK_CONTROL, &val);177 return !!(val & PCI_CLKRUN_EN);178}179 180static const struct clk_ops gemini_pci_clk_ops = {181 .recalc_rate = gemini_pci_recalc_rate,182 .round_rate = gemini_pci_round_rate,183 .set_rate = gemini_pci_set_rate,184 .enable = gemini_pci_enable,185 .disable = gemini_pci_disable,186 .is_enabled = gemini_pci_is_enabled,187};188 189static struct clk_hw *gemini_pci_clk_setup(const char *name,190 const char *parent_name,191 struct regmap *map)192{193 struct clk_gemini_pci *pciclk;194 struct clk_init_data init;195 int ret;196 197 pciclk = kzalloc(sizeof(*pciclk), GFP_KERNEL);198 if (!pciclk)199 return ERR_PTR(-ENOMEM);200 201 init.name = name;202 init.ops = &gemini_pci_clk_ops;203 init.flags = 0;204 init.parent_names = &parent_name;205 init.num_parents = 1;206 pciclk->map = map;207 pciclk->hw.init = &init;208 209 ret = clk_hw_register(NULL, &pciclk->hw);210 if (ret) {211 kfree(pciclk);212 return ERR_PTR(ret);213 }214 215 return &pciclk->hw;216}217 218/*219 * This is a self-deasserting reset controller.220 */221static int gemini_reset(struct reset_controller_dev *rcdev,222 unsigned long id)223{224 struct gemini_reset *gr = to_gemini_reset(rcdev);225 226 /* Manual says to always set BIT 30 (CPU1) to 1 */227 return regmap_write(gr->map,228 GEMINI_GLOBAL_SOFT_RESET,229 BIT(GEMINI_RESET_CPU1) | BIT(id));230}231 232static int gemini_reset_assert(struct reset_controller_dev *rcdev,233 unsigned long id)234{235 return 0;236}237 238static int gemini_reset_deassert(struct reset_controller_dev *rcdev,239 unsigned long id)240{241 return 0;242}243 244static int gemini_reset_status(struct reset_controller_dev *rcdev,245 unsigned long id)246{247 struct gemini_reset *gr = to_gemini_reset(rcdev);248 u32 val;249 int ret;250 251 ret = regmap_read(gr->map, GEMINI_GLOBAL_SOFT_RESET, &val);252 if (ret)253 return ret;254 255 return !!(val & BIT(id));256}257 258static const struct reset_control_ops gemini_reset_ops = {259 .reset = gemini_reset,260 .assert = gemini_reset_assert,261 .deassert = gemini_reset_deassert,262 .status = gemini_reset_status,263};264 265static int gemini_clk_probe(struct platform_device *pdev)266{267 /* Gives the fracions 1x, 1.5x, 1.85x and 2x */268 unsigned int cpu_ahb_mult[4] = { 1, 3, 24, 2 };269 unsigned int cpu_ahb_div[4] = { 1, 2, 13, 1 };270 void __iomem *base;271 struct gemini_reset *gr;272 struct regmap *map;273 struct clk_hw *hw;274 struct device *dev = &pdev->dev;275 struct device_node *np = dev->of_node;276 unsigned int mult, div;277 u32 val;278 int ret;279 int i;280 281 gr = devm_kzalloc(dev, sizeof(*gr), GFP_KERNEL);282 if (!gr)283 return -ENOMEM;284 285 /* Remap the system controller for the exclusive register */286 base = devm_platform_ioremap_resource(pdev, 0);287 if (IS_ERR(base))288 return PTR_ERR(base);289 290 map = syscon_node_to_regmap(np);291 if (IS_ERR(map)) {292 dev_err(dev, "no syscon regmap\n");293 return PTR_ERR(map);294 }295 296 gr->map = map;297 gr->rcdev.owner = THIS_MODULE;298 gr->rcdev.nr_resets = 32;299 gr->rcdev.ops = &gemini_reset_ops;300 gr->rcdev.of_node = np;301 302 ret = devm_reset_controller_register(dev, &gr->rcdev);303 if (ret) {304 dev_err(dev, "could not register reset controller\n");305 return ret;306 }307 308 /* RTC clock 32768 Hz */309 hw = clk_hw_register_fixed_rate(NULL, "rtc", NULL, 0, 32768);310 gemini_clk_data->hws[GEMINI_CLK_RTC] = hw;311 312 /* CPU clock derived as a fixed ratio from the AHB clock */313 regmap_read(map, GEMINI_GLOBAL_STATUS, &val);314 val >>= CPU_AHB_RATIO_SHIFT;315 val &= CPU_AHB_RATIO_MASK;316 hw = clk_hw_register_fixed_factor(NULL, "cpu", "ahb", 0,317 cpu_ahb_mult[val],318 cpu_ahb_div[val]);319 gemini_clk_data->hws[GEMINI_CLK_CPU] = hw;320 321 /* Security clock is 1:1 or 0.75 of APB */322 regmap_read(map, GEMINI_GLOBAL_CLOCK_CONTROL, &val);323 if (val & SECURITY_CLK_SEL) {324 mult = 1;325 div = 1;326 } else {327 mult = 3;328 div = 4;329 }330 hw = clk_hw_register_fixed_factor(NULL, "secdiv", "ahb", 0, mult, div);331 332 /*333 * These are the leaf gates, at boot no clocks are gated.334 */335 for (i = 0; i < ARRAY_SIZE(gemini_gates); i++) {336 const struct gemini_gate_data *gd;337 338 gd = &gemini_gates[i];339 gemini_clk_data->hws[GEMINI_CLK_GATES + i] =340 clk_hw_register_gate(NULL, gd->name,341 gd->parent_name,342 gd->flags,343 base + GEMINI_GLOBAL_CLOCK_CONTROL,344 gd->bit_idx,345 CLK_GATE_SET_TO_DISABLE,346 &gemini_clk_lock);347 }348 349 /*350 * The TV Interface Controller has a 5-bit half divider register.351 * This clock is supposed to be 27MHz as this is an exact multiple352 * of PAL and NTSC frequencies. The register is undocumented :(353 * FIXME: figure out the parent and how the divider works.354 */355 mult = 1;356 div = ((val >> TVC_HALFDIV_SHIFT) & TVC_HALFDIV_MASK);357 dev_dbg(dev, "TVC half divider value = %d\n", div);358 div += 1;359 hw = clk_hw_register_fixed_rate(NULL, "tvcdiv", "xtal", 0, 27000000);360 gemini_clk_data->hws[GEMINI_CLK_TVC] = hw;361 362 /* FIXME: very unclear what the parent is */363 hw = gemini_pci_clk_setup("PCI", "xtal", map);364 gemini_clk_data->hws[GEMINI_CLK_PCI] = hw;365 366 /* FIXME: very unclear what the parent is */367 hw = clk_hw_register_fixed_rate(NULL, "uart", "xtal", 0, 48000000);368 gemini_clk_data->hws[GEMINI_CLK_UART] = hw;369 370 return 0;371}372 373static const struct of_device_id gemini_clk_dt_ids[] = {374 { .compatible = "cortina,gemini-syscon", },375 { /* sentinel */ },376};377 378static struct platform_driver gemini_clk_driver = {379 .probe = gemini_clk_probe,380 .driver = {381 .name = "gemini-clk",382 .of_match_table = gemini_clk_dt_ids,383 .suppress_bind_attrs = true,384 },385};386builtin_platform_driver(gemini_clk_driver);387 388static void __init gemini_cc_init(struct device_node *np)389{390 struct regmap *map;391 struct clk_hw *hw;392 unsigned long freq;393 unsigned int mult, div;394 u32 val;395 int ret;396 int i;397 398 gemini_clk_data = kzalloc(struct_size(gemini_clk_data, hws,399 GEMINI_NUM_CLKS),400 GFP_KERNEL);401 if (!gemini_clk_data)402 return;403 gemini_clk_data->num = GEMINI_NUM_CLKS;404 405 /*406 * This way all clock fetched before the platform device probes,407 * except those we assign here for early use, will be deferred.408 */409 for (i = 0; i < GEMINI_NUM_CLKS; i++)410 gemini_clk_data->hws[i] = ERR_PTR(-EPROBE_DEFER);411 412 map = syscon_node_to_regmap(np);413 if (IS_ERR(map)) {414 pr_err("no syscon regmap\n");415 return;416 }417 /*418 * We check that the regmap works on this very first access,419 * but as this is an MMIO-backed regmap, subsequent regmap420 * access is not going to fail and we skip error checks from421 * this point.422 */423 ret = regmap_read(map, GEMINI_GLOBAL_STATUS, &val);424 if (ret) {425 pr_err("failed to read global status register\n");426 return;427 }428 429 /*430 * XTAL is the crystal oscillator, 60 or 30 MHz selected from431 * strap pin E6432 */433 if (val & PLL_OSC_SEL)434 freq = 30000000;435 else436 freq = 60000000;437 hw = clk_hw_register_fixed_rate(NULL, "xtal", NULL, 0, freq);438 pr_debug("main crystal @%lu MHz\n", freq / 1000000);439 440 /* VCO clock derived from the crystal */441 mult = 13 + ((val >> AHBSPEED_SHIFT) & AHBSPEED_MASK);442 div = 2;443 /* If we run on 30 MHz crystal we have to multiply with two */444 if (val & PLL_OSC_SEL)445 mult *= 2;446 hw = clk_hw_register_fixed_factor(NULL, "vco", "xtal", 0, mult, div);447 448 /* The AHB clock is always 1/3 of the VCO */449 hw = clk_hw_register_fixed_factor(NULL, "ahb", "vco", 0, 1, 3);450 gemini_clk_data->hws[GEMINI_CLK_AHB] = hw;451 452 /* The APB clock is always 1/6 of the AHB */453 hw = clk_hw_register_fixed_factor(NULL, "apb", "ahb", 0, 1, 6);454 gemini_clk_data->hws[GEMINI_CLK_APB] = hw;455 456 /* Register the clocks to be accessed by the device tree */457 of_clk_add_hw_provider(np, of_clk_hw_onecell_get, gemini_clk_data);458}459CLK_OF_DECLARE_DRIVER(gemini_cc, "cortina,gemini-syscon", gemini_cc_init);460