387 lines · c
1// SPDX-License-Identifier: GPL-2.02 3#include <linux/module.h>4#include <linux/kernel.h>5#include <linux/clk.h>6#include <linux/clk-provider.h>7#include <linux/err.h>8#include <linux/errno.h>9#include <linux/gpio/consumer.h>10#include <linux/i2c.h>11#include <linux/regulator/consumer.h>12 13#include <dt-bindings/clock/maxim,max9485.h>14 15#define MAX9485_NUM_CLKS 416 17/* This chip has only one register of 8 bit width. */18 19#define MAX9485_FS_12KHZ (0 << 0)20#define MAX9485_FS_32KHZ (1 << 0)21#define MAX9485_FS_44_1KHZ (2 << 0)22#define MAX9485_FS_48KHZ (3 << 0)23 24#define MAX9485_SCALE_256 (0 << 2)25#define MAX9485_SCALE_384 (1 << 2)26#define MAX9485_SCALE_768 (2 << 2)27 28#define MAX9485_DOUBLE BIT(4)29#define MAX9485_CLKOUT1_ENABLE BIT(5)30#define MAX9485_CLKOUT2_ENABLE BIT(6)31#define MAX9485_MCLK_ENABLE BIT(7)32#define MAX9485_FREQ_MASK 0x1f33 34struct max9485_rate {35 unsigned long out;36 u8 reg_value;37};38 39/*40 * Ordered by frequency. For frequency the hardware can generate with41 * multiple settings, the one with lowest jitter is listed first.42 */43static const struct max9485_rate max9485_rates[] = {44 { 3072000, MAX9485_FS_12KHZ | MAX9485_SCALE_256 },45 { 4608000, MAX9485_FS_12KHZ | MAX9485_SCALE_384 },46 { 8192000, MAX9485_FS_32KHZ | MAX9485_SCALE_256 },47 { 9126000, MAX9485_FS_12KHZ | MAX9485_SCALE_768 },48 { 11289600, MAX9485_FS_44_1KHZ | MAX9485_SCALE_256 },49 { 12288000, MAX9485_FS_48KHZ | MAX9485_SCALE_256 },50 { 12288000, MAX9485_FS_32KHZ | MAX9485_SCALE_384 },51 { 16384000, MAX9485_FS_32KHZ | MAX9485_SCALE_256 | MAX9485_DOUBLE },52 { 16934400, MAX9485_FS_44_1KHZ | MAX9485_SCALE_384 },53 { 18384000, MAX9485_FS_48KHZ | MAX9485_SCALE_384 },54 { 22579200, MAX9485_FS_44_1KHZ | MAX9485_SCALE_256 | MAX9485_DOUBLE },55 { 24576000, MAX9485_FS_48KHZ | MAX9485_SCALE_256 | MAX9485_DOUBLE },56 { 24576000, MAX9485_FS_32KHZ | MAX9485_SCALE_384 | MAX9485_DOUBLE },57 { 24576000, MAX9485_FS_32KHZ | MAX9485_SCALE_768 },58 { 33868800, MAX9485_FS_44_1KHZ | MAX9485_SCALE_384 | MAX9485_DOUBLE },59 { 33868800, MAX9485_FS_44_1KHZ | MAX9485_SCALE_768 },60 { 36864000, MAX9485_FS_48KHZ | MAX9485_SCALE_384 | MAX9485_DOUBLE },61 { 36864000, MAX9485_FS_48KHZ | MAX9485_SCALE_768 },62 { 49152000, MAX9485_FS_32KHZ | MAX9485_SCALE_768 | MAX9485_DOUBLE },63 { 67737600, MAX9485_FS_44_1KHZ | MAX9485_SCALE_768 | MAX9485_DOUBLE },64 { 73728000, MAX9485_FS_48KHZ | MAX9485_SCALE_768 | MAX9485_DOUBLE },65 { } /* sentinel */66};67 68struct max9485_driver_data;69 70struct max9485_clk_hw {71 struct clk_hw hw;72 struct clk_init_data init;73 u8 enable_bit;74 struct max9485_driver_data *drvdata;75};76 77struct max9485_driver_data {78 struct clk *xclk;79 struct i2c_client *client;80 u8 reg_value;81 struct regulator *supply;82 struct gpio_desc *reset_gpio;83 struct max9485_clk_hw hw[MAX9485_NUM_CLKS];84};85 86static inline struct max9485_clk_hw *to_max9485_clk(struct clk_hw *hw)87{88 return container_of(hw, struct max9485_clk_hw, hw);89}90 91static int max9485_update_bits(struct max9485_driver_data *drvdata,92 u8 mask, u8 value)93{94 int ret;95 96 drvdata->reg_value &= ~mask;97 drvdata->reg_value |= value;98 99 dev_dbg(&drvdata->client->dev,100 "updating mask 0x%02x value 0x%02x -> 0x%02x\n",101 mask, value, drvdata->reg_value);102 103 ret = i2c_master_send(drvdata->client,104 &drvdata->reg_value,105 sizeof(drvdata->reg_value));106 107 return ret < 0 ? ret : 0;108}109 110static int max9485_clk_prepare(struct clk_hw *hw)111{112 struct max9485_clk_hw *clk_hw = to_max9485_clk(hw);113 114 return max9485_update_bits(clk_hw->drvdata,115 clk_hw->enable_bit,116 clk_hw->enable_bit);117}118 119static void max9485_clk_unprepare(struct clk_hw *hw)120{121 struct max9485_clk_hw *clk_hw = to_max9485_clk(hw);122 123 max9485_update_bits(clk_hw->drvdata, clk_hw->enable_bit, 0);124}125 126/*127 * CLKOUT - configurable clock output128 */129static int max9485_clkout_set_rate(struct clk_hw *hw, unsigned long rate,130 unsigned long parent_rate)131{132 struct max9485_clk_hw *clk_hw = to_max9485_clk(hw);133 const struct max9485_rate *entry;134 135 for (entry = max9485_rates; entry->out != 0; entry++)136 if (entry->out == rate)137 break;138 139 if (entry->out == 0)140 return -EINVAL;141 142 return max9485_update_bits(clk_hw->drvdata,143 MAX9485_FREQ_MASK,144 entry->reg_value);145}146 147static unsigned long max9485_clkout_recalc_rate(struct clk_hw *hw,148 unsigned long parent_rate)149{150 struct max9485_clk_hw *clk_hw = to_max9485_clk(hw);151 struct max9485_driver_data *drvdata = clk_hw->drvdata;152 u8 val = drvdata->reg_value & MAX9485_FREQ_MASK;153 const struct max9485_rate *entry;154 155 for (entry = max9485_rates; entry->out != 0; entry++)156 if (val == entry->reg_value)157 return entry->out;158 159 return 0;160}161 162static long max9485_clkout_round_rate(struct clk_hw *hw, unsigned long rate,163 unsigned long *parent_rate)164{165 const struct max9485_rate *curr, *prev = NULL;166 167 for (curr = max9485_rates; curr->out != 0; curr++) {168 /* Exact matches */169 if (curr->out == rate)170 return rate;171 172 /*173 * Find the first entry that has a frequency higher than the174 * requested one.175 */176 if (curr->out > rate) {177 unsigned int mid;178 179 /*180 * If this is the first entry, clamp the value to the181 * lowest possible frequency.182 */183 if (!prev)184 return curr->out;185 186 /*187 * Otherwise, determine whether the previous entry or188 * current one is closer.189 */190 mid = prev->out + ((curr->out - prev->out) / 2);191 192 return (mid > rate) ? prev->out : curr->out;193 }194 195 prev = curr;196 }197 198 /* If the last entry was still too high, clamp the value */199 return prev->out;200}201 202struct max9485_clk {203 const char *name;204 int parent_index;205 const struct clk_ops ops;206 u8 enable_bit;207};208 209static const struct max9485_clk max9485_clks[MAX9485_NUM_CLKS] = {210 [MAX9485_MCLKOUT] = {211 .name = "mclkout",212 .parent_index = -1,213 .enable_bit = MAX9485_MCLK_ENABLE,214 .ops = {215 .prepare = max9485_clk_prepare,216 .unprepare = max9485_clk_unprepare,217 },218 },219 [MAX9485_CLKOUT] = {220 .name = "clkout",221 .parent_index = -1,222 .ops = {223 .set_rate = max9485_clkout_set_rate,224 .round_rate = max9485_clkout_round_rate,225 .recalc_rate = max9485_clkout_recalc_rate,226 },227 },228 [MAX9485_CLKOUT1] = {229 .name = "clkout1",230 .parent_index = MAX9485_CLKOUT,231 .enable_bit = MAX9485_CLKOUT1_ENABLE,232 .ops = {233 .prepare = max9485_clk_prepare,234 .unprepare = max9485_clk_unprepare,235 },236 },237 [MAX9485_CLKOUT2] = {238 .name = "clkout2",239 .parent_index = MAX9485_CLKOUT,240 .enable_bit = MAX9485_CLKOUT2_ENABLE,241 .ops = {242 .prepare = max9485_clk_prepare,243 .unprepare = max9485_clk_unprepare,244 },245 },246};247 248static struct clk_hw *249max9485_of_clk_get(struct of_phandle_args *clkspec, void *data)250{251 struct max9485_driver_data *drvdata = data;252 unsigned int idx = clkspec->args[0];253 254 return &drvdata->hw[idx].hw;255}256 257static int max9485_i2c_probe(struct i2c_client *client)258{259 struct max9485_driver_data *drvdata;260 struct device *dev = &client->dev;261 const char *xclk_name;262 int i, ret;263 264 drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);265 if (!drvdata)266 return -ENOMEM;267 268 drvdata->xclk = devm_clk_get(dev, "xclk");269 if (IS_ERR(drvdata->xclk))270 return PTR_ERR(drvdata->xclk);271 272 xclk_name = __clk_get_name(drvdata->xclk);273 274 drvdata->supply = devm_regulator_get(dev, "vdd");275 if (IS_ERR(drvdata->supply))276 return PTR_ERR(drvdata->supply);277 278 ret = regulator_enable(drvdata->supply);279 if (ret < 0)280 return ret;281 282 drvdata->reset_gpio =283 devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH);284 if (IS_ERR(drvdata->reset_gpio))285 return PTR_ERR(drvdata->reset_gpio);286 287 i2c_set_clientdata(client, drvdata);288 drvdata->client = client;289 290 ret = i2c_master_recv(drvdata->client, &drvdata->reg_value,291 sizeof(drvdata->reg_value));292 if (ret < 0) {293 dev_warn(dev, "Unable to read device register: %d\n", ret);294 return ret;295 }296 297 for (i = 0; i < MAX9485_NUM_CLKS; i++) {298 int parent_index = max9485_clks[i].parent_index;299 const char *name;300 301 if (of_property_read_string_index(dev->of_node,302 "clock-output-names",303 i, &name) == 0) {304 drvdata->hw[i].init.name = name;305 } else {306 drvdata->hw[i].init.name = max9485_clks[i].name;307 }308 309 drvdata->hw[i].init.ops = &max9485_clks[i].ops;310 drvdata->hw[i].init.num_parents = 1;311 drvdata->hw[i].init.flags = 0;312 313 if (parent_index > 0) {314 drvdata->hw[i].init.parent_names =315 &drvdata->hw[parent_index].init.name;316 drvdata->hw[i].init.flags |= CLK_SET_RATE_PARENT;317 } else {318 drvdata->hw[i].init.parent_names = &xclk_name;319 }320 321 drvdata->hw[i].enable_bit = max9485_clks[i].enable_bit;322 drvdata->hw[i].hw.init = &drvdata->hw[i].init;323 drvdata->hw[i].drvdata = drvdata;324 325 ret = devm_clk_hw_register(dev, &drvdata->hw[i].hw);326 if (ret < 0)327 return ret;328 }329 330 return devm_of_clk_add_hw_provider(dev, max9485_of_clk_get, drvdata);331}332 333static int __maybe_unused max9485_suspend(struct device *dev)334{335 struct i2c_client *client = to_i2c_client(dev);336 struct max9485_driver_data *drvdata = i2c_get_clientdata(client);337 338 gpiod_set_value_cansleep(drvdata->reset_gpio, 0);339 340 return 0;341}342 343static int __maybe_unused max9485_resume(struct device *dev)344{345 struct i2c_client *client = to_i2c_client(dev);346 struct max9485_driver_data *drvdata = i2c_get_clientdata(client);347 int ret;348 349 gpiod_set_value_cansleep(drvdata->reset_gpio, 1);350 351 ret = i2c_master_send(client, &drvdata->reg_value,352 sizeof(drvdata->reg_value));353 354 return ret < 0 ? ret : 0;355}356 357static const struct dev_pm_ops max9485_pm_ops = {358 SET_SYSTEM_SLEEP_PM_OPS(max9485_suspend, max9485_resume)359};360 361static const struct of_device_id max9485_dt_ids[] = {362 { .compatible = "maxim,max9485", },363 { }364};365MODULE_DEVICE_TABLE(of, max9485_dt_ids);366 367static const struct i2c_device_id max9485_i2c_ids[] = {368 { .name = "max9485", },369 { }370};371MODULE_DEVICE_TABLE(i2c, max9485_i2c_ids);372 373static struct i2c_driver max9485_driver = {374 .driver = {375 .name = "max9485",376 .pm = &max9485_pm_ops,377 .of_match_table = max9485_dt_ids,378 },379 .probe = max9485_i2c_probe,380 .id_table = max9485_i2c_ids,381};382module_i2c_driver(max9485_driver);383 384MODULE_AUTHOR("Daniel Mack <daniel@zonque.org>");385MODULE_DESCRIPTION("MAX9485 Programmable Audio Clock Generator");386MODULE_LICENSE("GPL v2");387