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1/* SPDX-License-Identifier: GPL-2.0-or-later */2/*3 * clk-si5351.h: Skyworks / Silicon Labs Si5351A/B/C I2C Clock Generator4 *5 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>6 * Rabeeh Khoury <rabeeh@solid-run.com>7 */8 9#ifndef _CLK_SI5351_H_10#define _CLK_SI5351_H_11 12#define SI5351_BUS_BASE_ADDR 0x6013 14#define SI5351_PLL_VCO_MIN 60000000015#define SI5351_PLL_VCO_MAX 90000000016#define SI5351_MULTISYNTH_MIN_FREQ 100000017#define SI5351_MULTISYNTH_DIVBY4_FREQ 15000000018#define SI5351_MULTISYNTH_MAX_FREQ 16000000019#define SI5351_MULTISYNTH67_MAX_FREQ SI5351_MULTISYNTH_DIVBY4_FREQ20#define SI5351_CLKOUT_MIN_FREQ 800021#define SI5351_CLKOUT_MAX_FREQ SI5351_MULTISYNTH_MAX_FREQ22#define SI5351_CLKOUT67_MAX_FREQ SI5351_MULTISYNTH67_MAX_FREQ23 24#define SI5351_PLL_A_MIN 1525#define SI5351_PLL_A_MAX 9026#define SI5351_PLL_B_MAX (SI5351_PLL_C_MAX-1)27#define SI5351_PLL_C_MAX 104857528#define SI5351_MULTISYNTH_A_MIN 629#define SI5351_MULTISYNTH_A_MAX 180030#define SI5351_MULTISYNTH67_A_MAX 25431#define SI5351_MULTISYNTH_B_MAX (SI5351_MULTISYNTH_C_MAX-1)32#define SI5351_MULTISYNTH_C_MAX 104857533#define SI5351_MULTISYNTH_P1_MAX ((1<<18)-1)34#define SI5351_MULTISYNTH_P2_MAX ((1<<20)-1)35#define SI5351_MULTISYNTH_P3_MAX ((1<<20)-1)36 37#define SI5351_DEVICE_STATUS 038#define SI5351_INTERRUPT_STATUS 139#define SI5351_INTERRUPT_MASK 240#define SI5351_STATUS_SYS_INIT (1<<7)41#define SI5351_STATUS_LOL_B (1<<6)42#define SI5351_STATUS_LOL_A (1<<5)43#define SI5351_STATUS_LOS (1<<4)44#define SI5351_OUTPUT_ENABLE_CTRL 345#define SI5351_OEB_PIN_ENABLE_CTRL 946#define SI5351_PLL_INPUT_SOURCE 1547#define SI5351_CLKIN_DIV_MASK (3<<6)48#define SI5351_CLKIN_DIV_1 (0<<6)49#define SI5351_CLKIN_DIV_2 (1<<6)50#define SI5351_CLKIN_DIV_4 (2<<6)51#define SI5351_CLKIN_DIV_8 (3<<6)52#define SI5351_PLLB_SOURCE (1<<3)53#define SI5351_PLLA_SOURCE (1<<2)54 55#define SI5351_CLK0_CTRL 1656#define SI5351_CLK1_CTRL 1757#define SI5351_CLK2_CTRL 1858#define SI5351_CLK3_CTRL 1959#define SI5351_CLK4_CTRL 2060#define SI5351_CLK5_CTRL 2161#define SI5351_CLK6_CTRL 2262#define SI5351_CLK7_CTRL 2363#define SI5351_CLK_POWERDOWN (1<<7)64#define SI5351_CLK_INTEGER_MODE (1<<6)65#define SI5351_CLK_PLL_SELECT (1<<5)66#define SI5351_CLK_INVERT (1<<4)67#define SI5351_CLK_INPUT_MASK (3<<2)68#define SI5351_CLK_INPUT_XTAL (0<<2)69#define SI5351_CLK_INPUT_CLKIN (1<<2)70#define SI5351_CLK_INPUT_MULTISYNTH_0_4 (2<<2)71#define SI5351_CLK_INPUT_MULTISYNTH_N (3<<2)72#define SI5351_CLK_DRIVE_STRENGTH_MASK (3<<0)73#define SI5351_CLK_DRIVE_STRENGTH_2MA (0<<0)74#define SI5351_CLK_DRIVE_STRENGTH_4MA (1<<0)75#define SI5351_CLK_DRIVE_STRENGTH_6MA (2<<0)76#define SI5351_CLK_DRIVE_STRENGTH_8MA (3<<0)77 78#define SI5351_CLK3_0_DISABLE_STATE 2479#define SI5351_CLK7_4_DISABLE_STATE 2580#define SI5351_CLK_DISABLE_STATE_MASK 381#define SI5351_CLK_DISABLE_STATE_LOW 082#define SI5351_CLK_DISABLE_STATE_HIGH 183#define SI5351_CLK_DISABLE_STATE_FLOAT 284#define SI5351_CLK_DISABLE_STATE_NEVER 385 86#define SI5351_PARAMETERS_LENGTH 887#define SI5351_PLLA_PARAMETERS 2688#define SI5351_PLLB_PARAMETERS 3489#define SI5351_CLK0_PARAMETERS 4290#define SI5351_CLK1_PARAMETERS 5091#define SI5351_CLK2_PARAMETERS 5892#define SI5351_CLK3_PARAMETERS 6693#define SI5351_CLK4_PARAMETERS 7494#define SI5351_CLK5_PARAMETERS 8295#define SI5351_CLK6_PARAMETERS 9096#define SI5351_CLK7_PARAMETERS 9197#define SI5351_CLK6_7_OUTPUT_DIVIDER 9298#define SI5351_OUTPUT_CLK_DIV_MASK (7 << 4)99#define SI5351_OUTPUT_CLK6_DIV_MASK (7 << 0)100#define SI5351_OUTPUT_CLK_DIV_SHIFT 4101#define SI5351_OUTPUT_CLK_DIV6_SHIFT 0102#define SI5351_OUTPUT_CLK_DIV_1 0103#define SI5351_OUTPUT_CLK_DIV_2 1104#define SI5351_OUTPUT_CLK_DIV_4 2105#define SI5351_OUTPUT_CLK_DIV_8 3106#define SI5351_OUTPUT_CLK_DIV_16 4107#define SI5351_OUTPUT_CLK_DIV_32 5108#define SI5351_OUTPUT_CLK_DIV_64 6109#define SI5351_OUTPUT_CLK_DIV_128 7110#define SI5351_OUTPUT_CLK_DIVBY4 (3<<2)111 112#define SI5351_SSC_PARAM0 149113#define SI5351_SSC_PARAM1 150114#define SI5351_SSC_PARAM2 151115#define SI5351_SSC_PARAM3 152116#define SI5351_SSC_PARAM4 153117#define SI5351_SSC_PARAM5 154118#define SI5351_SSC_PARAM6 155119#define SI5351_SSC_PARAM7 156120#define SI5351_SSC_PARAM8 157121#define SI5351_SSC_PARAM9 158122#define SI5351_SSC_PARAM10 159123#define SI5351_SSC_PARAM11 160124#define SI5351_SSC_PARAM12 161125 126#define SI5351_VXCO_PARAMETERS_LOW 162127#define SI5351_VXCO_PARAMETERS_MID 163128#define SI5351_VXCO_PARAMETERS_HIGH 164129 130#define SI5351_CLK0_PHASE_OFFSET 165131#define SI5351_CLK1_PHASE_OFFSET 166132#define SI5351_CLK2_PHASE_OFFSET 167133#define SI5351_CLK3_PHASE_OFFSET 168134#define SI5351_CLK4_PHASE_OFFSET 169135#define SI5351_CLK5_PHASE_OFFSET 170136 137#define SI5351_PLL_RESET 177138#define SI5351_PLL_RESET_B (1<<7)139#define SI5351_PLL_RESET_A (1<<5)140 141#define SI5351_CRYSTAL_LOAD 183142#define SI5351_CRYSTAL_LOAD_MASK (3<<6)143#define SI5351_CRYSTAL_LOAD_6PF (1<<6)144#define SI5351_CRYSTAL_LOAD_8PF (2<<6)145#define SI5351_CRYSTAL_LOAD_10PF (3<<6)146 147#define SI5351_FANOUT_ENABLE 187148#define SI5351_CLKIN_ENABLE (1<<7)149#define SI5351_XTAL_ENABLE (1<<6)150#define SI5351_MULTISYNTH_ENABLE (1<<4)151 152/**153 * enum si5351_variant - SiLabs Si5351 chip variant154 * @SI5351_VARIANT_A: Si5351A (8 output clocks, XTAL input)155 * @SI5351_VARIANT_A3: Si5351A MSOP10 (3 output clocks, XTAL input)156 * @SI5351_VARIANT_B: Si5351B (8 output clocks, XTAL/VXCO input)157 * @SI5351_VARIANT_C: Si5351C (8 output clocks, XTAL/CLKIN input)158 */159enum si5351_variant {160 SI5351_VARIANT_A = 1,161 SI5351_VARIANT_A3 = 2,162 SI5351_VARIANT_B = 3,163 SI5351_VARIANT_C = 4,164};165 166#endif167