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1# SPDX-License-Identifier: GPL-2.02#3# Hisilicon Clock specific Makefile4#5 6obj-y += clk.o clkgate-separated.o clkdivider-hi6220.o clk-hisi-phase.o7 8obj-$(CONFIG_ARCH_HI3xxx) += clk-hi3620.o9obj-$(CONFIG_ARCH_HIP04) += clk-hip04.o10obj-$(CONFIG_ARCH_HIX5HD2) += clk-hix5hd2.o11obj-$(CONFIG_COMMON_CLK_HI3516CV300) += crg-hi3516cv300.o12obj-$(CONFIG_COMMON_CLK_HI3519) += clk-hi3519.o13obj-$(CONFIG_COMMON_CLK_HI3559A) += clk-hi3559a.o14obj-$(CONFIG_COMMON_CLK_HI3660) += clk-hi3660.o15obj-$(CONFIG_COMMON_CLK_HI3670) += clk-hi3670.o16obj-$(CONFIG_COMMON_CLK_HI3798CV200) += crg-hi3798cv200.o17obj-$(CONFIG_COMMON_CLK_HI6220) += clk-hi6220.o18obj-$(CONFIG_RESET_HISI) += reset.o19obj-$(CONFIG_STUB_CLK_HI6220) += clk-hi6220-stub.o20obj-$(CONFIG_STUB_CLK_HI3660) += clk-hi3660-stub.o21