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1// SPDX-License-Identifier: GPL-2.0+2/*3 * Copyright (C) 2016 Freescale Semiconductor, Inc.4 * Copyright 2017~2018 NXP5 *6 */7 8#include <linux/bits.h>9#include <linux/clk-provider.h>10#include <linux/err.h>11#include <linux/io.h>12#include <linux/slab.h>13 14#include "../clk-fractional-divider.h"15#include "clk.h"16 17#define PCG_PR_MASK BIT(31)18#define PCG_PCS_SHIFT 2419#define PCG_PCS_MASK 0x720#define PCG_CGC_SHIFT 3021#define PCG_FRAC_SHIFT 322#define PCG_FRAC_WIDTH 123#define PCG_PCD_SHIFT 024#define PCG_PCD_WIDTH 325 26#define SW_RST BIT(28)27 28static int pcc_gate_enable(struct clk_hw *hw)29{30 struct clk_gate *gate = to_clk_gate(hw);31 unsigned long flags;32 u32 val;33 int ret;34 35 ret = clk_gate_ops.enable(hw);36 if (ret)37 return ret;38 39 spin_lock_irqsave(gate->lock, flags);40 /*41 * release the sw reset for peripherals associated with42 * with this pcc clock.43 */44 val = readl(gate->reg);45 val |= SW_RST;46 writel(val, gate->reg);47 48 spin_unlock_irqrestore(gate->lock, flags);49 50 return 0;51}52 53static void pcc_gate_disable(struct clk_hw *hw)54{55 clk_gate_ops.disable(hw);56}57 58static int pcc_gate_is_enabled(struct clk_hw *hw)59{60 return clk_gate_ops.is_enabled(hw);61}62 63static const struct clk_ops pcc_gate_ops = {64 .enable = pcc_gate_enable,65 .disable = pcc_gate_disable,66 .is_enabled = pcc_gate_is_enabled,67};68 69static struct clk_hw *imx_ulp_clk_hw_composite(const char *name,70 const char * const *parent_names,71 int num_parents, bool mux_present,72 bool rate_present, bool gate_present,73 void __iomem *reg, bool has_swrst)74{75 struct clk_hw *mux_hw = NULL, *fd_hw = NULL, *gate_hw = NULL;76 struct clk_fractional_divider *fd = NULL;77 struct clk_gate *gate = NULL;78 struct clk_mux *mux = NULL;79 struct clk_hw *hw;80 u32 val;81 82 val = readl(reg);83 if (!(val & PCG_PR_MASK)) {84 pr_info("PCC PR is 0 for clk:%s, bypass\n", name);85 return NULL;86 }87 88 if (mux_present) {89 mux = kzalloc(sizeof(*mux), GFP_KERNEL);90 if (!mux)91 return ERR_PTR(-ENOMEM);92 mux_hw = &mux->hw;93 mux->reg = reg;94 mux->shift = PCG_PCS_SHIFT;95 mux->mask = PCG_PCS_MASK;96 if (has_swrst)97 mux->lock = &imx_ccm_lock;98 }99 100 if (rate_present) {101 fd = kzalloc(sizeof(*fd), GFP_KERNEL);102 if (!fd) {103 kfree(mux);104 return ERR_PTR(-ENOMEM);105 }106 fd_hw = &fd->hw;107 fd->reg = reg;108 fd->mshift = PCG_FRAC_SHIFT;109 fd->mwidth = PCG_FRAC_WIDTH;110 fd->nshift = PCG_PCD_SHIFT;111 fd->nwidth = PCG_PCD_WIDTH;112 fd->flags = CLK_FRAC_DIVIDER_ZERO_BASED;113 if (has_swrst)114 fd->lock = &imx_ccm_lock;115 }116 117 if (gate_present) {118 gate = kzalloc(sizeof(*gate), GFP_KERNEL);119 if (!gate) {120 kfree(mux);121 kfree(fd);122 return ERR_PTR(-ENOMEM);123 }124 gate_hw = &gate->hw;125 gate->reg = reg;126 gate->bit_idx = PCG_CGC_SHIFT;127 if (has_swrst)128 gate->lock = &imx_ccm_lock;129 /*130 * make sure clock is gated during clock tree initialization,131 * the HW ONLY allow clock parent/rate changed with clock gated,132 * during clock tree initialization, clocks could be enabled133 * by bootloader, so the HW status will mismatch with clock tree134 * prepare count, then clock core driver will allow parent/rate135 * change since the prepare count is zero, but HW actually136 * prevent the parent/rate change due to the clock is enabled.137 */138 val = readl_relaxed(reg);139 val &= ~(1 << PCG_CGC_SHIFT);140 writel_relaxed(val, reg);141 }142 143 hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,144 mux_hw, &clk_mux_ops, fd_hw,145 &clk_fractional_divider_ops, gate_hw,146 has_swrst ? &pcc_gate_ops : &clk_gate_ops, CLK_SET_RATE_GATE |147 CLK_SET_PARENT_GATE | CLK_SET_RATE_NO_REPARENT);148 if (IS_ERR(hw)) {149 kfree(mux);150 kfree(fd);151 kfree(gate);152 }153 154 return hw;155}156 157struct clk_hw *imx7ulp_clk_hw_composite(const char *name, const char * const *parent_names,158 int num_parents, bool mux_present, bool rate_present,159 bool gate_present, void __iomem *reg)160{161 return imx_ulp_clk_hw_composite(name, parent_names, num_parents, mux_present, rate_present,162 gate_present, reg, false);163}164 165struct clk_hw *imx8ulp_clk_hw_composite(const char *name, const char * const *parent_names,166 int num_parents, bool mux_present, bool rate_present,167 bool gate_present, void __iomem *reg, bool has_swrst)168{169 return imx_ulp_clk_hw_composite(name, parent_names, num_parents, mux_present, rate_present,170 gate_present, reg, has_swrst);171}172EXPORT_SYMBOL_GPL(imx8ulp_clk_hw_composite);173