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1/* SPDX-License-Identifier: GPL-2.0 */2#ifndef __MACH_IMX_CLK_H3#define __MACH_IMX_CLK_H4 5#include <linux/bits.h>6#include <linux/spinlock.h>7#include <linux/clk-provider.h>8 9extern spinlock_t imx_ccm_lock;10extern bool mcore_booted;11 12void imx_check_clocks(struct clk *clks[], unsigned int count);13void imx_check_clk_hws(struct clk_hw *clks[], unsigned int count);14#ifndef MODULE15void imx_register_uart_clocks(void);16#else17static inline void imx_register_uart_clocks(void)18{19}20#endif21void imx_mmdc_mask_handshake(void __iomem *ccm_base, unsigned int chn);22void imx_unregister_hw_clocks(struct clk_hw *hws[], unsigned int count);23 24extern void imx_cscmr1_fixup(u32 *val);25 26enum imx_pllv1_type {27 IMX_PLLV1_IMX1,28 IMX_PLLV1_IMX21,29 IMX_PLLV1_IMX25,30 IMX_PLLV1_IMX27,31 IMX_PLLV1_IMX31,32 IMX_PLLV1_IMX35,33};34 35enum imx_sscg_pll_type {36 SCCG_PLL1,37 SCCG_PLL2,38};39 40enum imx_pll14xx_type {41 PLL_1416X,42 PLL_1443X,43};44 45enum imx_pllv4_type {46 IMX_PLLV4_IMX7ULP,47 IMX_PLLV4_IMX8ULP,48 IMX_PLLV4_IMX8ULP_1GHZ,49};50 51enum imx_pfdv2_type {52 IMX_PFDV2_IMX7ULP,53 IMX_PFDV2_IMX8ULP,54};55 56/* NOTE: Rate table should be kept sorted in descending order. */57struct imx_pll14xx_rate_table {58 unsigned int rate;59 unsigned int pdiv;60 unsigned int mdiv;61 unsigned int sdiv;62 unsigned int kdiv;63};64 65struct imx_pll14xx_clk {66 enum imx_pll14xx_type type;67 const struct imx_pll14xx_rate_table *rate_table;68 int rate_count;69 int flags;70};71 72extern struct imx_pll14xx_clk imx_1416x_pll;73extern struct imx_pll14xx_clk imx_1443x_pll;74extern struct imx_pll14xx_clk imx_1443x_dram_pll;75 76#define CLK_FRACN_GPPLL_INTEGER BIT(0)77#define CLK_FRACN_GPPLL_FRACN BIT(1)78 79/* NOTE: Rate table should be kept sorted in descending order. */80struct imx_fracn_gppll_rate_table {81 unsigned int rate;82 unsigned int mfi;83 unsigned int mfn;84 unsigned int mfd;85 unsigned int rdiv;86 unsigned int odiv;87};88 89struct imx_fracn_gppll_clk {90 const struct imx_fracn_gppll_rate_table *rate_table;91 int rate_count;92 int flags;93};94 95struct clk_hw *imx_clk_fracn_gppll(const char *name, const char *parent_name, void __iomem *base,96 const struct imx_fracn_gppll_clk *pll_clk);97struct clk_hw *imx_clk_fracn_gppll_integer(const char *name, const char *parent_name,98 void __iomem *base,99 const struct imx_fracn_gppll_clk *pll_clk);100 101extern struct imx_fracn_gppll_clk imx_fracn_gppll;102extern struct imx_fracn_gppll_clk imx_fracn_gppll_integer;103 104#define imx_clk_cpu(name, parent_name, div, mux, pll, step) \105 to_clk(imx_clk_hw_cpu(name, parent_name, div, mux, pll, step))106 107#define clk_register_gate2(dev, name, parent_name, flags, reg, bit_idx, \108 cgr_val, cgr_mask, clk_gate_flags, lock, share_count) \109 to_clk(clk_hw_register_gate2(dev, name, parent_name, flags, reg, bit_idx, \110 cgr_val, cgr_mask, clk_gate_flags, lock, share_count))111 112#define imx_clk_pllv3(type, name, parent_name, base, div_mask) \113 to_clk(imx_clk_hw_pllv3(type, name, parent_name, base, div_mask))114 115#define imx_clk_pfd(name, parent_name, reg, idx) \116 to_clk(imx_clk_hw_pfd(name, parent_name, reg, idx))117 118#define imx_clk_gate_exclusive(name, parent, reg, shift, exclusive_mask) \119 to_clk(imx_clk_hw_gate_exclusive(name, parent, reg, shift, exclusive_mask))120 121#define imx_clk_fixed(name, rate) \122 to_clk(imx_clk_hw_fixed(name, rate))123 124#define imx_clk_fixed_factor(name, parent, mult, div) \125 to_clk(imx_clk_hw_fixed_factor(name, parent, mult, div))126 127#define imx_clk_divider(name, parent, reg, shift, width) \128 to_clk(imx_clk_hw_divider(name, parent, reg, shift, width))129 130#define imx_clk_divider_flags(name, parent, reg, shift, width, flags) \131 to_clk(imx_clk_hw_divider_flags(name, parent, reg, shift, width, flags))132 133#define imx_clk_gate(name, parent, reg, shift) \134 to_clk(imx_clk_hw_gate(name, parent, reg, shift))135 136#define imx_clk_gate_dis(name, parent, reg, shift) \137 to_clk(imx_clk_hw_gate_dis(name, parent, reg, shift))138 139#define imx_clk_gate2(name, parent, reg, shift) \140 to_clk(imx_clk_hw_gate2(name, parent, reg, shift))141 142#define imx_clk_gate2_cgr(name, parent, reg, shift, cgr_val) \143 to_clk(__imx_clk_hw_gate2(name, parent, reg, shift, cgr_val, 0, NULL))144 145#define imx_clk_gate2_flags(name, parent, reg, shift, flags) \146 to_clk(imx_clk_hw_gate2_flags(name, parent, reg, shift, flags))147 148#define imx_clk_mux(name, reg, shift, width, parents, num_parents) \149 to_clk(imx_clk_hw_mux(name, reg, shift, width, parents, num_parents))150 151#define imx_clk_mux_flags(name, reg, shift, width, parents, num_parents, flags) \152 to_clk(imx_clk_hw_mux_flags(name, reg, shift, width, parents, num_parents, flags))153 154#define imx_clk_mux2_flags(name, reg, shift, width, parents, num_parents, flags) \155 to_clk(imx_clk_hw_mux2_flags(name, reg, shift, width, parents, num_parents, flags))156 157#define imx_clk_pllv1(type, name, parent, base) \158 to_clk(imx_clk_hw_pllv1(type, name, parent, base))159 160#define imx_clk_pllv2(name, parent, base) \161 to_clk(imx_clk_hw_pllv2(name, parent, base))162 163#define imx_clk_hw_gate(name, parent, reg, shift) \164 imx_clk_hw_gate_flags(name, parent, reg, shift, 0)165 166#define imx_clk_hw_gate2(name, parent, reg, shift) \167 imx_clk_hw_gate2_flags(name, parent, reg, shift, 0)168 169#define imx_clk_hw_gate_dis(name, parent, reg, shift) \170 imx_clk_hw_gate_dis_flags(name, parent, reg, shift, 0)171 172#define imx_clk_hw_gate_dis_flags(name, parent, reg, shift, flags) \173 __imx_clk_hw_gate(name, parent, reg, shift, flags, CLK_GATE_SET_TO_DISABLE)174 175#define imx_clk_hw_gate_flags(name, parent, reg, shift, flags) \176 __imx_clk_hw_gate(name, parent, reg, shift, flags, 0)177 178#define imx_clk_hw_gate2_flags(name, parent, reg, shift, flags) \179 __imx_clk_hw_gate2(name, parent, reg, shift, 0x3, flags, NULL)180 181#define imx_clk_hw_gate2_shared(name, parent, reg, shift, shared_count) \182 __imx_clk_hw_gate2(name, parent, reg, shift, 0x3, 0, shared_count)183 184#define imx_clk_hw_gate2_shared2(name, parent, reg, shift, shared_count) \185 __imx_clk_hw_gate2(name, parent, reg, shift, 0x3, CLK_OPS_PARENT_ENABLE, shared_count)186 187#define imx_clk_hw_gate3(name, parent, reg, shift) \188 imx_clk_hw_gate3_flags(name, parent, reg, shift, 0)189 190#define imx_clk_hw_gate3_flags(name, parent, reg, shift, flags) \191 __imx_clk_hw_gate(name, parent, reg, shift, flags | CLK_OPS_PARENT_ENABLE, 0)192 193#define imx_clk_hw_gate4(name, parent, reg, shift) \194 imx_clk_hw_gate4_flags(name, parent, reg, shift, 0)195 196#define imx_clk_hw_gate4_flags(name, parent, reg, shift, flags) \197 imx_clk_hw_gate2_flags(name, parent, reg, shift, flags | CLK_OPS_PARENT_ENABLE)198 199#define imx_clk_hw_mux2(name, reg, shift, width, parents, num_parents) \200 imx_clk_hw_mux2_flags(name, reg, shift, width, parents, num_parents, 0)201 202#define imx_clk_hw_mux(name, reg, shift, width, parents, num_parents) \203 __imx_clk_hw_mux(name, reg, shift, width, parents, num_parents, 0, 0)204 205#define imx_clk_hw_mux_flags(name, reg, shift, width, parents, num_parents, flags) \206 __imx_clk_hw_mux(name, reg, shift, width, parents, num_parents, flags, 0)207 208#define imx_clk_hw_mux_ldb(name, reg, shift, width, parents, num_parents) \209 __imx_clk_hw_mux(name, reg, shift, width, parents, num_parents, CLK_SET_RATE_PARENT, CLK_MUX_READ_ONLY)210 211#define imx_clk_hw_mux2_flags(name, reg, shift, width, parents, num_parents, flags) \212 __imx_clk_hw_mux(name, reg, shift, width, parents, num_parents, flags | CLK_OPS_PARENT_ENABLE, 0)213 214#define imx_clk_hw_divider(name, parent, reg, shift, width) \215 __imx_clk_hw_divider(name, parent, reg, shift, width, CLK_SET_RATE_PARENT)216 217#define imx_clk_hw_divider2(name, parent, reg, shift, width) \218 __imx_clk_hw_divider(name, parent, reg, shift, width, \219 CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE)220 221#define imx_clk_hw_divider_flags(name, parent, reg, shift, width, flags) \222 __imx_clk_hw_divider(name, parent, reg, shift, width, flags)223 224#define imx_clk_hw_pll14xx(name, parent_name, base, pll_clk) \225 imx_dev_clk_hw_pll14xx(NULL, name, parent_name, base, pll_clk)226 227struct clk_hw *imx_dev_clk_hw_pll14xx(struct device *dev, const char *name,228 const char *parent_name, void __iomem *base,229 const struct imx_pll14xx_clk *pll_clk);230 231struct clk_hw *imx_clk_hw_pllv1(enum imx_pllv1_type type, const char *name,232 const char *parent, void __iomem *base);233 234struct clk_hw *imx_clk_hw_pllv2(const char *name, const char *parent,235 void __iomem *base);236 237struct clk_hw *imx_clk_hw_frac_pll(const char *name, const char *parent_name,238 void __iomem *base);239 240struct clk_hw *imx_clk_hw_sscg_pll(const char *name,241 const char * const *parent_names,242 u8 num_parents,243 u8 parent, u8 bypass1, u8 bypass2,244 void __iomem *base,245 unsigned long flags);246 247enum imx_pllv3_type {248 IMX_PLLV3_GENERIC,249 IMX_PLLV3_SYS,250 IMX_PLLV3_USB,251 IMX_PLLV3_USB_VF610,252 IMX_PLLV3_AV,253 IMX_PLLV3_ENET,254 IMX_PLLV3_ENET_IMX7,255 IMX_PLLV3_SYS_VF610,256 IMX_PLLV3_DDR_IMX7,257 IMX_PLLV3_AV_IMX7,258};259 260struct clk_hw *imx_clk_hw_pllv3(enum imx_pllv3_type type, const char *name,261 const char *parent_name, void __iomem *base, u32 div_mask);262 263#define PLL_1416X_RATE(_rate, _m, _p, _s) \264 { \265 .rate = (_rate), \266 .mdiv = (_m), \267 .pdiv = (_p), \268 .sdiv = (_s), \269 }270 271#define PLL_1443X_RATE(_rate, _m, _p, _s, _k) \272 { \273 .rate = (_rate), \274 .mdiv = (_m), \275 .pdiv = (_p), \276 .sdiv = (_s), \277 .kdiv = (_k), \278 }279 280struct clk_hw *imx_clk_hw_pllv4(enum imx_pllv4_type type, const char *name,281 const char *parent_name, void __iomem *base);282 283struct clk_hw *clk_hw_register_gate2(struct device *dev, const char *name,284 const char *parent_name, unsigned long flags,285 void __iomem *reg, u8 bit_idx, u8 cgr_val, u8 cgr_mask,286 u8 clk_gate_flags, spinlock_t *lock,287 unsigned int *share_count);288 289struct clk * imx_obtain_fixed_clock(290 const char *name, unsigned long rate);291 292struct clk_hw *imx_obtain_fixed_clock_hw(293 const char *name, unsigned long rate);294 295struct clk_hw *imx_obtain_fixed_of_clock(struct device_node *np,296 const char *name, unsigned long rate);297 298struct clk_hw *imx_get_clk_hw_by_name(struct device_node *np, const char *name);299 300struct clk_hw *imx_clk_hw_gate_exclusive(const char *name, const char *parent,301 void __iomem *reg, u8 shift, u32 exclusive_mask);302 303struct clk_hw *imx_clk_hw_pfd(const char *name, const char *parent_name,304 void __iomem *reg, u8 idx);305 306struct clk_hw *imx_clk_hw_pfdv2(enum imx_pfdv2_type type, const char *name,307 const char *parent_name, void __iomem *reg, u8 idx);308 309struct clk_hw *imx_clk_hw_busy_divider(const char *name, const char *parent_name,310 void __iomem *reg, u8 shift, u8 width,311 void __iomem *busy_reg, u8 busy_shift);312 313struct clk_hw *imx_clk_hw_busy_mux(const char *name, void __iomem *reg, u8 shift,314 u8 width, void __iomem *busy_reg, u8 busy_shift,315 const char * const *parent_names, int num_parents);316 317struct clk_hw *imx7ulp_clk_hw_composite(const char *name,318 const char * const *parent_names,319 int num_parents, bool mux_present,320 bool rate_present, bool gate_present,321 void __iomem *reg);322 323struct clk_hw *imx8ulp_clk_hw_composite(const char *name,324 const char * const *parent_names,325 int num_parents, bool mux_present,326 bool rate_present, bool gate_present,327 void __iomem *reg, bool has_swrst);328 329struct clk_hw *imx_clk_hw_fixup_divider(const char *name, const char *parent,330 void __iomem *reg, u8 shift, u8 width,331 void (*fixup)(u32 *val));332 333struct clk_hw *imx_clk_hw_fixup_mux(const char *name, void __iomem *reg,334 u8 shift, u8 width, const char * const *parents,335 int num_parents, void (*fixup)(u32 *val));336 337static inline struct clk *to_clk(struct clk_hw *hw)338{339 if (IS_ERR_OR_NULL(hw))340 return ERR_CAST(hw);341 return hw->clk;342}343 344static inline struct clk_hw *imx_clk_hw_fixed(const char *name, int rate)345{346 return clk_hw_register_fixed_rate(NULL, name, NULL, 0, rate);347}348 349static inline struct clk_hw *imx_clk_hw_fixed_factor(const char *name,350 const char *parent, unsigned int mult, unsigned int div)351{352 return clk_hw_register_fixed_factor(NULL, name, parent,353 CLK_SET_RATE_PARENT, mult, div);354}355 356static inline struct clk_hw *imx_clk_hw_divider_closest(const char *name,357 const char *parent,358 void __iomem *reg, u8 shift,359 u8 width)360{361 return clk_hw_register_divider(NULL, name, parent, 0,362 reg, shift, width, CLK_DIVIDER_ROUND_CLOSEST, &imx_ccm_lock);363}364 365static inline struct clk_hw *__imx_clk_hw_divider(const char *name,366 const char *parent,367 void __iomem *reg, u8 shift,368 u8 width, unsigned long flags)369{370 return clk_hw_register_divider(NULL, name, parent, flags,371 reg, shift, width, 0, &imx_ccm_lock);372}373 374static inline struct clk_hw *__imx_clk_hw_gate(const char *name, const char *parent,375 void __iomem *reg, u8 shift,376 unsigned long flags,377 unsigned long clk_gate_flags)378{379 return clk_hw_register_gate(NULL, name, parent, flags | CLK_SET_RATE_PARENT, reg,380 shift, clk_gate_flags, &imx_ccm_lock);381}382 383static inline struct clk_hw *__imx_clk_hw_gate2(const char *name, const char *parent,384 void __iomem *reg, u8 shift, u8 cgr_val,385 unsigned long flags,386 unsigned int *share_count)387{388 return clk_hw_register_gate2(NULL, name, parent, flags | CLK_SET_RATE_PARENT, reg,389 shift, cgr_val, 0x3, 0, &imx_ccm_lock, share_count);390}391 392static inline struct clk_hw *__imx_clk_hw_mux(const char *name, void __iomem *reg,393 u8 shift, u8 width, const char * const *parents,394 int num_parents, unsigned long flags, unsigned long clk_mux_flags)395{396 return clk_hw_register_mux(NULL, name, parents, num_parents,397 flags | CLK_SET_RATE_NO_REPARENT, reg, shift,398 width, clk_mux_flags, &imx_ccm_lock);399}400 401struct clk_hw *imx_clk_hw_cpu(const char *name, const char *parent_name,402 struct clk *div, struct clk *mux, struct clk *pll,403 struct clk *step);404 405#define IMX_COMPOSITE_CORE BIT(0)406#define IMX_COMPOSITE_BUS BIT(1)407#define IMX_COMPOSITE_FW_MANAGED BIT(2)408 409#define IMX_COMPOSITE_CLK_FLAGS_DEFAULT \410 (CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE)411#define IMX_COMPOSITE_CLK_FLAGS_CRITICAL \412 (IMX_COMPOSITE_CLK_FLAGS_DEFAULT | CLK_IS_CRITICAL)413#define IMX_COMPOSITE_CLK_FLAGS_GET_RATE_NO_CACHE \414 (IMX_COMPOSITE_CLK_FLAGS_DEFAULT | CLK_GET_RATE_NOCACHE)415#define IMX_COMPOSITE_CLK_FLAGS_CRITICAL_GET_RATE_NO_CACHE \416 (IMX_COMPOSITE_CLK_FLAGS_GET_RATE_NO_CACHE | CLK_IS_CRITICAL)417 418struct clk_hw *__imx8m_clk_hw_composite(const char *name,419 const char * const *parent_names,420 int num_parents,421 void __iomem *reg,422 u32 composite_flags,423 unsigned long flags);424 425#define _imx8m_clk_hw_composite(name, parent_names, reg, composite_flags, flags) \426 __imx8m_clk_hw_composite(name, parent_names, \427 ARRAY_SIZE(parent_names), reg, composite_flags, flags)428 429#define imx8m_clk_hw_composite(name, parent_names, reg) \430 _imx8m_clk_hw_composite(name, parent_names, reg, \431 0, IMX_COMPOSITE_CLK_FLAGS_DEFAULT)432 433#define imx8m_clk_hw_composite_flags(name, parent_names, reg, flags) \434 _imx8m_clk_hw_composite(name, parent_names, reg, \435 0, IMX_COMPOSITE_CLK_FLAGS_DEFAULT | flags)436 437#define imx8m_clk_hw_composite_critical(name, parent_names, reg) \438 _imx8m_clk_hw_composite(name, parent_names, reg, \439 0, IMX_COMPOSITE_CLK_FLAGS_CRITICAL)440 441#define imx8m_clk_hw_composite_bus(name, parent_names, reg) \442 _imx8m_clk_hw_composite(name, parent_names, reg, \443 IMX_COMPOSITE_BUS, IMX_COMPOSITE_CLK_FLAGS_DEFAULT)444 445#define imx8m_clk_hw_composite_bus_flags(name, parent_names, reg, flags) \446 _imx8m_clk_hw_composite(name, parent_names, reg, \447 IMX_COMPOSITE_BUS, IMX_COMPOSITE_CLK_FLAGS_DEFAULT | flags)448 449#define imx8m_clk_hw_composite_bus_critical(name, parent_names, reg) \450 _imx8m_clk_hw_composite(name, parent_names, reg, \451 IMX_COMPOSITE_BUS, IMX_COMPOSITE_CLK_FLAGS_CRITICAL)452 453#define imx8m_clk_hw_composite_core(name, parent_names, reg) \454 _imx8m_clk_hw_composite(name, parent_names, reg, \455 IMX_COMPOSITE_CORE, IMX_COMPOSITE_CLK_FLAGS_DEFAULT)456 457#define imx8m_clk_hw_fw_managed_composite(name, parent_names, reg) \458 _imx8m_clk_hw_composite(name, parent_names, reg, \459 IMX_COMPOSITE_FW_MANAGED, \460 IMX_COMPOSITE_CLK_FLAGS_GET_RATE_NO_CACHE)461 462#define imx8m_clk_hw_fw_managed_composite_critical(name, parent_names, reg) \463 _imx8m_clk_hw_composite(name, parent_names, reg, \464 IMX_COMPOSITE_FW_MANAGED, \465 IMX_COMPOSITE_CLK_FLAGS_CRITICAL_GET_RATE_NO_CACHE)466 467struct clk_hw *imx93_clk_composite_flags(const char *name,468 const char * const *parent_names,469 int num_parents,470 void __iomem *reg,471 u32 domain_id,472 unsigned long flags);473#define imx93_clk_composite(name, parent_names, num_parents, reg, domain_id) \474 imx93_clk_composite_flags(name, parent_names, num_parents, reg, domain_id \475 CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE)476 477struct clk_hw *imx93_clk_gate(struct device *dev, const char *name, const char *parent_name,478 unsigned long flags, void __iomem *reg, u32 bit_idx, u32 val,479 u32 mask, u32 domain_id, unsigned int *share_count);480 481struct clk_hw *imx_clk_hw_divider_gate(const char *name, const char *parent_name,482 unsigned long flags, void __iomem *reg, u8 shift, u8 width,483 u8 clk_divider_flags, const struct clk_div_table *table,484 spinlock_t *lock);485 486struct clk_hw *imx_clk_gpr_mux(const char *name, const char *compatible,487 u32 reg, const char **parent_names,488 u8 num_parents, const u32 *mux_table, u32 mask);489 490#endif491