66 lines · c
1// SPDX-License-Identifier: GPL-2.0-only2/*3 * Copyright (c) 2014 MediaTek Inc.4 * Author: Shunli Wang <shunli.wang@mediatek.com>5 */6 7#include <linux/clk-provider.h>8#include <linux/platform_device.h>9 10#include "clk-mtk.h"11#include "clk-gate.h"12 13#include <dt-bindings/clock/mt2701-clk.h>14 15static const struct mtk_gate_regs eth_cg_regs = {16 .sta_ofs = 0x0030,17};18 19#define GATE_ETH(_id, _name, _parent, _shift) \20 GATE_MTK(_id, _name, _parent, ð_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)21 22static const struct mtk_gate eth_clks[] = {23 GATE_DUMMY(CLK_DUMMY, "eth_dummy"),24 GATE_ETH(CLK_ETHSYS_HSDMA, "hsdma_clk", "ethif_sel", 5),25 GATE_ETH(CLK_ETHSYS_ESW, "esw_clk", "ethpll_500m_ck", 6),26 GATE_ETH(CLK_ETHSYS_GP2, "gp2_clk", "trgpll", 7),27 GATE_ETH(CLK_ETHSYS_GP1, "gp1_clk", "ethpll_500m_ck", 8),28 GATE_ETH(CLK_ETHSYS_PCM, "pcm_clk", "ethif_sel", 11),29 GATE_ETH(CLK_ETHSYS_GDMA, "gdma_clk", "ethif_sel", 14),30 GATE_ETH(CLK_ETHSYS_I2S, "i2s_clk", "ethif_sel", 17),31 GATE_ETH(CLK_ETHSYS_CRYPTO, "crypto_clk", "ethif_sel", 29),32};33 34static u16 rst_ofs[] = { 0x34, };35 36static const struct mtk_clk_rst_desc clk_rst_desc = {37 .version = MTK_RST_SIMPLE,38 .rst_bank_ofs = rst_ofs,39 .rst_bank_nr = ARRAY_SIZE(rst_ofs),40};41 42static const struct mtk_clk_desc eth_desc = {43 .clks = eth_clks,44 .num_clks = ARRAY_SIZE(eth_clks),45 .rst_desc = &clk_rst_desc,46};47 48static const struct of_device_id of_match_clk_mt2701_eth[] = {49 { .compatible = "mediatek,mt2701-ethsys", .data = ð_desc },50 { /* sentinel */ }51};52MODULE_DEVICE_TABLE(of, of_match_clk_mt2701_eth);53 54static struct platform_driver clk_mt2701_eth_drv = {55 .probe = mtk_clk_simple_probe,56 .remove = mtk_clk_simple_remove,57 .driver = {58 .name = "clk-mt2701-eth",59 .of_match_table = of_match_clk_mt2701_eth,60 },61};62module_platform_driver(clk_mt2701_eth_drv);63 64MODULE_DESCRIPTION("MediaTek MT2701 Ethernet clocks driver");65MODULE_LICENSE("GPL");66