134 lines · c
1// SPDX-License-Identifier: GPL-2.0-only2/*3 * Copyright (c) 2017 MediaTek Inc.4 * Author: Weiyi Lu <weiyi.lu@mediatek.com>5 */6 7#include <linux/clk-provider.h>8#include <linux/platform_device.h>9 10#include "clk-mtk.h"11#include "clk-gate.h"12 13#include <dt-bindings/clock/mt2712-clk.h>14 15static const struct mtk_gate_regs mm0_cg_regs = {16 .set_ofs = 0x104,17 .clr_ofs = 0x108,18 .sta_ofs = 0x100,19};20 21static const struct mtk_gate_regs mm1_cg_regs = {22 .set_ofs = 0x114,23 .clr_ofs = 0x118,24 .sta_ofs = 0x110,25};26 27static const struct mtk_gate_regs mm2_cg_regs = {28 .set_ofs = 0x224,29 .clr_ofs = 0x228,30 .sta_ofs = 0x220,31};32 33#define GATE_MM0(_id, _name, _parent, _shift) \34 GATE_MTK(_id, _name, _parent, &mm0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)35 36#define GATE_MM1(_id, _name, _parent, _shift) \37 GATE_MTK(_id, _name, _parent, &mm1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)38 39#define GATE_MM2(_id, _name, _parent, _shift) \40 GATE_MTK(_id, _name, _parent, &mm2_cg_regs, _shift, &mtk_clk_gate_ops_setclr)41 42static const struct mtk_gate mm_clks[] = {43 /* MM0 */44 GATE_MM0(CLK_MM_SMI_COMMON, "mm_smi_common", "mm_sel", 0),45 GATE_MM0(CLK_MM_SMI_LARB0, "mm_smi_larb0", "mm_sel", 1),46 GATE_MM0(CLK_MM_CAM_MDP, "mm_cam_mdp", "mm_sel", 2),47 GATE_MM0(CLK_MM_MDP_RDMA0, "mm_mdp_rdma0", "mm_sel", 3),48 GATE_MM0(CLK_MM_MDP_RDMA1, "mm_mdp_rdma1", "mm_sel", 4),49 GATE_MM0(CLK_MM_MDP_RSZ0, "mm_mdp_rsz0", "mm_sel", 5),50 GATE_MM0(CLK_MM_MDP_RSZ1, "mm_mdp_rsz1", "mm_sel", 6),51 GATE_MM0(CLK_MM_MDP_RSZ2, "mm_mdp_rsz2", "mm_sel", 7),52 GATE_MM0(CLK_MM_MDP_TDSHP0, "mm_mdp_tdshp0", "mm_sel", 8),53 GATE_MM0(CLK_MM_MDP_TDSHP1, "mm_mdp_tdshp1", "mm_sel", 9),54 GATE_MM0(CLK_MM_MDP_CROP, "mm_mdp_crop", "mm_sel", 10),55 GATE_MM0(CLK_MM_MDP_WDMA, "mm_mdp_wdma", "mm_sel", 11),56 GATE_MM0(CLK_MM_MDP_WROT0, "mm_mdp_wrot0", "mm_sel", 12),57 GATE_MM0(CLK_MM_MDP_WROT1, "mm_mdp_wrot1", "mm_sel", 13),58 GATE_MM0(CLK_MM_FAKE_ENG, "mm_fake_eng", "mm_sel", 14),59 GATE_MM0(CLK_MM_MUTEX_32K, "mm_mutex_32k", "clk32k", 15),60 GATE_MM0(CLK_MM_DISP_OVL0, "mm_disp_ovl0", "mm_sel", 16),61 GATE_MM0(CLK_MM_DISP_OVL1, "mm_disp_ovl1", "mm_sel", 17),62 GATE_MM0(CLK_MM_DISP_RDMA0, "mm_disp_rdma0", "mm_sel", 18),63 GATE_MM0(CLK_MM_DISP_RDMA1, "mm_disp_rdma1", "mm_sel", 19),64 GATE_MM0(CLK_MM_DISP_RDMA2, "mm_disp_rdma2", "mm_sel", 20),65 GATE_MM0(CLK_MM_DISP_WDMA0, "mm_disp_wdma0", "mm_sel", 21),66 GATE_MM0(CLK_MM_DISP_WDMA1, "mm_disp_wdma1", "mm_sel", 22),67 GATE_MM0(CLK_MM_DISP_COLOR0, "mm_disp_color0", "mm_sel", 23),68 GATE_MM0(CLK_MM_DISP_COLOR1, "mm_disp_color1", "mm_sel", 24),69 GATE_MM0(CLK_MM_DISP_AAL, "mm_disp_aal", "mm_sel", 25),70 GATE_MM0(CLK_MM_DISP_GAMMA, "mm_disp_gamma", "mm_sel", 26),71 GATE_MM0(CLK_MM_DISP_UFOE, "mm_disp_ufoe", "mm_sel", 27),72 GATE_MM0(CLK_MM_DISP_SPLIT0, "mm_disp_split0", "mm_sel", 28),73 GATE_MM0(CLK_MM_DISP_OD, "mm_disp_od", "mm_sel", 31),74 /* MM1 */75 GATE_MM1(CLK_MM_DISP_PWM0_MM, "mm_pwm0_mm", "mm_sel", 0),76 GATE_MM1(CLK_MM_DISP_PWM0_26M, "mm_pwm0_26m", "pwm_sel", 1),77 GATE_MM1(CLK_MM_DISP_PWM1_MM, "mm_pwm1_mm", "mm_sel", 2),78 GATE_MM1(CLK_MM_DISP_PWM1_26M, "mm_pwm1_26m", "pwm_sel", 3),79 GATE_MM1(CLK_MM_DSI0_ENGINE, "mm_dsi0_engine", "mm_sel", 4),80 GATE_MM1(CLK_MM_DSI0_DIGITAL, "mm_dsi0_digital", "dsi0_lntc", 5),81 GATE_MM1(CLK_MM_DSI1_ENGINE, "mm_dsi1_engine", "mm_sel", 6),82 GATE_MM1(CLK_MM_DSI1_DIGITAL, "mm_dsi1_digital", "dsi1_lntc", 7),83 GATE_MM1(CLK_MM_DPI_PIXEL, "mm_dpi_pixel", "vpll_dpix", 8),84 GATE_MM1(CLK_MM_DPI_ENGINE, "mm_dpi_engine", "mm_sel", 9),85 GATE_MM1(CLK_MM_DPI1_PIXEL, "mm_dpi1_pixel", "vpll3_dpix", 10),86 GATE_MM1(CLK_MM_DPI1_ENGINE, "mm_dpi1_engine", "mm_sel", 11),87 GATE_MM1(CLK_MM_LVDS_PIXEL, "mm_lvds_pixel", "vpll_dpix", 16),88 GATE_MM1(CLK_MM_LVDS_CTS, "mm_lvds_cts", "lvdstx", 17),89 GATE_MM1(CLK_MM_SMI_LARB4, "mm_smi_larb4", "mm_sel", 18),90 GATE_MM1(CLK_MM_SMI_COMMON1, "mm_smi_common1", "mm_sel", 21),91 GATE_MM1(CLK_MM_SMI_LARB5, "mm_smi_larb5", "mm_sel", 22),92 GATE_MM1(CLK_MM_MDP_RDMA2, "mm_mdp_rdma2", "mm_sel", 23),93 GATE_MM1(CLK_MM_MDP_TDSHP2, "mm_mdp_tdshp2", "mm_sel", 24),94 GATE_MM1(CLK_MM_DISP_OVL2, "mm_disp_ovl2", "mm_sel", 25),95 GATE_MM1(CLK_MM_DISP_WDMA2, "mm_disp_wdma2", "mm_sel", 26),96 GATE_MM1(CLK_MM_DISP_COLOR2, "mm_disp_color2", "mm_sel", 27),97 GATE_MM1(CLK_MM_DISP_AAL1, "mm_disp_aal1", "mm_sel", 28),98 GATE_MM1(CLK_MM_DISP_OD1, "mm_disp_od1", "mm_sel", 29),99 GATE_MM1(CLK_MM_LVDS1_PIXEL, "mm_lvds1_pixel", "vpll3_dpix", 30),100 GATE_MM1(CLK_MM_LVDS1_CTS, "mm_lvds1_cts", "lvdstx3", 31),101 /* MM2 */102 GATE_MM2(CLK_MM_SMI_LARB7, "mm_smi_larb7", "mm_sel", 0),103 GATE_MM2(CLK_MM_MDP_RDMA3, "mm_mdp_rdma3", "mm_sel", 1),104 GATE_MM2(CLK_MM_MDP_WROT2, "mm_mdp_wrot2", "mm_sel", 2),105 GATE_MM2(CLK_MM_DSI2, "mm_dsi2", "mm_sel", 3),106 GATE_MM2(CLK_MM_DSI2_DIGITAL, "mm_dsi2_digital", "dsi0_lntc", 4),107 GATE_MM2(CLK_MM_DSI3, "mm_dsi3", "mm_sel", 5),108 GATE_MM2(CLK_MM_DSI3_DIGITAL, "mm_dsi3_digital", "dsi1_lntc", 6),109};110 111static const struct mtk_clk_desc mm_desc = {112 .clks = mm_clks,113 .num_clks = ARRAY_SIZE(mm_clks),114};115 116static const struct platform_device_id clk_mt2712_mm_id_table[] = {117 { .name = "clk-mt2712-mm", .driver_data = (kernel_ulong_t)&mm_desc },118 { /* sentinel */ }119};120MODULE_DEVICE_TABLE(platform, clk_mt2712_mm_id_table);121 122static struct platform_driver clk_mt2712_mm_drv = {123 .probe = mtk_clk_pdev_probe,124 .remove = mtk_clk_pdev_remove,125 .driver = {126 .name = "clk-mt2712-mm",127 },128 .id_table = clk_mt2712_mm_id_table,129};130module_platform_driver(clk_mt2712_mm_drv);131 132MODULE_DESCRIPTION("MediaTek MT2712 MultiMedia ddp clocks driver");133MODULE_LICENSE("GPL");134