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1// SPDX-License-Identifier: GPL-2.02/*3 * Copyright (c) 2018 MediaTek Inc.4 * Author: Owen Chen <owen.chen@mediatek.com>5 */6 7#include <linux/clk-provider.h>8#include <linux/platform_device.h>9 10#include "clk-mtk.h"11#include "clk-gate.h"12 13#include <dt-bindings/clock/mt6765-clk.h>14 15static const struct mtk_gate_regs mm_cg_regs = {16 .set_ofs = 0x104,17 .clr_ofs = 0x108,18 .sta_ofs = 0x100,19};20 21#define GATE_MM(_id, _name, _parent, _shift) \22 GATE_MTK(_id, _name, _parent, &mm_cg_regs, _shift, &mtk_clk_gate_ops_setclr)23 24static const struct mtk_gate mm_clks[] = {25 /* MM */26 GATE_MM(CLK_MM_MDP_RDMA0, "mm_mdp_rdma0", "mm_ck", 0),27 GATE_MM(CLK_MM_MDP_CCORR0, "mm_mdp_ccorr0", "mm_ck", 1),28 GATE_MM(CLK_MM_MDP_RSZ0, "mm_mdp_rsz0", "mm_ck", 2),29 GATE_MM(CLK_MM_MDP_RSZ1, "mm_mdp_rsz1", "mm_ck", 3),30 GATE_MM(CLK_MM_MDP_TDSHP0, "mm_mdp_tdshp0", "mm_ck", 4),31 GATE_MM(CLK_MM_MDP_WROT0, "mm_mdp_wrot0", "mm_ck", 5),32 GATE_MM(CLK_MM_MDP_WDMA0, "mm_mdp_wdma0", "mm_ck", 6),33 GATE_MM(CLK_MM_DISP_OVL0, "mm_disp_ovl0", "mm_ck", 7),34 GATE_MM(CLK_MM_DISP_OVL0_2L, "mm_disp_ovl0_2l", "mm_ck", 8),35 GATE_MM(CLK_MM_DISP_RSZ0, "mm_disp_rsz0", "mm_ck", 9),36 GATE_MM(CLK_MM_DISP_RDMA0, "mm_disp_rdma0", "mm_ck", 10),37 GATE_MM(CLK_MM_DISP_WDMA0, "mm_disp_wdma0", "mm_ck", 11),38 GATE_MM(CLK_MM_DISP_COLOR0, "mm_disp_color0", "mm_ck", 12),39 GATE_MM(CLK_MM_DISP_CCORR0, "mm_disp_ccorr0", "mm_ck", 13),40 GATE_MM(CLK_MM_DISP_AAL0, "mm_disp_aal0", "mm_ck", 14),41 GATE_MM(CLK_MM_DISP_GAMMA0, "mm_disp_gamma0", "mm_ck", 15),42 GATE_MM(CLK_MM_DISP_DITHER0, "mm_disp_dither0", "mm_ck", 16),43 GATE_MM(CLK_MM_DSI0, "mm_dsi0", "mm_ck", 17),44 GATE_MM(CLK_MM_FAKE_ENG, "mm_fake_eng", "mm_ck", 18),45 GATE_MM(CLK_MM_SMI_COMMON, "mm_smi_common", "mm_ck", 19),46 GATE_MM(CLK_MM_SMI_LARB0, "mm_smi_larb0", "mm_ck", 20),47 GATE_MM(CLK_MM_SMI_COMM0, "mm_smi_comm0", "mm_ck", 21),48 GATE_MM(CLK_MM_SMI_COMM1, "mm_smi_comm1", "mm_ck", 22),49 GATE_MM(CLK_MM_CAM_MDP, "mm_cam_mdp_ck", "mm_ck", 23),50 GATE_MM(CLK_MM_SMI_IMG, "mm_smi_img_ck", "mm_ck", 24),51 GATE_MM(CLK_MM_SMI_CAM, "mm_smi_cam_ck", "mm_ck", 25),52 GATE_MM(CLK_MM_IMG_DL_RELAY, "mm_img_dl_relay", "mm_ck", 26),53 GATE_MM(CLK_MM_IMG_DL_ASYNC_TOP, "mm_imgdl_async", "mm_ck", 27),54 GATE_MM(CLK_MM_DIG_DSI, "mm_dig_dsi_ck", "mm_ck", 28),55 GATE_MM(CLK_MM_F26M_HRTWT, "mm_hrtwt", "f_f26m_ck", 29),56};57 58static const struct mtk_clk_desc mm_desc = {59 .clks = mm_clks,60 .num_clks = ARRAY_SIZE(mm_clks),61};62 63static const struct of_device_id of_match_clk_mt6765_mm[] = {64 {65 .compatible = "mediatek,mt6765-mmsys",66 .data = &mm_desc,67 }, {68 /* sentinel */69 }70};71MODULE_DEVICE_TABLE(of, of_match_clk_mt6765_mm);72 73static struct platform_driver clk_mt6765_mm_drv = {74 .probe = mtk_clk_simple_probe,75 .remove = mtk_clk_simple_remove,76 .driver = {77 .name = "clk-mt6765-mm",78 .of_match_table = of_match_clk_mt6765_mm,79 },80};81module_platform_driver(clk_mt6765_mm_drv);82 83MODULE_DESCRIPTION("MediaTek MT6765 MultiMedia clocks driver");84MODULE_LICENSE("GPL");85