102 lines · c
1// SPDX-License-Identifier: GPL-2.0-only2/*3 * Copyright (c) 2022 Collabora Ltd.4 * Author: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>5 */6 7#include <dt-bindings/clock/mediatek,mt6795-clk.h>8#include <linux/module.h>9#include <linux/platform_device.h>10#include "clk-gate.h"11#include "clk-mtk.h"12 13#define GATE_MM0(_id, _name, _parent, _shift) \14 GATE_MTK(_id, _name, _parent, &mm0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)15 16#define GATE_MM1(_id, _name, _parent, _shift) \17 GATE_MTK(_id, _name, _parent, &mm1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)18 19static const struct mtk_gate_regs mm0_cg_regs = {20 .set_ofs = 0x0104,21 .clr_ofs = 0x0108,22 .sta_ofs = 0x0100,23};24 25static const struct mtk_gate_regs mm1_cg_regs = {26 .set_ofs = 0x0114,27 .clr_ofs = 0x0118,28 .sta_ofs = 0x0110,29};30 31static const struct mtk_gate mm_gates[] = {32 /* MM0 */33 GATE_MM0(CLK_MM_SMI_COMMON, "mm_smi_common", "mm_sel", 0),34 GATE_MM0(CLK_MM_SMI_LARB0, "mm_smi_larb0", "mm_sel", 1),35 GATE_MM0(CLK_MM_CAM_MDP, "mm_cam_mdp", "mm_sel", 2),36 GATE_MM0(CLK_MM_MDP_RDMA0, "mm_mdp_rdma0", "mm_sel", 3),37 GATE_MM0(CLK_MM_MDP_RDMA1, "mm_mdp_rdma1", "mm_sel", 4),38 GATE_MM0(CLK_MM_MDP_RSZ0, "mm_mdp_rsz0", "mm_sel", 5),39 GATE_MM0(CLK_MM_MDP_RSZ1, "mm_mdp_rsz1", "mm_sel", 6),40 GATE_MM0(CLK_MM_MDP_RSZ2, "mm_mdp_rsz2", "mm_sel", 7),41 GATE_MM0(CLK_MM_MDP_TDSHP0, "mm_mdp_tdshp0", "mm_sel", 8),42 GATE_MM0(CLK_MM_MDP_TDSHP1, "mm_mdp_tdshp1", "mm_sel", 9),43 GATE_MM0(CLK_MM_MDP_CROP, "mm_mdp_crop", "mm_sel", 10),44 GATE_MM0(CLK_MM_MDP_WDMA, "mm_mdp_wdma", "mm_sel", 11),45 GATE_MM0(CLK_MM_MDP_WROT0, "mm_mdp_wrot0", "mm_sel", 12),46 GATE_MM0(CLK_MM_MDP_WROT1, "mm_mdp_wrot1", "mm_sel", 13),47 GATE_MM0(CLK_MM_FAKE_ENG, "mm_fake_eng", "mm_sel", 14),48 GATE_MM0(CLK_MM_MUTEX_32K, "mm_mutex_32k", "clk32k", 15),49 GATE_MM0(CLK_MM_DISP_OVL0, "mm_disp_ovl0", "mm_sel", 16),50 GATE_MM0(CLK_MM_DISP_OVL1, "mm_disp_ovl1", "mm_sel", 17),51 GATE_MM0(CLK_MM_DISP_RDMA0, "mm_disp_rdma0", "mm_sel", 18),52 GATE_MM0(CLK_MM_DISP_RDMA1, "mm_disp_rdma1", "mm_sel", 19),53 GATE_MM0(CLK_MM_DISP_RDMA2, "mm_disp_rdma2", "mm_sel", 20),54 GATE_MM0(CLK_MM_DISP_WDMA0, "mm_disp_wdma0", "mm_sel", 21),55 GATE_MM0(CLK_MM_DISP_WDMA1, "mm_disp_wdma1", "mm_sel", 22),56 GATE_MM0(CLK_MM_DISP_COLOR0, "mm_disp_color0", "mm_sel", 23),57 GATE_MM0(CLK_MM_DISP_COLOR1, "mm_disp_color1", "mm_sel", 24),58 GATE_MM0(CLK_MM_DISP_AAL, "mm_disp_aal", "mm_sel", 25),59 GATE_MM0(CLK_MM_DISP_GAMMA, "mm_disp_gamma", "mm_sel", 26),60 GATE_MM0(CLK_MM_DISP_UFOE, "mm_disp_ufoe", "mm_sel", 27),61 GATE_MM0(CLK_MM_DISP_SPLIT0, "mm_disp_split0", "mm_sel", 28),62 GATE_MM0(CLK_MM_DISP_SPLIT1, "mm_disp_split1", "mm_sel", 29),63 GATE_MM0(CLK_MM_DISP_MERGE, "mm_disp_merge", "mm_sel", 30),64 GATE_MM0(CLK_MM_DISP_OD, "mm_disp_od", "mm_sel", 31),65 66 /* MM1 */67 GATE_MM1(CLK_MM_DISP_PWM0MM, "mm_disp_pwm0mm", "mm_sel", 0),68 GATE_MM1(CLK_MM_DISP_PWM026M, "mm_disp_pwm026m", "pwm_sel", 1),69 GATE_MM1(CLK_MM_DISP_PWM1MM, "mm_disp_pwm1mm", "mm_sel", 2),70 GATE_MM1(CLK_MM_DISP_PWM126M, "mm_disp_pwm126m", "pwm_sel", 3),71 GATE_MM1(CLK_MM_DSI0_ENGINE, "mm_dsi0_engine", "mm_sel", 4),72 GATE_MM1(CLK_MM_DSI0_DIGITAL, "mm_dsi0_digital", "dsi0_dig", 5),73 GATE_MM1(CLK_MM_DSI1_ENGINE, "mm_dsi1_engine", "mm_sel", 6),74 GATE_MM1(CLK_MM_DSI1_DIGITAL, "mm_dsi1_digital", "dsi1_dig", 7),75 GATE_MM1(CLK_MM_DPI_PIXEL, "mm_dpi_pixel", "dpi0_sel", 8),76 GATE_MM1(CLK_MM_DPI_ENGINE, "mm_dpi_engine", "mm_sel", 9),77};78 79static const struct mtk_clk_desc mm_desc = {80 .clks = mm_gates,81 .num_clks = ARRAY_SIZE(mm_gates),82};83 84static const struct platform_device_id clk_mt6795_mm_id_table[] = {85 { .name = "clk-mt6795-mm", .driver_data = (kernel_ulong_t)&mm_desc },86 { /* sentinel */ }87};88MODULE_DEVICE_TABLE(platform, clk_mt6795_mm_id_table);89 90static struct platform_driver clk_mt6795_mm_drv = {91 .driver = {92 .name = "clk-mt6795-mm",93 },94 .id_table = clk_mt6795_mm_id_table,95 .probe = mtk_clk_pdev_probe,96 .remove = mtk_clk_pdev_remove,97};98module_platform_driver(clk_mt6795_mm_drv);99 100MODULE_DESCRIPTION("MediaTek MT6795 MMSYS clocks driver");101MODULE_LICENSE("GPL");102