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1// SPDX-License-Identifier: GPL-2.0-only2/*3 * Copyright (c) 2022 Collabora Ltd.4 * Author: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>5 */6 7#include <dt-bindings/clock/mediatek,mt6795-clk.h>8#include <linux/module.h>9#include <linux/platform_device.h>10#include "clk-gate.h"11#include "clk-mtk.h"12 13#define GATE_VDEC(_id, _name, _parent, _regs) \14 GATE_MTK(_id, _name, _parent, _regs, 0, \15 &mtk_clk_gate_ops_setclr_inv)16 17static const struct mtk_gate_regs vdec0_cg_regs = {18 .set_ofs = 0x0000,19 .clr_ofs = 0x0004,20 .sta_ofs = 0x0000,21};22 23static const struct mtk_gate_regs vdec1_cg_regs = {24 .set_ofs = 0x0008,25 .clr_ofs = 0x000c,26 .sta_ofs = 0x0008,27};28 29static const struct mtk_gate vdec_clks[] = {30 GATE_VDEC(CLK_VDEC_CKEN, "vdec_cken", "vdec_sel", &vdec0_cg_regs),31 GATE_VDEC(CLK_VDEC_LARB_CKEN, "vdec_larb_cken", "mm_sel", &vdec1_cg_regs),32};33 34static const struct mtk_clk_desc vdec_desc = {35 .clks = vdec_clks,36 .num_clks = ARRAY_SIZE(vdec_clks),37};38 39static const struct of_device_id of_match_clk_mt6795_vdecsys[] = {40 { .compatible = "mediatek,mt6795-vdecsys", .data = &vdec_desc },41 { /* sentinel */ }42};43MODULE_DEVICE_TABLE(of, of_match_clk_mt6795_vdecsys);44 45static struct platform_driver clk_mt6795_vdecsys_drv = {46 .probe = mtk_clk_simple_probe,47 .remove = mtk_clk_simple_remove,48 .driver = {49 .name = "clk-mt6795-vdecsys",50 .of_match_table = of_match_clk_mt6795_vdecsys,51 },52};53module_platform_driver(clk_mt6795_vdecsys_drv);54 55MODULE_DESCRIPTION("MediaTek MT6795 vdecsys clocks driver");56MODULE_LICENSE("GPL");57